JP2000012638A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect corrosion of metal wiring and a metal plug formed by the CMP(chemical machine polishing) method during a wafer process. SOLUTION: When Cu wires 36 and 37 connected to pn junctions are formed in a chip formation region of a semiconductor wafer 1, first and second Cu electrodes 38 and 39 connected to the pn junction are also formed in a TEG region. Then, a probe 55 is brought into contact with pads 53 and 54 in connect with the first and second Cu electrodes 38 and 39, and the conduction state between the electrodes is measured, thus judging the degree of corrosion of the Cu wires 36 and 37 formed in the chip region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly, to a method for manufacturing a semiconductor integrated circuit device.
The present invention relates to a technique which is effective when applied to a semiconductor integrated circuit device having metal wiring formed by a mechanical polishing (CMP) method.

[0002]

2. Description of the Related Art In a conventional LSI wiring forming process, a metal film such as an aluminum (Al) alloy film or a tungsten (W) film is deposited on a silicon substrate (wafer) by a sputtering method, and then a photoresist film is formed. In general, the metal film is patterned by dry etching using the mask as a mask.

However, with the recent high integration of LSI,
In the above-described method, the increase in wiring resistance due to the reduction in wiring width becomes remarkable, and particularly in high-performance logic LSIs, it is becoming a major factor impeding the performance. Therefore, recently, for example, “1993 VMIC (VLSI Mul
tilevel Interconnection Conference) Proceedings ", p1
5 to p21, a groove is previously formed in the insulating film on the silicon substrate, and a Cu film having lower electric resistance than Al is deposited on the insulating film including the inside of the groove, An introduction of a Cu wiring forming process (so-called damascene process) in which an unnecessary Cu film outside a groove is polished back by a chemical mechanical polishing (CMP) method and left inside the groove has been advanced.

In the above damascene process, if the width of the groove becomes narrower as the wiring width becomes finer, it becomes difficult to completely bury the Cu film inside the groove. Shu, p. 308-
As described in p314, a technique of reflowing a Cu film deposited by a sputtering method and flowing it into a groove,
For example, Press Journal, November 2, 1997
"Monthly Semiconductor World" p.308
As described in pp. 314 to 314, introduction of a process of forming a Cu film by a CVD method or an electroplating method, which has better step coverage than the sputter-reflow method, is also in progress.

[0005]

In the conventional damascene process, the unnecessary Cu film remaining on the insulating film outside the groove is removed by CM even when the Cu film is formed by any of the above methods.
A step of polishing back by the P method is required. However, when the Cu film is polished by the CMP method, a part of the Cu is eluted by an acid or alkali which is a component in the slurry, so that a part of the wiring is corroded, and an open defect or a short defect may occur. .

[0006] Such corrosion of the Cu wiring is caused by a pn junction (for example, a diffusion resistance element, a MOS transistor) formed on a silicon substrate.
This characteristically occurs in a Cu wiring connected to a source and a drain of a transistor, a collector, a base, and an emitter of a bipolar transistor. Although not as remarkable as Cu wiring, wiring and plugs formed by polishing other metal materials (for example, W, Al alloy, etc.) by the CMP method, when they are connected to the pn junction, Corrosion may occur due to the above reasons.

FIG. 12A is a model diagram showing a mechanism of generating an electromotive force of a pn junction, FIG. 12B is a graph showing IV characteristics of the pn junction at the time of light irradiation and at the time of darkness, and FIG. FIG. 4 is a model diagram showing a corrosion generation mechanism of a Cu wiring.

As shown in FIG. 12A, when light enters a pn junction formed on a silicon substrate, an external voltage (-) is applied on the p-side and-on the n-side due to the photovoltaic effect of silicon.
0.6V), and the IV characteristic of the pn junction shifts as shown in FIG.
Cu wiring connected to the p side (+ side) of the pn junction-pn junction-Cu wiring connected to the n side (-side) of the pn junction-short circuit to a closed circuit formed by polishing slurry attached to the wafer surface A current flows, and Cu ²⁺ ions dissociate from the surface of the Cu wiring connected to the p-side (+ side) of the pn junction, causing electrochemical corrosion (electrolytic corrosion).

FIG. 14 is a graph showing the relationship between the slurry concentration (%) and the etching (elution) rate of Cu when a voltage is applied. As shown in the figure, when the slurry concentration is 100%, the elution rate of Cu is relatively small, but it can be seen that the elution rate rapidly increases when the slurry is diluted to some extent with water.

From the above, it can be said that when light enters the pn junction while the slurry diluted with water is attached to the surface of the silicon wafer, the elution of Cu becomes remarkable, causing corrosion. Specifically, when the slurry attached to the surface of the wafer in the polishing step is diluted with pure water in the subsequent rinsing step or post-cleaning step, or when the wafer stands by between the polishing step and the post-cleaning step, etc. When light enters the pn junction, corrosion of the Cu wiring occurs.

The present inventor has investigated the conditions under which corrosion of the Cu wiring is likely to occur, and as a result, the following has also been found.
This will be described with reference to FIGS. 15 and 16. (1) Corrosion depends on the photocurrent value (Isc) but does not depend on the external voltage value (V) (V> 0).

(2) The photocurrent value increases as the area of the pn junction increases, and in particular, corrosion or the like is likely to occur in wirings and plugs connected to the pn junction having a large area of about 100 μm ² or more (white light of about 700 μm ^2). Looks).

(3) The photocurrent value increases as the external resistance decreases. That is, the resistance of the slurry diluent is usually much larger than the diffusion resistance of the pn junction, but when the distance between the electrodes is short and the liquid resistance is small, the photocurrent value increases and the corrosion is accelerated. become.

Therefore, when the occurrence of wiring corrosion as described above cannot be detected in the middle of the wafer process, the occurrence of corrosion is detected only after the probe inspection performed in the final step of the wafer process. Early improvement in yield is greatly delayed.

An object of the present invention is to provide a technique capable of detecting corrosion of a metal wiring or a metal plug formed by using a CMP method during a wafer process.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

The method for manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps (a) to (e).

(A) forming a plurality of semiconductor elements in a chip region on the main surface of the semiconductor wafer and forming a pn junction in a TEG region on the main surface of the semiconductor wafer; (b) forming a pn junction on the main surface of the semiconductor wafer; Forming an insulating film in the chip region and forming a plurality of grooves in the insulating film in the TEG region; and (c) forming a metal film on the insulating film including the inside of the plurality of grooves. (D) polishing the metal film by a chemical mechanical polishing method to leave the metal film inside the plurality of concave grooves, thereby forming a wiring or a wire electrically connected to the plurality of semiconductor elements in the chip region. A first electrode electrically connected to a p-type semiconductor region forming part of the pn junction in the TEG region, and an n-type semiconductor forming another part of the pn junction in the TEG region Electrically connected to the area Forming a second electrode,
(E) determining a degree of corrosion of the wiring or the plug formed in the chip region based on a conduction state between the first electrode and the second electrode formed in the TEG region. Process.

According to the above means, it is possible to detect the corrosion of the metal wiring and metal plug formed by using the CMP method during the wafer process.
The manufacturing yield of I is improved.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.

MOS-LS according to an embodiment of the present invention
The method of manufacturing I will be described in the order of steps with reference to FIGS. The left part of FIGS. 1 to 7 and FIGS.
The right part shows the chip area.

First, as shown in FIG. 1, a semiconductor wafer 1 made of, for example, p-type single crystal silicon is prepared, and an n-type well 2 and a well 2 are formed on its main surface by well-known ion implantation and selective oxidation (LOCOS). After forming field oxide film 3, the surface of n-type well 2 is thermally oxidized to form gate oxide film 5. In a region (not shown) of the semiconductor wafer 1, p for forming an n-channel MISFET is formed.
Although a mold well is formed, its illustration is omitted.

Next, as shown in FIG. 2, after a gate electrode 6 is formed on the gate oxide film 5 of the n-type well 2, p-type impurities (for example, boron) are added to the n-type well 2 on both sides of the gate electrode 6. ) Is ion-implanted to form a source and a drain (p-type semiconductor region 7).
An ISFET (Qp) is formed. At this time, a p-type impurity (for example) is ion-implanted also into the n-type well 2 in the TEG region to form a p-type semiconductor region 7. Gate electrode 6
Is formed, for example, by depositing a polycrystalline silicon film and a W silicide film on the semiconductor wafer 1 by a CVD method, and then patterning these films by dry etching using a photoresist film as a mask.

Generally, C connected to the p-type semiconductor region 7
Corrosion of the u wiring (described later) is caused by the area of the p-type semiconductor
If it exceeds about 00 μm ² , it will occur remarkably,
As the area of the p-type semiconductor region 7 increases, the degree of corrosion also increases. Therefore, the area of the p-type semiconductor region 7 formed in the n-type well 2 in the TEG region is, for example, at least 100 μm.
It is set in a range from about m ² to a maximum of about 1600 μm ² .
Also preferably, 100, 200, 400, 800, 1
A plurality of p-type semiconductor regions 7 having different areas such as 600 μm ² may be formed in the TEG region.

Next, as shown in FIG.
After a silicon oxide film 8 is deposited thereon by a CVD method, the silicon oxide film 8 is dry-etched using a photoresist film as a mask, thereby forming a p-channel MISFET.
A contact hole 9 is formed above the source and drain (n-type semiconductor region 7) of (Qp), and a contact hole 10 is formed above the n-type well 2 and the p-type semiconductor region 7 in the TEG region.

Next, as shown in FIG. 4, first-layer wirings 11 to 15 are formed on the silicon oxide film 8, and then a silicon oxide film is formed on these wirings 11 to 15 by the CVD method. After the first interlayer insulating film 16 is formed by deposition, through holes 22 to 25 are formed in the interlayer insulating film 16 by dry etching using a photoresist film as a mask. The first layer wirings 11 to 15 are formed, for example, on the silicon oxide film 8 including the insides of the contact holes 9 and 10 by C
After a W film is deposited by a VD method (or a sputtering method), the W film is formed by patterning the W film by dry etching using a photoresist film as a mask.

Next, as shown in FIG.
After a plug 26 is formed inside 2 to 25, a silicon oxide film 21 is deposited on the interlayer insulating film 16 by the CVD method, and a groove 30 is formed in the silicon oxide film 21 by dry etching using a photoresist film as a mask. To 33 are formed.
The plug 26 is formed by depositing a W film on the interlayer insulating film 16 including the insides of the through holes 22 to 25 by a CVD method, and then etching the W film (or polishing by a CMP method).

Next, as shown in FIG.
A Cu film 35 is deposited on the silicon oxide film 21 including the inside by sputtering. When it is difficult to sufficiently bury the Cu film 35 therein by the sputtering method due to the large aspect ratio of the concave grooves 30 to 33, after the Cu film 35 is deposited, the semiconductor wafer 1 is heat-treated. The Cu film 35 may be reflowed so as to flow into the concave grooves 30 to 33. Alternatively, the Cu film 35 may be formed by a CVD method or an electroplating method having better step coverage than the sputtering-reflow method.

Next, as shown in FIG.
By polishing by the MP method, Cu wirings 36 and 37 of the second layer are formed inside the concave grooves 30 and 31 in the chip region, and at the same time, the first Cu electrode 38 is formed inside the concave grooves 32 and 33 in the TEG region. A second Cu electrode 39 is formed.

The smaller the area of the first Cu electrode 38 connected to the p-type semiconductor region 7 in the TEG region, the greater the rate of volume change due to corrosion. That is, the first Cu electrode 3
8 has a higher sensitivity to corrosion as its area is smaller. Therefore, it is desirable that the area of the first Cu electrode 38 be the area of the minimum pattern of the wiring layout rule or an area close thereto. More specifically, in the case of the 0.3 μm wiring width rule, 0.3 × 0.3 = 0.09 μm ² or 0.3 × 0.3.
6 = 0.18 μm ² , 0.5 μm in the case of 0.5 μm wiring width rule
× 0.5 = 0.25 μm ² or 0.5 × 1.0 = 0.50 μ
In the case of the rule of m ² and the wiring width of 1.0 μm, 1.0 × 1.0 = 1.0
μm ² or 1.0 × 2.0 = 2.0 μm ² . On the other hand, T
Second Cu electrode 39 connected to n-type well 2 in the EG region
Means that the liquid resistance (liquid resistance between the first Cu electrode 38) and the like when the slurry adhered to the surface of the semiconductor wafer 1 in the polishing step is diluted with pure water in the subsequent rinsing step or post-cleaning step. In order to reduce the size, the area is made larger (for example, 30 μm ² or more) than the first Cu electrode 38.

The value of the photocurrent flowing between the first Cu electrode 38 connected to the n-type well 2 in the TEG region and the second Cu electrode 39 connected to the p-type semiconductor region 7 depends on the distance between the two electrodes. Shorter is greater. That is, the first Cu electrode 38
The shorter the distance between the electrode and the second Cu electrode 39, the greater the sensitivity to corrosion. Therefore, the first Cu electrode 38 and the second Cu
The electrode 39 is arranged as close as possible (for example, 5 to 1).
(Approximately 20 μm).

When the amount of light applied to the pn junction changes, the photocurrent value changes accordingly. Therefore, when the upper portion of the p-type semiconductor region 7 in the chip region is covered with the first-layer wirings (11 to 13) and the like, the upper portion of the p-type semiconductor region 7 in the TEG region is also in the first layer. It is desirable to cover with the eye wiring (14) and make the amount of light irradiated to the p-type semiconductor region 7 approximately equal between the chip region and the TEG region.

FIG. 8 shows the Cu wirings 36, 3 in the second layer.
7 is a schematic diagram of a CMP apparatus used for forming a first Cu electrode 38 and a second Cu electrode 39. FIG. As shown in the figure, the CMP apparatus has a housing 101 having an open top, and the upper end of a rotating shaft 102 rotatably attached to the housing 101 is rotationally driven by a motor 103. A polishing machine (platen) 104 is attached. A polishing pad 105 formed by uniformly attaching a synthetic resin having a large number of pores is attached to the surface of the polishing board 104.

Further, the CMP apparatus is used for the semiconductor wafer 1
And a wafer carrier 106 for holding the wafer.
A drive shaft 107 to which the wafer carrier 106 is attached is integrated with the wafer carrier 106 to form a motor (not shown).
, And is moved up and down above the polishing plate 104.

The semiconductor wafer 1 is placed in a wafer carrier 106
The main surface, that is, the surface to be polished is turned downward by a vacuum suction mechanism (not shown) provided in the wafer carrier 10.
6 is held. At the lower end of the wafer carrier 106,
A concave portion 106a for accommodating the semiconductor wafer 1 is formed. When the semiconductor wafer 1 is accommodated in the concave portion 106a, the polished surface is substantially the same as or slightly protrudes from the lower end surface of the wafer carrier 106. .

Above the polishing plate 104, a polishing pad 10
A slurry supply pipe 108 for supplying a slurry (S) is provided between the surface of the semiconductor wafer 1 and the surface of the semiconductor wafer 1 to be polished, and the slurry (S) supplied from the lower end of the slurry supply pipe 108 supplies the slurry (S). The polishing surface is chemically polished.

Further, the CMP apparatus has a polishing pad 10
5 is provided with a dresser 109 which is a tool for shaping (dressing) the surface. This dresser 109
It is attached to the lower end of a drive shaft 110 that moves up and down above the polishing plate 104 and is driven to rotate by a motor (not shown).

The dressing is performed after the polishing operation of several semiconductor base wafers 1 is completed or every time the polishing operation of one semiconductor wafer 1 is completed. Alternatively, dressing may be performed simultaneously with polishing. For example, when the semiconductor wafer 1 is pressed against the polishing pad 105 by the wafer carrier 106 and is polished for a predetermined time, the wafer carrier 106 is retracted upward. Next, the dresser 109 moves downward to move the polishing pad 105.
After the surface is dressed for a predetermined time, the dresser 109 is retracted upward. Subsequently, another semiconductor wafer 1 is mounted on the wafer carrier 106, and the above-described polishing step is repeated. After the predetermined number of semiconductor wafers 1 have been polished in this way, the polishing operation is completed by stopping the rotation of the polishing plate 104.

Next, as shown in FIG.
A silicon oxide film is deposited on the wirings 36 and 37, the first Cu electrode 38, and the second Cu
A first interlayer insulating film 40 is formed, and then through holes 41 to 44 are formed in the interlayer insulating film 40 by dry etching using a photoresist film as a mask.
A plug 45 made of a W film is buried in each of 1 to 44.
Subsequently, after depositing a silicon oxide film 46 on the interlayer insulating film 40 by the CVD method, the third-layer Cu wirings 51 and 52 are formed inside the concave grooves 47 to 50 formed in the silicon oxide film 46.
And pads 53 and 54 are formed. Plug 45, third
Cu wirings 51 and 52 and pads 53 and 54 of the layer are
The plug 26 and the Cu wiring 3 of the second layer, respectively.
It is formed by a method similar to that of 6, 37. FIG. 10 is a plan view showing a layout of the pads 53 and 54, the first Cu electrode 38, and the second Cu electrode 39 formed in the TEG region.

Thereafter, as shown in FIG. 11, a probe 55 is applied to the pads 53 and 54 formed in the TEG region to measure the conduction state. At this time, if the second-layer Cu wirings 36 and 37 formed in the chip region are corroded, the first Cu electrode 38 formed in the TEG region is also corroded. The pads 53 and 54 are open (non-conductive). Further, even when the first Cu electrode 38 has not completely disappeared due to corrosion, the degree of corrosion can be determined by an increase in resistance value as compared with a normal case.

As described above, according to the present embodiment, the CM
The corrosion of the Cu wirings 36 and 37 formed by using the P method
Since detection can be performed in the middle of the wafer process, it is possible to extract the semiconductor wafer 1 in which the wiring corrosion has occurred in the middle of the wafer process.
Can be improved at an early stage.

When there are many (for example, four or more) wiring layers, the first Cu electrode 38 and the second
A Cu electrode 39 is formed for each wiring layer, and a first Cu electrode 38 and a second C
By measuring the continuity state with the u electrode 39,
Since it is possible to specify whether corrosion occurs in the MP process, it is possible to improve and stabilize the process.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

The region where the electrode for detecting the corrosion of the wiring is disposed is not limited to the TEG region. If there is a space for disposing the electrode inside the chip region, it may be disposed there.

The present invention can also be applied to a so-called dual damascene process in which a Cu film is simultaneously buried in a concave groove and a through hole formed in an insulating film to simultaneously form a Cu wiring and a Cu plug. Further, the present invention can be applied to a case where a wiring or a plug is formed of a metal material other than Cu.

[0047]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, corrosion of a metal wiring or a metal plug formed by using the CMP method can be detected during the wafer process. That is, which CMP
It is possible to detect whether or not corrosion occurs in the process, and this information can be used for failure analysis. In particular, the reliability of high-speed LSIs that form wiring and plugs using corrosive metal materials such as Cu In addition, the production yield can be improved.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor wafer showing a method for manufacturing a MOS-LSI according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor wafer showing a method for manufacturing a MOS-LSI according to an embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of a semiconductor wafer showing a method for manufacturing a MOS-LSI according to an embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of a semiconductor wafer showing a method for manufacturing a MOS-LSI according to an embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of a semiconductor wafer showing a method for manufacturing a MOS-LSI according to an embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of a semiconductor wafer showing a method for manufacturing a MOS-LSI according to an embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of a semiconductor wafer showing a method for manufacturing a MOS-LSI according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a CMP apparatus used for manufacturing a MOS-LSI according to an embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of a semiconductor wafer showing a method for manufacturing a MOS-LSI according to an embodiment of the present invention;

FIG. 10 shows a MOS-LSI according to an embodiment of the present invention.
FIG. 5 is a plan view showing a layout of pads, first Cu electrodes, and second Cu electrodes formed in a TEG region of FIG.

FIG. 11 is a MOS-LSI according to an embodiment of the present invention;
FIG. 13 is a cross-sectional view of a main part of a semiconductor wafer, illustrating a method for manufacturing the same.

12A is a model diagram showing a mechanism of generating an electromotive force of a pn junction, and FIG.
5 is a graph showing V characteristics.

FIG. 13 is a model diagram showing a corrosion generation mechanism of a Cu wiring.

FIG. 14 shows slurry concentration (%) and Cu
4 is a graph showing a relationship between the etching (elution) rate and the etching speed.

FIG. 15 is a graph showing a correlation between pn junction area and open circuit voltage and corrosion.

FIG. 16 is a graph showing a correlation between a pn junction area, a short-circuit current, and corrosion.

[Explanation of symbols]

 Reference Signs List 1 semiconductor wafer 2 n-type well 3 field oxide film 5 gate oxide film 6 gate electrode 7 p-type semiconductor region (source, drain) 8 silicon oxide film 9, 10 contact hole 11 to 15 first layer wiring 16 first layer Second interlayer insulating film 21 Silicon oxide film 22-25 Through hole 26 Plug 30-33 Groove 35 Cu film 36, 37 Cu wiring of second layer 38 First Cu electrode 39 Second Cu electrode 40 Second layer interlayer insulation Films 41 to 44 Through holes 45 Plugs 46 Silicon oxide films 47 to 50 Concave grooves 51, 52 Third-level Cu wiring 53, 54 Pads 55 Probes 101 Housing 102 Rotating shaft 103 Motor 104 Polishing machine (platen) 105 Polishing pad 106 wafer carrier 106a recess 107 drive shaft 108 slurry supply pipe 109 drain Sa 110 drive shaft S slurry Qp p-channel type MISFET R terminator resistor

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideaki Nonami 6-16-16 Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Naofumi Ohashi 6--16 Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Device Development Center (72) Inventor Nobuo Owada 6-16, Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Device Development Center (72) Inventor Yoshio Honma 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Address: Central Research Laboratory, Hitachi, Ltd. (72) Kenji Hino, Inventor 1-280 Higashi Koigabo, Kokubunji-shi, Tokyo (72) Central Research Laboratory, Hitachi, Ltd. (72) Toshiyuki Kikuchi 6-16, Shinmachi, Omachi, Tokyo F-ter in Hitachi, Ltd. Device Development Center (Reference) 4M106 AA07 AA11 AB15 AB17 AD01 AD09 BA01 CA10 CA56 5F033 AA02 AA05 AA13 BA15 BA17 CA11 DA04 DA15 DA34 EA02 EA23

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) forming a plurality of semiconductor elements in a chip region on a main surface of a semiconductor wafer; Forming a pn junction in a TEG region, (b) forming an insulating film on the main surface of the semiconductor wafer, and then forming a plurality of grooves in the insulating film in the chip region and the TEG region;
(C) forming a metal film on the insulating film including the inside of the plurality of grooves; (d) polishing the metal film by a chemical mechanical polishing method to leave the inside of the plurality of grooves. Accordingly, a wiring or a plug electrically connected to the plurality of semiconductor elements is formed in the chip region, and the peg-type semiconductor region constituting a part of the pn junction is electrically connected to the TEG region. Forming a first electrode, and a second electrode electrically connected to an n-type semiconductor region forming another part of the pn junction, (e) forming the TEG.
A step of determining a degree of corrosion of the wiring or the plug formed in the chip region based on a conduction state between the first electrode and the second electrode formed in the region. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said metal film contains at least copper. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein an area of said first electrode electrically connected to said p-type semiconductor region is electrically connected to said n-type semiconductor region. A method of manufacturing a semiconductor integrated circuit device, wherein the area is smaller than the area of the second electrode connected to the semiconductor integrated circuit device. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein a plurality of said pn junctions having different areas are formed in said TEG region. . 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first integrated circuit device is formed in said TEG region.
And disposing the second electrode and the second electrode in close proximity to each other. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said wiring or said plug, said first electrode and said second electrode are formed in a plurality of wiring layers, and A method of manufacturing a semiconductor integrated circuit device, comprising: measuring a conduction state between the first electrode and the second electrode each time the wiring or the plug is formed in the wiring layer. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the wiring or the plug is electrically connected to a p-type semiconductor region forming a part of the semiconductor element. A method for manufacturing a semiconductor integrated circuit device, comprising: