CN103647801A - Data collector applied to real-time quality monitoring at traditional industrial site - Google Patents
Data collector applied to real-time quality monitoring at traditional industrial site Download PDFInfo
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- CN103647801A CN103647801A CN201310581660.9A CN201310581660A CN103647801A CN 103647801 A CN103647801 A CN 103647801A CN 201310581660 A CN201310581660 A CN 201310581660A CN 103647801 A CN103647801 A CN 103647801A
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Abstract
The invention discloses a data collector applied to real-time quality monitoring at a traditional industrial site. The data collector includes a data acquisition circuit, a data transmission circuit and a communication protocol conversion circuit, wherein the data acquisition circuit and the transmission circuit comprise at least two data acquisition or transmission modes and the communication protocol conversion circuit is capable of automatic communication protocol conversion according to the data acquisition or transmission modes, so that various data acquisition or transmission modes can be compatible and real-time delivery of data in the Internet of Things is better achieved.
Description
Technical field
The present invention relates to technology of Internet of things field, relate more specifically to a kind of data acquisition unit that is applied to the on-the-spot quality monitoring in real time of traditional industry.
Background technology
The fast development of Internet of Things, has higher requirement to data acquisition equipment, especially aspect the on-the-spot monitoring in real time of traditional industry, higher to the requirement of data acquisition equipment.Current, in countries in the world, be engaged in the developmental research of data acquisition and series of products thereof, the producer of production and operation reaches several thousand, nearly ten thousand kinds of the kinds of product, are widely used in the data acquisition of industry control.
Yet data acquisition interface that at present product is on the market supported is comparatively single, data acquisition transmission means is also very limited, has seriously hindered advancing of Internet of Things.
Therefore, be badly in need of a kind of data acquisition unit that is applied to the on-the-spot quality monitoring in real time of traditional industry and overcome above-mentioned defect.
Summary of the invention
The object of this invention is to provide a kind of data acquisition unit that is applied to the on-the-spot quality monitoring in real time of traditional industry, to realize the compatibility of several data acquisition mode and data transfer mode, thereby better in Internet of Things, carry out the real-time transmission of data.
For achieving the above object, the invention provides a kind of data acquisition unit that is applied to the on-the-spot quality monitoring in real time of traditional industry, comprise communication Protocol Conversion circuit and the data acquisition circuit and the data transmission circuit that are connected with described communication Protocol Conversion circuit, described data acquisition circuit comprises at least two kinds of cable data acquisition interface circuit, described data transmission circuit comprises at least two kinds of Wireless Data Transmission interface circuits, and described communication Protocol Conversion circuit is according to the acquisition mode of data and the automatic converts communications agreement of transmission means.
Compared with prior art, the data acquisition unit that the present invention is applied to the on-the-spot quality monitoring in real time of traditional industry comprises data acquisition circuit, data transmission circuit and communication Protocol Conversion circuit, wherein data acquisition circuit and data transmission circuit comprise that at least two kinds gather or transmission means, communication Protocol Conversion circuit can be according to data acquisition or the automatic converts communications agreement of transmission means, thereby make several data acquisition mode and the data transfer mode can be compatible, better realized the real-time transmission of data in Internet of Things.
Preferably, described cable data acquisition interface circuit comprises usb circuit, RS232 interface circuit, RS485 interface circuit, ethernet interface circuit and CAN bus interface circuit.
Preferably, described Wireless Data Transmission interface circuit comprises GPRS interface circuit, WIFI interface circuit, Zigbee interface circuit and RFID interface circuit.
Preferably, the data acquisition unit that is applied to the on-the-spot quality monitoring in real time of traditional industry described in also comprises memory circuit and the power circuit being connected with described communication Protocol Conversion circuit.
Preferably, described communication Protocol Conversion circuit is specially FPGA and controls change-over circuit.
Preferably, described RS232 interface circuit comprises single supply level transferring chip U11, interface RS1 and interface RS232, the pin 11,12 of described single supply level transferring chip U11 is connected with described communication Protocol Conversion circuit, the pin 14 of described single supply level transferring chip U11 is connected with pin 2 and the RS1 of interface RS232, and the pin 13 of described single supply level transferring chip U11 is connected with pin 3 and the RS1 of interface RS232.
Preferably, described CAN bus interface circuit comprises CAN bus control chip U13, CAN bus transceiver U14, CAN bus protection chip U12 and socket P19, the pin 7 of described CAN bus transceiver U14, 6 respectively with the pin 1 of socket P19, pin 2 connects, the pin 7 of described CAN bus transceiver U14, 6 respectively with the pin 2 of described CAN bus protection chip U12, pin 1 connects, the pin 1 of described CAN bus transceiver U14, 4 respectively with the pin 1 of described CAN bus control chip U13, 2 connect, described CAN bus transceiver U14 is by pin 7, 6 are connected with described communication Protocol Conversion circuit.
Preferably, described Zigbee interface circuit comprises control chip CC2530, socket JP1 and socket JP2, the pin 4,5,6,9,10,11,12,13,14 of described socket JP1 is connected with the pin 34,35,36,5,6,7,8,9,11 of described control chip CC2530 respectively, described socket JP1 is connected with described communication Protocol Conversion circuit by pin 7,8, and the pin 3,5,6,7,8,9,10,11,12 of described socket JP2 is connected with the pin 20,19,18,17,16,15,14,13,12 of described control chip CC2530 respectively.
Preferably, described RFID interface circuit comprises RFID read-write chip U10 and socket J5, the pin 31,30,29 of described RFID read-write chip U10 is connected with the pin 3,4,5 of described socket J5 respectively, the pin 6 of described RFID read-write chip U10 is connected with the pin 1 of described socket J5 and 3V power supply, the pin 24 of described RFID read-write chip U10 is connected with the pin 6 of socket J5, and the pin 3,4,5,6 of described socket J5 is connected with described communication Protocol Conversion circuit.
Preferably, described usb circuit comprises 2 hole contact pin P17, USB-B-R chip, capacitor C 98, resistance R 64, R62, R67 and transistor Q2, one end after described capacitor C 98 and resistance R 64 parallel connections is connected with the pin 0 of described USB-B-R chip, other end ground connection, the pin 1 of described USB-B-R chip is connected with the pin 1 of described contact pin P17, the pin 2 of contact pin P17 connects 5V power supply, the pin 2 of described USB-B-R chip, 3 are connected with described communication Protocol Conversion circuit, the pin 3 of described USB-B-R chip is connected with one end of resistance R 62, the other end of resistance R 62 is connected with the collector electrode of transistor Q2, the emitter of transistor Q2 connects 3.3V power supply, the base stage of transistor Q2 is connected with one end of resistance R 67, the other end of resistance R 67 forms port PC13, port PC13 is connected with described communication Protocol Conversion circuit.
By following description also by reference to the accompanying drawings, it is more clear that the present invention will become, and these accompanying drawings are used for explaining embodiments of the invention.
Accompanying drawing explanation
Fig. 1 is the structured flowchart that the present invention is applied to data acquisition unit one embodiment of the on-the-spot quality monitoring in real time of traditional industry.
Fig. 2 be the present invention be applied to the on-the-spot quality monitoring in real time of traditional industry data acquisition unit by the schematic diagram of RS232 interface image data, USB interface uploading data.
Fig. 3 is the circuit diagram of usb circuit 121 in Fig. 1.
Fig. 4 is the circuit diagram of RS232 interface circuit 122 in Fig. 1.
Fig. 5 is the circuit diagram of RS485 interface circuit 123 in Fig. 1.
Fig. 6 is the circuit diagram of ethernet interface circuit 124 in Fig. 1.
Fig. 7 is the circuit diagram of CAN bus interface circuit 125 in Fig. 1.
Fig. 8 is the circuit diagram of GPRS interface circuit 141 in Fig. 1.
Fig. 9 is the circuit diagram of WIFI interface circuit 142 in Fig. 1.
Figure 10 is the circuit diagram of Zigbee interface circuit 143 in Fig. 1.
Figure 11 is the circuit diagram of RFID interface circuit 144 in Fig. 1.
Figure 12 is the circuit diagram of communication Protocol Conversion circuit 10 in Fig. 1.
Figure 13 is the circuit diagram of memory circuit 16 in Fig. 1.
Figure 14 is the circuit diagram of power circuit 17 in Fig. 1.
Figure 15 is the circuit diagram that Fig. 1 Program writes interface circuit 18.
Embodiment
With reference now to accompanying drawing, describe embodiments of the invention, in accompanying drawing, similarly element numbers represents similar element.
Please refer to Fig. 1, described the structured flowchart that the present invention is applied to data acquisition unit one embodiment of the on-the-spot quality monitoring in real time of traditional industry.As shown in Figure 1, the data acquisition unit 100 that is applied to the on-the-spot quality monitoring in real time of traditional industry comprises:
Communication Protocol Conversion circuit 10, data acquisition circuit 12 and data transmission circuit 14.Wherein, communication Protocol Conversion circuit 10 is specially FPGA and controls change-over circuit, data acquisition circuit 12 is for connecting communication Protocol Conversion circuit 10 and outside data acquisition equipment, with by the transfer of data arriving gathering to communication Protocol Conversion circuit 10, data acquisition circuit 12 comprises at least two kinds of cable data acquisition interface circuit, in the present embodiment, data acquisition circuit 12 comprises usb circuit 121, RS232 interface circuit 122, RS485 interface circuit 123, ethernet interface circuit 124 and CAN bus interface circuit 125, usb circuit 121 is corresponding to USB interface, by USB interface, transmit data, RS232 interface circuit 122 is corresponding to RS232 interface, by RS232 interface transmission data, in like manner, known RS485 interface circuit 123, ethernet interface circuit 124 and CAN bus interface circuit 125, data transmission circuit 14 comprises at least two kinds of Wireless Data Transmission interface circuits, and in the present embodiment, data transmission circuit 14 comprises GPRS interface circuit 141, WIFI interface circuit 142, Zigbee interface circuit 143 and RFID interface circuit 144.Communication Protocol Conversion circuit 10 is for automatically communicating the conversion of agreement according to the input interface of data, output interface and transmission means, wherein the input interface of data, output interface are USB interface, RS232 interface, RS485 interface, Ethernet interface or CAN bus interface arbitrarily.In addition, device 100 also comprises that memory circuit 16, power circuit 17 and program write interface circuit 18, memory circuit 16 is for storing the program that writes or the data of collection, and power circuit 17 is used to communication Protocol Conversion circuit 10, data acquisition circuit 12 and data transmission circuit 14 that working power is provided.
In the present embodiment, device 100 is used integrated ARM mainboard, and application embedded OS can compatible windows and linus operating system.Device 100 is supported multiple wired data acquisition modes, as: the modes such as RS232, RS485, MPI, DP, USB, Ethernet interface, PLC, and multiple wireless data transfer mode, as GPRS, Zigbee, RFID, bluetooth, WIFI, 3G etc.Between different data transfer modes, can realize the automatic conversion of communication protocol, by protocol conversion, transmission data can be converted to the form needing, thereby realize the transfer of data of Internet of Things.Wherein, communication protocol automatically conversion is specially: the communication protocol of storing various interface by protocol stack, protocol stack receives after data data flow by analysis, thereby contrast with the communication protocol of various interface, and then judge the data stream interface pattern of reception, and according to the output interface pattern detecting, contrast its communication protocol and change, complete automatic transfer process.
Take " RS232 interface image data, USB interface are exported data " below as example illustrates the communication protocol process of conversion automatically, comprise the following steps:
(1) determine input interface and output interface, the interface that in the present invention, first definition accesses is input interface, and secondly interface of access is output interface; In the present embodiment, input interface is that RS232 interface, output interface are USB interface (as shown in Figure 2);
(2) process input traffic, the data of RS232 interface collection send fpga chip (fpga chip in communication Protocol Conversion circuit 10) to and process, in FPGA, embedded the Nios-II kernel of 32, an and built-in protocol stack, first protocol stack extracts RS232 data flow, receives one by one, and analyze its data format by transmitting the data of coming in, then storage, waits for the connection of output interface;
(3) determine output interface pattern and complete automatic conversion; After output interface is connected, FPGA determines output interface pattern by send frame detection data to each interface, in this example, output interface is USB interface, therefore send and detect after data, only have USB interface return data, FPGA kernel just can determine that output interface pattern is USB interface, determine after output interface, fpga chip is converted to the data of storage the data flow of USB transformat, then transmits, thereby completed the process that RS232 interface is automatically converted to USB interface.
In like manner, when Wireless Data Transmission modes such as adopting WIFI, bluetooth is carried out transfer of data, also can communicate by communication Protocol Conversion circuit 10 conversion of agreement, thereby realize support several data acquisition mode and data transfer mode.
As can be seen from the above description, device 100 is connected to collecting device by various interface circuit, then the data upload each equipment being collected is to master station computer or server, possess Real-time Collection, autostore, immediate feedback, automatically process, self-propagating function, thereby provide assurance for authenticity, validity, real-time, the availability of field data.
Please refer to Fig. 3, described the circuit diagram of usb circuit 121 in Fig. 1.As shown in Figure 3, usb circuit 121 comprises 2 hole contact pin P17, USB-B-R chip, capacitor C 98, resistance R 64, R62, R67 and transistor Q2, wherein the model of transistor Q2 is 8550, and capacitor C 98 is 10pF, and resistance R 64 is that 1M Ω, R62 are that 1k Ω, R67 are 10k Ω.
Particularly, one end after capacitor C 98 and resistance R 64 parallel connections is connected with the pin 0 of USB-B-R chip, other end ground connection, the pin 1 of USB-B-R chip is connected with the pin 1 of contact pin P17, the pin 2 of contact pin P17 connects 5V power supply, the pin 2(PA11 of USB-B-R chip), 3(PA12) respectively with the pin 106 of fpga chip, 110 connect, the pin 3(PA12 of USB-B-R chip) be connected with one end of resistance R 62 simultaneously, the other end of resistance R 62 is connected with the collector electrode of transistor Q2, the emitter of transistor Q2 connects 3.3V power supply, the base stage of transistor Q2 is connected with one end of resistance R 67, the other end of resistance R 67 forms port PC13, port PC13 is connected with the pin 111 of fpga chip.
Please refer to Fig. 4, described the circuit diagram of RS232 interface circuit 122 in Fig. 1.As shown in Figure 4, RS232 interface circuit 122 comprises required resistance, the electric capacity of peripheral circuit of single supply level transferring chip U11, interface RS1, interface RS232 and single supply level transferring chip U11.Wherein single supply level transferring chip U11 is specially MAX232, and its peripheral circuit comprises resistance R 57, capacitor C 73, C77, C63, C74 and C86.Particularly, interface RS232 is nine needles serial port, and capacitor C 73, C77, C63, C74 and C86 are 100nF.
Wherein MAX232 chip is the single supply level transferring chip that U.S. letter (MAXIM) company aims at the design of rs-232 standard serial ports, use+5v single power supply.MAX232 chip mainly comprises three parts: first is charge pump circuit, by 1,2,3,4,5,6 pin and 4 electric capacity, formed, function be generation+12v and-two power supplys of 12v, offer the needs of RS-232 serial ports level; Second portion is data transaction passage, by 7,8,9,10,11,12,13,14 pin, form two data channel, wherein 13 pin (R1IN), 12 pin (R1OUT), 11 pin (T1IN), 14 pin (T1OUT) are the first data channel, 8 pin (R2IN), 9 pin (R2OUT), 10 pin (T2IN), 7 pin (T2OUT) are the second data channel, and TTL/CMOS data convert RS-232 data to and deliver to computer DB9 plug from 14 pin (T1OUT), 7 pin (T2OUT) from 11 pins (T1IN), 10 pins (T2IN) input; The RS-232 data of DB9 plug are exported from 12 pins (R1OUT), 9 pins (R2OUT) from 13 pins (R1IN), 8 pins (R2IN) input convert TTL/CMOS data to.Third part is power supply, 15 pin GND, 16 pin VCC(+5v).
Particularly, in the present embodiment, use the first data channel of MAX232, the pin 11(2-R of MAX232) with the pin 71(2-R of fpga chip) be connected, the pin 12 of MAX232 is the pin 72(2-T with fpga chip by resistance R 57) be connected, the pin 14 of MAX232 is connected with pin 2 and the RS1 of RS232, and the pin 13 of MAX232 is connected with pin 3 and the RS1 of RS232.In addition, pin 1 and the pin 3 of MAX232 link together by capacitor C 73, pin 4 and the pin 5 of MAX232 link together by capacitor C 77, the pin 2 of MAX232 is connected with one end of capacitor C 63, the other end of capacitor C 63 is connected with the pin of MAX232 16 and 3.3V power supply, the pin 16 of MAX232 passes through capacitor C 74 ground connection, pin 15 ground connection of MAX232, and the pin 16 of MAX232 is by capacitor C 86 ground connection.
During work, the TTL/CMOS data that equipment collects convert to RS-232 data from 11 pins (T1IN) input, deliver to the DB9 plug of computer from 14 pin (T1OUT); The RS-232 data of DB9 plug are from 13 pins (R1IN) inputs, export after converting TTL/CMOS data to from 12 pins (R1OUT).
Please refer to Fig. 5, described the circuit diagram of RS485 interface circuit 123 in Fig. 1.As shown in Figure 5, RS485 interface circuit 123 comprises socket P15, chip U15, interface RS2, resistance R 46, resistance R 63, resistance R 68, resistance R 71 and capacitor C 99.Its chips U15 is specially SP3485, and resistance R 46, R68 are 10k Ω, and capacitor C 99 is 100nF.
SP3485 is+half-duplex RS 485 transceivers of 3.3V power supply, meet RS-485 and RS-422 serial protocol standard, message transmission rate can be up to 100Mbps(bringing onto load).SP3485 adopts difference input, the balance way of output, and output, input share a pair of circuit, and its pin function is as follows: pin A is in-phase end, pin B is end of oppisite phase, and pin R0 is receiver output, and pin DI is transmitter input, pin RE is receiver output enable end, and pin DE is transmitter output enable end.
Particularly, in the present embodiment the pin 1 of SP3485 by resistance R 63 the pin 69(4-T with fpga chip) be connected, the pin 4 of SP3485 and the pin 70(4-R of fpga chip) be connected, the pin 2 of SP3485, the pin 68(PB2 of pin 3 and fpga chip) be connected, wherein the pin 3 of SP3485 is by resistance R 68 ground connection, pin 5 ground connection of SP3485, the pin 6 of SP3485 is connected with one end and the RS2 of resistance R 71, the pin 7 of SP3485 and the other end of resistance R 71 are connected with RS, the pin 8 of SP3485 is connected with one end of 3.3V power supply and capacitor C 99, the other end ground connection of capacitor C 99, the pin 3 of socket P15 is connected with 3.3V power supply, the pin 2 of socket P15 is connected with one end of resistance R 46, the pin 68(PB2 of the other end of resistance R 46 and fpga chip) and the pin 2 of SP3485, pin 3 connects, pin 1 ground connection of socket P15.During work, by the pin 68(PB2 of FPGA) select the transmission direction of data, by pin 4-T, pin 4-R transmitting serial data, RS-485 has 2 holding wires: sending and receiving is all A and B.Because the receipts of RS-485 are to share two lines with sending out, so can not receive and send out (half-duplex) simultaneously, can only receive separately data or transmission data.
During work, computer, by RS232, RS485 transducer, connects many 485 equipment successively, and the equipment in bus is carried out to communication.
Please refer to Fig. 6, is the circuit diagram of ethernet interface circuit in Fig. 1 124.As shown in Figure 6, ethernet interface circuit 124 comprises ethernet controller U9, interface J4, some resistance, electric capacity, inductance and crystal oscillator.In the present embodiment, ethernet controller U9 is specially ENC28J60, interface J4 is specially RJ45, in the present embodiment, RJ45 is the DTE type for ethernet nic, router, Ethernet interface etc., I can be called " data terminal equipment " DTE, from certain meaning, DTE equipment is " active communication equipment ", and RJ45 always has 14 pins.
Particularly, the pin 4(PA1 of ethernet controller ENC28J60), 6(PA6), 7(PA7), 8(PA5), 9(PA4), 10(PE1) be connected with the pin 75,76,77,80,83,84 of fpga chip respectively, the pin 27,26 of ethernet controller ENC28J60 is connected with the pin 9,12 of interface RJ45 respectively, in addition, the pin 1 of ethernet controller ENC28J60 is by capacitor C 56 ground connection, the pin 2 of ethernet controller ENC28J60, 11, 18, 21, 22 ground connection, the pin 12 of ethernet controller ENC28J60, 13 respectively with resistance R 50, one end of R51 connects, resistance R 50, the other end of R51 is connected with one end of capacitor C 61, the other end ground connection of capacitor C 61, and the pin 14 of ethernet controller ENC28J60 is by resistance R 53 ground connection, the pin 15 of ethernet controller ENC28J60 connects 3.3V power supply, the pin 16 of ethernet controller ENC28J60, 17 respectively with resistance R 52, one end of R49 connects, resistance R 52, the other end of R49 is connected with one end of capacitor C 60 and one end of inductance L 6, another termination 3.3V power supply of inductance L 6, the other end ground connection of capacitor C 60, the pin 19 of ethernet controller ENC28J60, 20, 25, 28 connect 3.3V power supply, the pin 23 of ethernet controller ENC28J60, 24 connect clock circuit, and clock circuit is by capacitor C 57, capacitor C 59 and crystal oscillator Y3 form, and as shown in Figure 6, in addition, the pin 28 of ethernet controller ENC28J60 is also connected with filter capacitor C55 to annexation, the pin 4 of interface RJ45, pin 5 are connected with one end of capacitor C 62, C72 respectively, the other end ground connection of capacitor C 62, C72, the pin 10,11 of interface RJ45 is connected with one end of resistance R 55, R54 respectively, the other end ground connection of resistance R 55, R54, pin 8,13,14 ground connection of interface RJ45.
Wherein, backbone network adopts the Industrial Ethernet technology of 100M, can guarantee that each is monitored, monitor message is carried out high-speed transfer and exchange, guarantees the real-time of system.Backbone network has redundancy when design, and equipment has error correcting capability, has flexibility and extensibility, has guaranteed high reliability, can also support multiple network agreement simultaneously.
Wherein capacitor C 55 is 10pF, and capacitor C 56, C62, C72 are 10uF, and capacitor C 57, C59 are 20pF, and crystal oscillator Y3 is 25MHz, and inductance L 6 is 100uH.
Please refer to Fig. 7, is the circuit diagram of CAN bus interface circuit 125 in Fig. 1.As shown in Figure 7, CAN bus interface circuit 125 comprises CAN bus control chip U13, CAN bus transceiver U14, CAN bus protection chip U12, socket P19 and capacitor C 104, C106, crystal oscillator Y6, resistance R 70.In the present embodiment, CAN bus control chip U13 is MCP2515, and CAN bus transceiver U14 is TJA1050, and CAN bus protection chip U12 is PESN1CAN, and socket P19 is 2 spring hole scokets, and capacitor C 104, C106 are 30pF, and crystal oscillator Y6 is 16MHz.CAN is the serial communication protocol of ISO International standardization, has high-performance and reliability, and is widely used in the aspects such as industrial automation, boats and ships, Medical Devices, industrial equipment.CAN bus is real-time between each node for dcs realizes, data communication reliably provides strong technical support.
Particularly, the pin 7(CANH of CAN bus transceiver TJA1050), 6(CANL) respectively with the pin 1 of socket P19, pin 2 connects, the pin 1 of socket P19, parallel resistance R24 between pin 2, meanwhile, the pin 7(CANH of CAN bus transceiver TJA1050), 6(CANL) respectively with the pin 2 of CAN bus protection chip PESN1CAN, pin 1 connects, to play the effect of route protection, and the pin 1 of CAN bus transceiver TJA1050, 4 respectively with the pin 1(TXCAN of CAN bus control chip MCP2515), 2(RXCAN) connect the pin 1 of CAN bus control chip MCP2515, 2 simultaneously with the pin 85 of fpga chip, 86 connect, capacitor C 104, C106 and crystal oscillator Y6 form the clock circuit of CAN bus control chip MCP2515 and pass through the pin 7 of CAN bus control chip MCP2515, 8 for it provides clock, and the pin 18 of CAN bus control chip MCP2515 connects 3.3V power supply, the pin 2 of CAN bus transceiver TJA1050, 8 and pin 3 ground connection of CAN bus protection chip PESN1CAN, CAN bus transceiver TJA1050 is by pin 7, 6 with the pin 112 of fpga chip, 113 connect.
Please refer to Fig. 8, described the circuit diagram of GPRS interface circuit 141 in Fig. 1.As shown in Figure 8, GPRS interface circuit 141 comprises gsm module U1, wireless module U4, antennal interface CN1, SIM interface CN2, Strobe Controller U5, battery B2 and several resistance, electric capacity, diode, switch.In the present embodiment, wireless module U4 is specially SIM900, and SIM interface CN2 is specially SIMCARD-6, and Strobe Controller U5 is specially SMF05C.
Particularly, the pin 9(PB11 of gsm module U1), 10(PB10) be connected with the pin 115,114 of fpga chip respectively, between the pin 10 of gsm module U1 and pin 15, be connected with resistance R 11, pin 55,56,57 ground connection of gsm module U1, the pin 1 of wireless module SIM900, between 2, be connected with switch S 1, the pin 9(GSM-TXD of wireless module SIM900), 10(GSM-RXD) respectively with the pin 104 of fpga chip, 105 connect, and the pin 16 of wireless module SIM900 is by the rear ground connection of capacitor C 15, the pin 17 of wireless module SIM900, 18, 29, 39, 45, 46 ground connection, the pin 26 of wireless module SIM900 is connected with the positive pole of battery B1, the minus earth of battery B1, the pin 30 of wireless module SIM900 and one end of resistance R 13, the pin 6 of SIMCARD-6 and the pin of SMF05C 4 connect, the other end of resistance R 13 is by capacitor C 18 ground connection, the pin 31 of wireless module SIM900 is connected with one end of the other end of resistance R 13 and resistance R 14, the other end of resistance R 14 is connected with the pin 1 of the pin of SIMCARD-6 3 and SMF05C, the pin 32 of wireless module SIM900 is connected with one end of resistance R 15, the other end of resistance R 15 is connected with the pin 6 of the pin of SIMCARD-6 4 and SMF05C, the pin 33 of wireless module SIM900 is connected with the other end of resistance R 16, the other end of resistance R 16 is connected with the pin 5 of the pin of SIMCARD-6 5 and SMF05C, pin 1 ground connection of SIMCARD-6, the pin 6 of SIMCARD-6 is also connected with filter capacitor C17, pin 2 ground connection of SMF05C, the pin 52(NET_LIGHT of wireless module SIM900) by resistance R 1, be connected with the positive pole of light-emitting diode D2, the minus earth of light-emitting diode D2, the pin 53 of wireless module SIM900, 54, 58, 59, 61, 62, 63, 64, 65 ground connection, the pin 55 of wireless module SIM900, 56, 57 with capacitor C 3, C4, C5, one end of C6 connects, capacitor C 3, C4, C5, the other end ground connection of C6, the pin 60 of wireless module SIM900 is connected with one end of resistance R 2 and capacitor C 2, and the other end of resistance R 2 is connected with one end of resistance R 1 and capacitor C 1, capacitor C 1, the other end ground connection of C2, the other end of resistance R 1 is connected with the pin 1 of antennal interface CN1, the pin 2 of antennal interface CN1, 3, 4, 5 ground connection, the pin 66(STAUS of wireless module SIM900) by resistance R 3, be connected the minus earth of light-emitting diode D1 with the positive pole of light-emitting diode D1.
Please refer to Fig. 9, described the circuit diagram of WIFI interface circuit 142 in Fig. 1.As shown in Figure 9, WIFI interface circuit 142 comprises antenna E1, WIFI module U8, modulus conversion chip U7, voltage adjuster chip U6, socket P10, interface J2, J3 and some resistance, electric capacity, inductance, crystal oscillator.In the present embodiment, WIFI module U8 is specially WM-G-MR-09, and modulus conversion chip U7 is specially DAC2450A, and voltage adjuster chip U6 is specially XC6219B332MR, and socket P10 is specially 28 spring hole scokets, and interface J2, J3 are specially the interface in 12 holes.
Particularly, the pin 20(W-R of socket P10), 21(W-T) respectively with the pin 101 of fpga chip, 103 connect, the pin 20 of socket P10 is connected with one end of resistance R 45 simultaneously, the pin 25 of socket P10 is connected with one end of resistance R 48, the pin 27 of socket P10 is by capacitor C 58 ground connection, the pin 28 of socket P10 connects 5V power supply, resistance R 45, the other end of R48 is connected with the pin 10 of socket P10 and one end of resistance R 37, the pin 4(SD_D2 of the other end of resistance R 37 and socket P10) be connected, the pin 2(SD_D0 of socket P10) ground connection, the pin 1 of socket P10 connects 5V power supply, simultaneously, the pin 1 of socket P10 is also parallel with filter capacitor C53, C54, the pin 2(SD_D0 of socket P10) with the pin 21 of WIFI module U8, the pin 7 of interface J3 and one end of resistance R 38 connect, the pin 3(SD_D1 of socket P10) with the pin 5 of WIFI module U8, the pin 8 of interface J3 and one end of resistance R 39 connect, the pin 4(SD_D2 of socket P10) with the pin 22 of WIFI module U8, the pin 9 of interface J3 and one end of resistance R 40 connect, the pin 5(SD_D3 of socket P10) with the pin 12 of WIFI module U8, the pin 10 of interface J3 and one end of resistance R 41 connect, the pin 6(SD_CMD of socket P10) with the pin 20 of WIFI module U8, the pin 11 of interface J3 and one end of resistance R 42 connect, the pin 7(SD_CLK of socket P10) with the pin 14 of WIFI module U8, the pin 12 of interface J3 and one end of resistance R 43 connect, resistance R 38, R39, R40, R41, R42, the other end of R43 links together and forms input VDD-WIFI, the pin 31 of WIFI module U8 is connected with input VDD-WIFI by resistance R 20, the pin 32 of WIFI module U8 is connected with one end of resistance R 22 with resistance R 19, the other end of resistance R 19 is connected with input VDD-WIFI, the other end of resistance R 22 (WL-nRESET) is connected with the pin 5 of interface J3, the pin 1 of WIFI module U8, 3, 8, 19, 26 ground connection, the pin 17 of WIFI module U8 is connected with filter capacitor C47 in parallel, C48, the pin 18 of WIFI module U8 is connected with filter capacitor C49, C50, the pin 25 of WIFI module U8 is connected with filter capacitor C51 in parallel, C52, the pin 9 of WIFI module U8, 28, 27 are connected with input VDD_WIFI, and are all connected with filter capacitor C43 in parallel, C44, C45, C46, the pin 30(WIFI WAKEUP of WIFI module U8) be connected with one end of resistance R 23 and the pin 4 of interface J3, the other end of resistance R 23 is connected with input VDD_WIFI, and the pin 2 of WIFI module U8 is connected with one end of resistance R 18 and capacitor C 28, the other end of resistance R 18 and the pin of DAC2450A 1, antenna E1 and capacitor C 24 connect, the other end ground connection of capacitor C 24 and capacitor C 28, and the pin 2 of DAC2450A is connected with the pin 4 of XC6219B332MR, the pin 1 of XC6219B332MR, 3 with the pin 11 of interface J2, 12 and the pin 1 of interface J3, 2 connect, meanwhile, and the pin 1 of XC6219B332MR, 3 are connected with one end of capacitor C 25, the other end ground connection of capacitor C 25, and pin 2 ground connection of XC6219B332MR, the pin 5 of XC6219B332MR is connected with one end of input VDD-WIFI and capacitor C 26, the other end ground connection of capacitor C 26, the pin 4 of input VDD-WIFI access crystal oscillator X1, meanwhile, input VDD-WIFI is by the pin 1 of resistance R 30 access crystal oscillator X1, and the pin 3 of crystal oscillator X1 is exported the pulse signal of 32KHz, and the pin 3 of crystal oscillator X1 is connected with the pin 35 of WIFI module U8.
Please refer to Figure 10, described the circuit diagram of Zigbee interface circuit 143 in Fig. 1.As shown in figure 10, Zigbee interface circuit 143 comprises control chip CC2530,7 hole double socket JP1,6 hole double socket JP2 and some resistance, electric capacity, inductance, crystal oscillator.
Particularly, the pin 4(P22 of socket JP1), 5(P21), 6(P20), 9(P15), 10(P14), 11(P13), 12(P12), 13(P11), 14(P10) respectively with the pin 34 of control chip CC2530, 35, 36, 5, 6, 7, 8, 9, 11 connect, the pin 7(Z-R of socket JP1), 8(Z-T) with the pin 73 of fpga chip, 74 connect, the pin 3(RESET of socket JP2), 5(P00), 6(P01), 7(P02), 8(P03), 9(P04), 10(P05), 11(P06), 12(P07) respectively with the pin 20 of control chip CC2530, 19, 18, 17, 16, 15, 14, 13, 12 connect, the pin 1 of control chip CC2530, 2, 3, 4, 41 ground connection, the pin 39 of control chip CC2530, 10, 21, 24, 27, 28, 29, 31 with one end ground connection of inductance L 7, the other end of inductance L 7 is connected with 3.3V power supply, the pin 25,26 of control chip CC2530 is connected with one end of capacitor C 87, C92 respectively, the other end of capacitor C 87 is connected with one end of inductance L 9, L11 and capacitor C 88, the other end ground connection of inductance L 9, the other end of capacitor C 92 is connected with one end of the other end, inductance L 12 and the capacitor C 94 of inductance L 11, the other end ground connection of capacitor C 94, the other end of inductance L 12, capacitor C 88 is connected with one end of capacitor C 93, C95, the other end of capacitor C 93 is connected with one end and the antenna E2 of capacitor C 96, the other end ground connection of capacitor C 96, C95, capacitor C 100, capacitor C 105 and crystal oscillator Y5 form control chip CC2530 Yi road clock signal, and by pin 22,23 inputs of control chip CC2530, capacitor C 101, capacitor C 102 and crystal oscillator Y4 form another road clock signal of control chip CC2530, and by pin 32,33 inputs of control chip CC2530, the pin 30 of control chip CC2530 is by resistance R 57 ground connection, and the pin 40 of control chip CC2530 is by capacitor C 103 ground connection.
Please refer to Figure 11, described the circuit diagram of RFID interface circuit 144 in Fig. 1.As shown in figure 11, RFID interface circuit 144 comprises RFID read-write chip U10, socket J5 and some resistance, electric capacity, inductance, crystal oscillator.In the present embodiment, RFID read-write chip U10 is MF522, and socket J5 is 8 spring hole scokets.
Particularly, the pin 31(MISO of RFID read-write chip MF522), 30(MISI), 29(SCK) respectively with the pin 3(PC2 of socket J5), 4(PC3), 5(PC5) connect, the pin 6 of RFID read-write chip MF522 and the pin 1(PC0 of socket J5) and one end of resistance R 56 be connected, the other end of resistance R 56 is connected with 3V power supply, the pin 32 of RFID read-write chip MF522 is connected with 3V power supply, the pin 24(SDA of RFID read-write chip MF522) with the pin 6(PC1 of socket J5) be connected, the pin 2 of socket J5 connects 3.3V power supply, pin 7 ground connection of socket J5, the pin 3(PC2 of socket J5), 4(PC3), 5(PC5), 6(PC1) respectively with the pin 87 of fpga chip, 98, 99, 100 connect, and the pin 21 of RFID read-write chip MF522 is connected with one end of capacitor C 91 and crystal oscillator X2, and the pin 22 of RFID read-write chip MF522 is connected with the other end of one end of capacitor C 97 and crystal oscillator X2, capacitor C 91, the other end of C97 is connected with one end of capacitor C 90, the other end of capacitor C 90 is connected with the pin 16 of RFID read-write chip MF522 and one end of resistance R 60, the other end of resistance R 60 is connected with the pin 17 of RFID read-write chip MF522 and one end of resistance R 61, the other end of resistance R 61 is connected with one end of capacitor C 89, the pin 11 of RFID read-write chip MF522, 13 respectively with inductance L 8, one end of L10 connects, the other end of inductance L 8 and capacitor C 78, one end of C80 connects, the other end of inductance L 10 and capacitor C 83, one end of C85 connects, and the other end of capacitor C 80 and capacitor C 83 connects, the other end of capacitor C 78 and capacitor C 81, the other end of one end of C79 and capacitor C 89 connects, the other end of capacitor C 85 and capacitor C 84, one end of C82 connects, capacitor C 84, the other end of C82 and capacitor C 81, the other end of C79 connects, the pin 2 of RFID read-write chip MF522, 3, 12, 15 are connected with 3V power supply, and connect filter capacitor C75 in parallel, C76.
Please refer to Figure 12, described the circuit diagram of communication Protocol Conversion circuit 10 in Fig. 1, in the present embodiment, communication Protocol Conversion circuit 10 is specially FPGA and controls change-over circuit.Communication Protocol Conversion circuit 10 writes interface circuit 18 with usb circuit 121, RS232 interface circuit 122, RS485 interface circuit 123, ethernet interface circuit 124, CAN bus interface circuit 125, GPRS interface circuit 141, WIFI interface circuit 142, Zigbee interface circuit 143, RFID interface circuit 144, memory circuit 16 and program and is connected.Particularly, communication Protocol Conversion circuit 10 comprises fpga chip and peripheral circuit thereof, and fpga chip is specially EP4CE6E22C8N.
Please refer to Figure 13, described the circuit diagram of memory circuit 16 in Fig. 1.As shown in figure 13, memory circuit consists of storage chip IS63LC1024, and storage chip IS63LC1024 is connected with fpga chip, for store various kinds of data.
Please refer to Figure 14, described the circuit diagram of power circuit 17 in Fig. 1.As shown in figure 14, power circuit is used to each several part circuit in Fig. 1 that operating voltage is provided.
Please refer to Figure 15, described the circuit diagram that Fig. 1 Program writes interface circuit 18.As shown in figure 15, physical circuit figure as shown in figure 15.
As can be seen from the above description, the data acquisition unit 100 that the present invention is applied to the on-the-spot quality monitoring in real time of traditional industry has the following advantages:
1, the variation of data collection station interface, integrates wired, wireless communication technology;
2, apply cloud computing platform, reduced use cost;
3, between each transmission means, can automatically identify, automatically conversion.
In addition, the present invention is applied to the data acquisition unit 100 of the on-the-spot quality monitoring in real time of traditional industry, and the technical indicator of expection is as shown in table 1 below:
Table 1
The economic benefit of expection: existing only to there is our product price of product section function on market as a reference, take 50,000 yuan/overlap as unit price, the prediction of income from sales, cost and profit situation and business tax and additional calculations are respectively in Table 2 and table 3:
| ? | 2013 | 2014 | 2015 | 2016 | Add up to |
| Sales volume | 30 | 50 | 90 | 130 | 300 |
| Not containing tax income from sales (ten thousand yuan) | 150 | 250 | 450 | 650 | 1500 |
| Subtract: total cost (ten thousand yuan) | 91.95 | 153.25 | 275.85 | 398.45 | 919.5 |
| Subtract: business tax and additional (ten thousand yuan) | 1.22 | 2.04 | 3.67 | 5.92 | 12.78 |
| Total profit (ten thousand yuan) | 56.83 | 94.71 | 170.48 | 245.63 | 567.72 |
| Net profit (ten thousand yuan) | 42.62 | 71.03 | 127.86 | 184.22 | 425.79 |
Table 2
| ? | 2013 | 2014 | 2015 | 2016 | Add up to |
| Income from sales (ten thousand yuan) | 150 | 250 | 450 | 650 | 1500 |
| Output VAT (ten thousand yuan)- |
17% | 17% | 17% | 17% | 17% |
| Direct material takes (ten thousand yuan) | 90 | 150 | 270 | 360 | 870 |
| Input VAT (ten thousand yuan)- |
17% | 17% | 17% | 17% | 17% |
| Value added tax payable (ten thousand yuan) | 10.2 | 17 | 30.6 | 49.3 | 107.1 |
| Business tax and additional (ten thousand yuan) | 1.22 | 2.04 | 3.67 | 5.92 | 12.78 |
Table 3
Expection social benefit: the extensive popularization of this technology has fundamentally changed traditional quality management mode, and tradition is manual logging data, utilizes Excel to carry out data statistics, thus cause information isolate, not in time, inaccurate.The mode of utilizing Internet of Things to carry out monitoring in real time to data acquisition can make whole Quality Examination fundamentally change traditional industry pattern by informationization, promotes sooner, more efficiently, more accurately industrialized development.By 10000, put into production every year, can be the newly-increased job nearly 100 people of enterprise.
Invention has been described for above combination most preferred embodiment, but the present invention is not limited to the embodiment of above announcement, and should contain the various modifications of carrying out according to essence of the present invention, equivalent combinations.
Claims (10)
1. a data acquisition unit that is applied to the on-the-spot quality monitoring in real time of traditional industry, it is characterized in that, comprise communication Protocol Conversion circuit and the data acquisition circuit and the data transmission circuit that are connected with described communication Protocol Conversion circuit, described data acquisition circuit comprises at least two kinds of cable data acquisition interface circuit, described data transmission circuit comprises at least two kinds of Wireless Data Transmission interface circuits, and described communication Protocol Conversion circuit is according to the acquisition mode of data and the automatic converts communications agreement of transmission means.
2. the data acquisition unit that is applied to the on-the-spot quality monitoring in real time of traditional industry as claimed in claim 1, it is characterized in that, described cable data acquisition interface circuit comprises usb circuit, RS232 interface circuit, RS485 interface circuit, ethernet interface circuit and CAN bus interface circuit.
3. the data acquisition unit that is applied to the on-the-spot quality monitoring in real time of traditional industry as claimed in claim 2, it is characterized in that, described Wireless Data Transmission interface circuit comprises GPRS interface circuit, WIFI interface circuit, Zigbee interface circuit and RFID interface circuit.
4. the data acquisition unit that is applied to the on-the-spot quality monitoring in real time of traditional industry as claimed in claim 3, is characterized in that, also comprises the memory circuit and the power circuit that are connected with described communication Protocol Conversion circuit.
5. the data acquisition unit that is applied to the on-the-spot quality monitoring in real time of traditional industry as claimed in claim 4, is characterized in that, described communication Protocol Conversion circuit is specially FPGA and controls change-over circuit.
6. the data acquisition unit that is applied to the on-the-spot quality monitoring in real time of traditional industry as claimed in claim 5, it is characterized in that, described RS232 interface circuit comprises single supply level transferring chip U11, interface RS1 and interface RS232, the pin 11,12 of described single supply level transferring chip U11 is connected with described communication Protocol Conversion circuit, the pin 14 of described single supply level transferring chip U11 is connected with pin 2 and the RS1 of interface RS232, and the pin 13 of described single supply level transferring chip U11 is connected with pin 3 and the RS1 of interface RS232.
7. the data acquisition unit that is applied to the on-the-spot quality monitoring in real time of traditional industry as claimed in claim 5, it is characterized in that, described CAN bus interface circuit comprises CAN bus control chip U13, CAN bus transceiver U14, CAN bus protection chip U12 and socket P19, the pin 7 of described CAN bus transceiver U14, 6 respectively with the pin 1 of described socket P19, pin 2 connects, the pin 7 of described CAN bus transceiver U14, 6 respectively with the pin 2 of described CAN bus protection chip U12, pin 1 connects, the pin 1 of described CAN bus transceiver U14, 4 respectively with the pin 1 of described CAN bus control chip U13, 2 connect, described CAN bus transceiver U14 is by pin 7, 6 are connected with described communication Protocol Conversion circuit.
8. the data acquisition unit that is applied to the on-the-spot quality monitoring in real time of traditional industry as claimed in claim 5, it is characterized in that, described Zigbee interface circuit comprises control chip CC2530, socket JP1 and socket JP2, the pin 4 of described socket JP1, 5, 6, 9, 10, 11, 12, 13, 14 respectively with the pin 34 of described control chip CC2530, 35, 36, 5, 6, 7, 8, 9, 11 connect, described socket JP1 is by pin 7, 8 are connected with described communication Protocol Conversion circuit, the pin 3 of described socket JP2, 5, 6, 7, 8, 9, 10, 11, 12 respectively with the pin 20 of described control chip CC2530, 19, 18, 17, 16, 15, 14, 13, 12 connect.
9. the data acquisition unit that is applied to the on-the-spot quality monitoring in real time of traditional industry as claimed in claim 5, it is characterized in that, described RFID interface circuit comprises RFID read-write chip U10 and socket J5, the pin 31,30,29 of described RFID read-write chip U10 is connected with the pin 3,4,5 of described socket J5 respectively, the pin 6 of described RFID read-write chip U10 is connected with the pin 1 of described socket J5 and 3V power supply, the pin 24 of described RFID read-write chip U10 is connected with the pin 6 of socket J5, and the pin 3,4,5,6 of described socket J5 is connected with described communication Protocol Conversion circuit.
10. the data acquisition unit that is applied to the on-the-spot quality monitoring in real time of traditional industry as claimed in claim 5, it is characterized in that, described usb circuit comprises 2 hole contact pin P17, USB-B-R chip, capacitor C 98, resistance R 64, R62, R67 and transistor Q2, one end after described capacitor C 98 and resistance R 64 parallel connections is connected with the pin 0 of described USB-B-R chip, other end ground connection, the pin 1 of described USB-B-R chip is connected with the pin 1 of described contact pin P17, the pin 2 of contact pin P17 connects 5V power supply, the pin 2 of described USB-B-R chip, 3 are connected with described communication Protocol Conversion circuit, the pin 3 of described USB-B-R chip is connected with one end of resistance R 62, the other end of resistance R 62 is connected with the collector electrode of transistor Q2, the emitter of transistor Q2 connects 3.3V power supply, the base stage of transistor Q2 is connected with one end of resistance R 67, the other end of resistance R 67 forms port PC13, port PC13 is connected with described communication Protocol Conversion circuit.
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| CN108107770A (en) * | 2017-05-23 | 2018-06-01 | 深圳市鸿哲智能系统工程有限公司 | A kind of power supply comprehensive control management system |
| CN108000535A (en) * | 2017-12-22 | 2018-05-08 | 安徽杰智智能科技有限公司 | A kind of six-joint robot intelligent controller |
| CN109087491B (en) * | 2018-07-24 | 2021-04-27 | 郑州大学第一附属医院 | Medical equipment remote data acquisition unit |
| CN109087491A (en) * | 2018-07-24 | 2018-12-25 | 郑州大学第附属医院 | A kind of Medical Devices remote data acquisition device |
| CN109739124A (en) * | 2018-12-25 | 2019-05-10 | 南京熊猫电子股份有限公司 | Multi-bus interface data handling utility system |
| CN110262316A (en) * | 2019-05-28 | 2019-09-20 | 无锡市瑞丰计量科技有限公司 | Instrument and meter intelligent things module |
| CN111308933A (en) * | 2020-02-25 | 2020-06-19 | 广东省智能制造研究所 | Internet of things data acquisition system based on FPGA |
| CN111308933B (en) * | 2020-02-25 | 2021-11-05 | 广东省智能制造研究所 | Internet of things data acquisition system based on FPGA |
| CN112003928A (en) * | 2020-08-21 | 2020-11-27 | 深圳市康冠智能科技有限公司 | Multifunctional screen synchronous control method, device and equipment |
| CN112003928B (en) * | 2020-08-21 | 2021-06-25 | 深圳市康冠智能科技有限公司 | Multifunctional screen synchronous control method, device and equipment |
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