CN103647542A - Pre-weight reduction circuit for high-speed serialization deserializer - Google Patents
Pre-weight reduction circuit for high-speed serialization deserializer Download PDFInfo
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- CN103647542A CN103647542A CN201310597942.8A CN201310597942A CN103647542A CN 103647542 A CN103647542 A CN 103647542A CN 201310597942 A CN201310597942 A CN 201310597942A CN 103647542 A CN103647542 A CN 103647542A
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- amplitude controller
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- 239000013585 weight reducing agent Substances 0.000 title abstract description 6
- 230000005540 biological transmission Effects 0.000 claims abstract description 30
- 208000020442 loss of weight Diseases 0.000 claims description 60
- 230000000694 effects Effects 0.000 abstract description 3
- 238000013461 design Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 238000004891 communication Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011960 computer-aided design Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005562 fading Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 239000013307 optical fiber Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 208000016261 weight loss Diseases 0.000 description 1
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Abstract
The invention discloses a pre-weight reduction circuit for a high-speed serialization deserializer, which comprises a resistance voltage divider, a weight reduction amplitude controller and an output stage, wherein the resistance voltage divider and the output stage are connected with the weight reduction amplitude controller. The resistor voltage divider comprises thirty-one equivalent resistors and a first resistor with a resistance value larger than the equivalent resistors, which are sequentially connected in series. The weight-reducing amplitude controller is also connected with an inverter and an external input signal end. The weight reduction amplitude controller is of a tree structure, five columns are provided, and each column is controlled by thirty transmission gates, sixteen transmission gates, eight transmission gates, four transmission gates and two transmission gates. The output stage consists of a multiplexer, a voltage buffer and an operational amplifier which are connected in sequence. The invention can be used for the sending end of a high-speed serialization deserializer, and can reduce the weight of each bit after the first bit in the same polarity bit string, thereby achieving the effect of reducing the amplitude of low-frequency data in advance, compensating the high-frequency attenuation of a channel, and improving the transmission bandwidth on the premise of ensuring the error rate.
Description
Technical field
The present invention relates to a kind of pre-loss of weight circuit, particularly relate to a kind of pre-loss of weight circuit for high speed SerDes, belong to analog communication techniques field.
Background technology
In Modern Communication System, serial data communication can be saved interconnection resources, to signal amplitude require littlely, and crosstalking between signal is little, transmission rate is high, is widely used in various high-speed communication standards, as Ethernet, optical fiber communication, core bus etc.
While transmitting high-speed serial data on the larger link of loss, channel can be abstracted into a low pass filter.This can make the data generation distortion of transmission, increases data in the error rate of receiving terminal.In addition, in the design of high speed SerDes, maximum problem is the control of data processing time, and this is also the key factor of restriction drive bandwidth.Along with the raising of drive bandwidth, when position that the bit wide of each data is less than driver is during the processing time, before the value of transmitted signal will affect the waveform of present bit, there is intersymbol interference.Intersymbol interference is prone to when one group of identical numeric data that serial data stream comprises a plurality of bits, and while following thereafter the opposite number Value Data of short bit.For a long time steady state value charges completely to channel electric capacity, cannot reverse compensation in back to back contrary data bit, and the magnitude of voltage of contrary data likely can be detected, thereby intersymbol interference occurs.Intersymbol interference has reduced the peak frequency that system can be moved.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of pre-loss of weight circuit for high speed SerDes, it implements loss of weight to first afterwards each in identical polar bit string, in identical polar bit string first loss of weight not, can be applicable to the transmitting terminal of high speed SerDes, can reach the effect that reduces in advance low-frequency data amplitude, the high frequency attenuation of compensate for channel improves transmission bandwidth under the prerequisite that guarantees the error rate.
The present invention solves above-mentioned technical problem by following technical proposals: a kind of pre-loss of weight circuit for high speed SerDes, it is characterized in that, it comprises resitstance voltage divider, loss of weight amplitude controller, output stage, and resitstance voltage divider, output stage are all connected with loss of weight amplitude controller.
Preferably, described resitstance voltage divider comprises successively 31 substitutional resistances of series connection and the first resistance that resistance value is greater than substitutional resistance.
Preferably, 40 octuple that the resistance of described the first resistance is substitutional resistance.
Preferably, described loss of weight amplitude controller is also connected with an inverter, an external input signal end.
Preferably, five external input signals of described external input signal end input, five external input signals are used for controlling loss of weight amplitude; Five external input signals generate five bit Inverting signals through inverter respectively.
Preferably, described loss of weight amplitude controller is tree structure, has five row, and each is controlled every row by 30 transmission gates, 16 transmission gates, eight transmission gates, four transmission gates, two transmission gates.
Preferably, described output stage is comprised of the multiplexer connecting successively, voltage buffer, operational amplifier.
Preferably, 32 reference voltages of described resitstance voltage divider output are as the input of loss of weight amplitude controller.
Positive progressive effect of the present invention is: the present invention can effectively simplify pre-loss of weight circuit structure, thereby reduce, realizes the required number of transistors of pre-loss of weight function, can reduce area and the cost of chip, and reduces the power consumption while using.The present invention can control loss of weight amplitude flexibly by five external input signals, realizes 32 kinds of loss of weight amplitudes that do not wait from 0～-4.3dB.
Accompanying drawing explanation
Fig. 1 is that the present invention is for the structural representation of the pre-loss of weight circuit of high speed SerDes.
Fig. 2 is the structural representation of resitstance voltage divider in the present invention.
Fig. 3 is the structural representation of loss of weight amplitude controller in the present invention.
Fig. 4 is the structural representation of output stage in the present invention.
Embodiment
Below in conjunction with accompanying drawing, provide preferred embodiment of the present invention, to describe technical scheme of the present invention in detail.
As shown in Figures 1 to 4, the present invention comprises resitstance voltage divider, loss of weight amplitude controller, output stage for the pre-loss of weight circuit of high speed SerDes, and resitstance voltage divider, output stage are all connected with loss of weight amplitude controller.Resitstance voltage divider comprises successively 31 substitutional resistances of series connection and the first resistance that resistance value is greater than substitutional resistance.Loss of weight amplitude controller is also connected with an inverter, an external input signal end.Loss of weight amplitude controller is tree structure, has five row, and each is controlled every row by 30 transmission gates, 16 transmission gates, eight transmission gates, four transmission gates, two transmission gates.Output stage is comprised of the multiplexer connecting successively, voltage buffer, operational amplifier.
32 each and every one taps on the resistance string of 32 resistance (R0 to R31) of resitstance voltage divider are designated as Vref[0] to Vref[31], can produce 32 different transmission amplitude reference voltages.Wherein, the resistance of the first resistance can be 40 octuple of substitutional resistance.Five external input signals of external input signal end input (can be expressed as de_empha[0] to de_empha[4]), five external input signals are used for controlling loss of weight amplitude; Five external input signals generate five bit Inverting signals (can be expressed as den_empha[0] to den_empha[4]) through inverter respectively.Five external input signals and five bit Inverting signal co-controlling transmission gate switches.Its conducting when the control signal of transmission gate is " 1 ".Transmission gate is designated as S (p, q), such as " S[0,1] " in figure etc.32 reference voltages of resitstance voltage divider output, as the input of loss of weight amplitude controller, correspond respectively to 32 kinds of loss of weight amplitudes that do not wait from 0～-4.3dB.San Shi bis-tunnel inputs are connected with output by tree structure, and each road input is connected with output Vref_tx through five transmission gate switches.If p is even number, S (p, q)=Den_empha[q-1]; If p is odd number, S (p, q)=De_empha[q-1].If de_empha[4:0] binary number that represents is i, exports vref_tx=vref[i].If the input signal bitmap=1 of output stage, multiplexer output v1=vp(supply voltage); If bitmap=0, multiplexer output v1=vref_tx.By voltage buffer, increase driving force.Vp_tx=v1。Operational amplifier be take Txip/m as differential data input.Vp_tx is as the power supply of output stage operational amplifier.During bitmap=1, without loss of weight function, the amplitude of amplifier differential output signal txop/txom is 1.2V; During bitmap=0, the loss of weight amplitude vp_tx that the amplitude of txop/txom configured.
The present invention can be used for the transmitting terminal of high speed SerDes, first afterwards each in identical polar bit string is implemented to loss of weight, can reach the effect that reduces in advance low-frequency data amplitude, the high frequency attenuation of compensate for channel improves transmission bandwidth under the prerequisite that guarantees the error rate.According to which, realize pre-loss of weight, the Analog Circuit Design flow process with available standards realizes, and can reduce clock recovery circuitry complexity, area, power consumption, and available input signal controls flexibly, realizes the feature of multiple (32 kinds) loss of weight amplitude.
The present invention adopts a control signal whether to select loss of weight for the pre-loss of weight circuit of high speed SerDes.Control signal is provided by digital circuit.When this position is 1, indication does not need loss of weight, and the peak-to-peak value of transmitting terminal output difference sub-signal is 1.2V.When this position is 0, indication needs loss of weight, and output difference sub-signal is by the loss of weight amplitude output of setting.The structure that is used for the pre-loss of weight circuit of high speed SerDes will be tried one's best simply.The structure of pre-loss of weight circuit is simpler, realizes the required number of transistors of pre-loss of weight function just fewer, and the area of chip is just less like this, and chip cost reduces, and power consumption also will reduce in addition; The present invention can control loss of weight amplitude flexibly by five external input signals, realizes 32 kinds of loss of weight amplitudes that do not wait from 0～-4.3dB.Pre-loss of weight circuit adopts analog circuit to realize completely, and the Analog Circuit Design flow process of the standard of support.The Analog Circuit Design flow process of standard adopts EDA (Electronic Design Automatic: electric design automation) instrument Computer Aided Design, raising design efficiency.Pre-loss of weight circuit adopts analog circuit to realize, and supports board design flow process, can simplify this circuit is integrated into the difficulty in SerDes transmitting terminal, improves circuit reliability.
The present invention, for the decay of compensating signal HFS, adopts balancing technique to improve signal waveform.Balancing technique is that it can compensate high frequency loss to a great extent for improving a kind of technological means of signal transmission quality.Balancing technique generally comprises transmitting terminal equilibrium and receiving terminal equilibrium.Transmitting terminal equilibrium, also referred to as preequalization, can realize by pre-loss of weight circuit.Use pre-Technology of Weight Reduction, at transmitting terminal, first low-frequency data is carried out to amplitude fading, Here it is, and it can compensate the key point of high frequency attenuation.Its operation principle is: in the moment of signal generation saltus step, circuit is constant to signal driver amplitude; And arbitrarily in consecutive identical numerical value, reduce driving amount at signal, signal swing is decreased.This is because the high fdrequency component of signal focuses mostly in the hopping edge of data; And when consecutive identical numerical value appears in data, mainly with low frequency component, be main, at this time data being decayed, the low frequency component of the data that decayed, so, has just reached the object of pre-loss of weight circuit decay low frequency.In addition, the present invention passed through in the moment of signal generation saltus step, and circuit is constant to the amplitude of signal driver, and arbitrarily in consecutive identical numerical value, reduce the means of driving amount at signal, greatly accelerate the speed that saltus step occurs, thereby reduced intersymbol interference, accelerated the processing time of data.Thereby guaranteeing, under the prerequisite of the receiving terminal error rate, to have improved the bandwidth of driver.
Above-described specific embodiment; the technical problem of solution of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (8)
1. for a pre-loss of weight circuit for high speed SerDes, it is characterized in that, it comprises resitstance voltage divider, loss of weight amplitude controller, output stage, and resitstance voltage divider, output stage are all connected with loss of weight amplitude controller.
2. the pre-loss of weight circuit for high speed SerDes as claimed in claim 1, is characterized in that, described resitstance voltage divider comprises successively 31 substitutional resistances of series connection and the first resistance that resistance value is greater than substitutional resistance.
3. the pre-loss of weight circuit for high speed SerDes as claimed in claim 2, is characterized in that 40 octuple that the resistance of described the first resistance is substitutional resistance.
4. the pre-loss of weight circuit for high speed SerDes as claimed in claim 1, is characterized in that, described loss of weight amplitude controller is also connected with an inverter, an external input signal end.
5. the pre-loss of weight circuit for high speed SerDes as claimed in claim 4, is characterized in that, five external input signals of described external input signal end input, and five external input signals are used for controlling loss of weight amplitude; Five external input signals generate five bit Inverting signals through inverter respectively.
6. the pre-loss of weight circuit for high speed SerDes as claimed in claim 1, it is characterized in that, described loss of weight amplitude controller is tree structure, has five row, and each is controlled every row by 30 transmission gates, 16 transmission gates, eight transmission gates, four transmission gates, two transmission gates.
7. the pre-loss of weight circuit for high speed SerDes as claimed in claim 1, is characterized in that, described output stage is comprised of the multiplexer connecting successively, voltage buffer, operational amplifier.
8. the pre-loss of weight circuit for high speed SerDes as claimed in claim 1, is characterized in that, 32 reference voltages of described resitstance voltage divider output are as the input of loss of weight amplitude controller.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055314A (en) * | 2010-11-16 | 2011-05-11 | 香港应用科技研究院有限公司 | Programmable electromagnetic interference (EMI) rejection with enhanced noise immunity and process tolerability |
| US20130033290A1 (en) * | 2011-08-04 | 2013-02-07 | Gregory King | Apparatuses and methods of communicating differential serial signals including charge injection |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055314A (en) * | 2010-11-16 | 2011-05-11 | 香港应用科技研究院有限公司 | Programmable electromagnetic interference (EMI) rejection with enhanced noise immunity and process tolerability |
| US20130033290A1 (en) * | 2011-08-04 | 2013-02-07 | Gregory King | Apparatuses and methods of communicating differential serial signals including charge injection |
Non-Patent Citations (1)
| Title |
|---|
| 韦雪明等: "一种2.5Gb/s带预加重结构的低压差分串行发送器", 《微电子学》 * |
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