CN106953818B - Equalizer setting device - Google Patents
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- CN106953818B CN106953818B CN201710073300.6A CN201710073300A CN106953818B CN 106953818 B CN106953818 B CN 106953818B CN 201710073300 A CN201710073300 A CN 201710073300A CN 106953818 B CN106953818 B CN 106953818B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03878—Line equalisers; line build-out devices
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Abstract
The embodiment of the invention discloses an equalizer setting device. The device comprises: the digital-to-analog converter comprises a filter circuit, an analog-to-digital converter, a digital storage, a digital comparator and a first digital accumulator, wherein the filter circuit, the analog-to-digital converter, the digital storage, the digital comparator and the first digital accumulator are sequentially connected, the output end of an equalizer is connected with the input end of the filter circuit, the output end of the first digital accumulator is connected with the set value input end of the equalizer, and the output end of the analog-to-digital converter is connected with the input end of the digital comparator. The technical scheme of the embodiment of the invention solves the technical problems of time and labor waste and high cost in the prior art of accurately setting the set value of the equalizer, realizes the accurate setting of the set value of the equalizer once, quickly, simply, conveniently, accurately and at low cost, and saves labor force to a certain extent.
Description
Technical Field
The embodiment of the invention relates to an equalizer parameter setting technology, in particular to an equalizer setting device.
Background
In the fields of internet communication, data transmission among computer motherboard chips, optical fiber communication, high-speed backplane data transmission and the like, the serial data transmission rate of a single channel reaches or even exceeds 10Gbps-20 Gbps. With the increase of transmission rate, problems caused by signal integrity, such as transmission medium loss, reflection, impedance mismatch, crosstalk and the like, become more and more serious, so that an eye pattern formed by overlapping tracks of data received by a receiving end is partially or completely closed before high level/low level decision is made.
In order to improve communication quality and reduce bit error rate and intersymbol interference, a channel equalization technique is usually adopted at a receiving end, i.e. an equalizer is used to counteract the influence of adverse factors on a channel, such as channel loss, uneven frequency response and the like. Because the transmission characteristics of each channel are different due to different factors such as time, environment, temperature, etc., the setting value of the equalizer needs to be adaptively adjusted according to the channel, and the offset voltage of the equalizer itself also affects the transmission quality of the signal, so the offset voltage compensation value of the equalizer needs to be correctly set.
In the prior art, the setting value and the offset compensation voltage of the equalizer are accurately set, generally, a special instrument is needed to measure the eye pattern of the equalizer, and then the setting value and the offset compensation voltage of the equalizer are manually adjusted according to the eye pattern, so that time and labor are wasted, and the special instrument for measuring the eye pattern is generally large in size, inconvenient to move and expensive.
Disclosure of Invention
In view of this, embodiments of the present invention provide an equalizer setting apparatus to optimize the technical problems of time and labor consuming and high cost in the prior art, in which the setting value of the equalizer and the offset compensation voltage are accurately set.
An embodiment of the present invention provides an equalizer setting apparatus, including: a filter circuit 101, an analog-to-digital converter 102, a digital memory 103, a digital comparator 104, and a first digital accumulator 105;
the filter circuit 101, the analog-to-digital converter 102, the digital memory 103, the digital comparator 104 and the first digital accumulator 105 are sequentially connected, an output end of the equalizer 201 is connected with an input end of the filter circuit 101, an output end of the first digital accumulator 105 is connected with a set value input end of the equalizer 201, and an output end of the analog-to-digital converter 102 is connected with an input end of the digital comparator 104;
the filter circuit 101 filters the equalized signal output by the equalizer 201 to obtain a filtered signal, the analog-to-digital converter 102 performs analog-to-digital conversion on the filtered signal to obtain a first digital signal, when the equalizer 201 inputs a test signal, the digital memory 103 receives the first digital signal, when the equalizer 201 inputs an operation signal, the digital memory 103 no longer receives the first digital signal, the digital comparator 104 compares the first digital signal output by the analog-to-digital converter 102 with the second digital signal output by the digital memory 103, outputs a comparison result, the first digital accumulator 105 performs data accumulation according to the comparison result until the value of the first digital signal is greater than or equal to the value of the second digital signal, and outputs the accumulated data to the equalizer 201.
In the above apparatus, it is preferable that the apparatus further comprises: a second digital accumulator 106;
the input end of the second digital accumulator 106 is connected to the output end of the digital comparator 104, and the output end of the second digital accumulator 106 is connected to the offset voltage input end of the equalizer 201;
wherein the equalizer 201 comprises one or two signal inputs;
when the input of the equalizer 201 is turned off and the equalizer 201 includes a signal input terminal which is connected to a first standard voltage, or includes two signal input terminals which are short-circuited or connected to the first standard voltage at the same time, the digital memory 103 does not receive the first digital signal but receives an external reference value input signal, the first digital accumulator 105 does not receive the comparison result any more, and the second digital accumulator 106 performs data accumulation according to the comparison result until the value of the first digital signal is greater than or equal to the value of the second digital signal, and outputs the accumulated data to the equalizer 201.
In the above apparatus, preferably, the filtering apparatus 101 includes: a buffer 1011, an analog multiplier 1012, and a low-pass filter 1013;
the buffer 1011, the analog multiplier 1012 and the low-pass filter 1013 are connected in sequence, wherein the output terminal of the buffer 1011 is connected to both signal input terminals of the analog multiplier 1012.
In the above apparatus, it is preferable that the apparatus further comprises: an input switch 107, a third digital accumulator 108 and an offset voltage compensation module 109;
the input end of the input switch 107 is connected to the output end of the equalizer 201, the output end of the input switch 107 is connected to the input end of the buffer 1011, the input end of the third digital accumulator 108 is connected to the output end of the digital comparator 104, the output end of the third digital accumulator 108 is connected to the input end of the offset voltage compensation module 109, and the output end of the offset voltage compensation module 109 is connected to the compensation input end of the analog multiplier 102;
wherein the buffer 1011 comprises one or two inputs;
when the input switch 107 is turned off and the buffer 1011 includes an input end which is connected to a second standard voltage, or includes two input ends which are short-circuited or connected to the second standard voltage at the same time, the digital memory 103 does not receive the first digital signal but receives an external reference value input signal, the first digital accumulator 105 and the second digital accumulator 106 do not receive the comparison result, the third digital accumulator 108 performs data accumulation according to the comparison result until the value of the first digital signal is greater than or equal to the value of the second digital signal, and outputs the accumulated data to the offset voltage compensation module 109, and the offset voltage compensation module 109 outputs the compensation electric signal to the analog multiplier 102.
In the above apparatus, preferably, the analog-to-digital converter 102 is a 5-bit analog-to-digital converter.
In the above apparatus, it is preferable that the operation mode of the buffer 1011 includes a high gain low bandwidth mode and a low gain high bandwidth mode.
In the above device, preferably, the input switch 107 is a CMOS analog switch.
In the above apparatus, it is preferable that the operation mode of the low pass filter 1013 includes a 0dB gain mode and a 6dB gain mode.
An embodiment of the present invention provides an equalizer setting apparatus, which uses a filter circuit 101, an analog-to-digital converter 102, a digital memory 103, a digital comparator 104 and a first digital accumulator 105, the filter circuit 101, the analog-to-digital converter 102, the digital memory 103, the digital comparator 104 and the first digital accumulator 105 are connected in sequence, the output end of the equalizer 201 is connected with the input end of the filter circuit 101, the output end of the first digital accumulator 105 is connected with the set value input end of the equalizer 201, the output end of the analog-to-digital converter 102 is connected with the input end of the digital comparator 104, so that the problems that the setting value of the equalizer is accurately set in the prior art, which is time-consuming and labor-consuming are solved, the method has the advantages of achieving accurate setting of the set value of the equalizer in a single time, fast, simple, convenient, accurate and low-cost manner and saving labor force to a certain extent.
Drawings
Fig. 1a is a structural diagram of an equalizer setting apparatus according to an embodiment of the present invention;
fig. 1b is a comparison diagram of eye diagrams of an output signal before and after an equalizer adjusts an input signal according to a set value according to an embodiment of the present invention;
fig. 2 is a structural diagram of an equalizer setting apparatus according to a second embodiment of the present invention;
fig. 3 is a structural diagram of an equalizer setting apparatus according to a third embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention.
It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings. Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
Example one
Fig. 1a is a structural diagram of an equalizer setting apparatus according to an embodiment of the present invention, where the structure of the equalizer setting apparatus in this embodiment specifically includes:
the filter circuit 101, the analog-to-digital converter 102, the digital memory 103, the digital comparator 104 and the first digital accumulator 105 are sequentially connected, the output end of the equalizer 201 is connected with the input end of the filter circuit 101, the output end of the first digital accumulator 105 is connected with the set value input end of the equalizer 201, and the output end of the analog-to-digital converter 102 is connected with the input end of the digital comparator 104.
Further, the filter circuit 101 is optimized to: the buffer 1011, the analog multiplier 1012 and the low-pass filter 1013 are connected in sequence, wherein the output end of the buffer 1011 is connected to two signal input ends of the analog multiplier 1012 simultaneously.
As will be understood by those skilled in the art, since signals are transmitted in different channels with different losses and the losses of high frequency signals are particularly severe, there is a phenomenon that a portion of an eye diagram of an output signal of an equalizer tends to close, as shown in a left diagram of fig. 1b, so that the equalizer generally compensates for an input signal, particularly a high frequency signal portion, and the value of the compensation needs to be determined according to the actual attenuation degree of the signal.
In this embodiment, the value of the first digital signal corresponding to the test signal is used as the reference comparison value for gain compensation, wherein the test signal may specifically be a continuous 0/1 alternating signal, and the frequency is a signal with a frequency that is one tenth or lower of the maximum frequency of the equalizer 201 input equalizer allowed to transmit the signal.
The adjustment process of the setting value of equalizer 201 may be, for example, that equalizer 201 inputs the test signal first, buffer 1011 is set to the low-gain high-bandwidth operation mode, for improving the load driving capability of the test signal output from the equalizer 201, the output terminal of the buffer 1011 is connected to both input terminals of the analog multiplier 1012, the analog-to-digital converter 102, after receiving the filtered signal, performs only the integration operation on the input signal in the operation mode of squaring the level value of the output signal of the buffer 1011 and setting the low-pass filter 1013 to a gain of 0dB to obtain the relative effective value of power, the filtered signal is analog-to-digital converted to obtain a first digital signal, the first digital signal is received and stored by the digital memory 103, in this process, although the digital comparator 104 outputs the comparison result according to the input data, the first digital accumulator 105 does not receive the comparison result output by the digital comparator 104.
It will be understood by those skilled in the art that the value range of the first digital signal is determined by the number of significant bits of the analog-to-digital converter 102, for example, when the number of significant bits of the analog-to-digital converter 102 is 5 bits, the value range of the first digital signal is 1 to 32, and when the number of significant bits of the analog-to-digital converter 102 is 6 bits, the value range of the first digital signal is 1 to 64.
Then, the equalizer 201 inputs an operation signal of the maximum transmission rate allowed by the equalizer, wherein the operation signal may specifically be a continuous 0/1 alternating signal, at this time, the buffer 1011 is still set to the operation mode of low gain and high bandwidth, the operation mode of the low pass filter 1013 is set to 6dB gain makes the output signal generate 6dB gain compared with the input signal while filtering the input signal, the digital memory 103 no longer receives the first digital signal, the digital comparator 104 compares the first digital signal output by the analog-to-digital converter 102 with the second digital signal output by the digital memory 103, and outputs the comparison result, in this embodiment and the following embodiments, when the value of the first digital signal is greater than or equal to the value of the second digital signal, the comparison result output by the digital comparator 104 is 0, when the value of the first digital signal is less than the value of the second digital signal, the comparison result output by the digital comparator 104 is 1, the first digital accumulator 105 performs data accumulation according to the comparison result and outputs the accumulated data to the equalizer 201, the equalizer 201 adjusts the input signal according to the input data at the set value input end, and when the value of the first digital signal is smaller than the value of the second digital signal, the digital comparator 104 continues to compare the first digital signal (generated by the working signal adjusted by the equalizer 201) and the second digital signal and outputs the comparison result until the value of the first digital signal is greater than or equal to the value of the second digital signal, so that the adjustment process of the set value of the equalizer 201 is completed, at this time, the equalizer 201 compensates the input working signal by the compensation amount, so that the equalizer 201 can perform accurate voltage compensation on the input working signal, so that the eye diagram of the equalized signal output by the equalizer is closer to the ideal state, as shown in the right diagram of fig. 1 b.
In addition, explaining that the low pass filter 1013 needs to perform gain compensation of 6dB on the equalizer output signal, since the bandwidth of the equalizer 201 is defined as a frequency point when the signal amplitude is attenuated by 3dB when the eye diagram of the output signal of the equalizer 201 reaches the state of the right diagram in fig. 1b, the signal of the frequency at the bandwidth is already attenuated by 3dB compared with the low frequency signal and is attenuated by 6dB compared with the low frequency signal after the square operation by the analog multiplier, so that the filter circuit compensates for the gain of 6dB here.
An embodiment of the present invention provides an equalizer setting apparatus, which uses a filter circuit 101, an analog-to-digital converter 102, a digital memory 103, a digital comparator 104 and a first digital accumulator 105, the filter circuit 101, the analog-to-digital converter 102, the digital memory 103, the digital comparator 104 and the first digital accumulator 105 are connected in sequence, the output end of the equalizer 201 is connected with the input end of the filter circuit 101, the output end of the first digital accumulator 105 is connected with the set value input end of the equalizer 201, the output end of the analog-to-digital converter 102 is connected with the input end of the digital comparator 104, so that the problems that the setting value of the equalizer is accurately set in the prior art, which is time-consuming and labor-consuming are solved, the method has the advantages of achieving accurate setting of the set value of the equalizer in a single time, fast, simple, convenient, accurate and low-cost manner and saving labor force to a certain extent.
Example two
Fig. 2 is a structural diagram of an equalizer setting apparatus according to a second embodiment of the present invention, which is optimized based on the second embodiment, and in this embodiment, as shown in fig. 2, the equalizer setting apparatus further includes: and a second digital accumulator 106, wherein an input end of the second digital accumulator 106 is connected with an output end of the digital comparator 104, and an output end of the second digital accumulator 106 is connected with an offset voltage input end of the equalizer 201.
It can be understood by those skilled in the art that the equalizer itself generally has more or less offset voltages, and therefore, in the present embodiment, the second digital accumulator 106 is added to compensate for the offset voltage of the equalizer 201, but in the present embodiment, it is still default that no offset voltage exists in the equalizer setting system, and when the equalizer 201 has an offset voltage, the offset voltage of the equalizer 201 needs to be compensated first, and then the setting value of the equalizer 201 can be adjusted, that is, the offset voltage compensation process of the equalizer 201 in the present embodiment needs to be completed first, so that the adjustment process of the setting value of the equalizer 201 in the first embodiment can be performed.
Also, it will be appreciated by those skilled in the art that the received signal of the equalizer is mostly a differential signal, and therefore, most equalizers have two signal inputs for receiving the differential signal. In the present embodiment, whether the equalizer 201 has only one signal input terminal or two signal input terminals, the method and the accuracy for compensating the offset voltage of the equalizer 201 are not affected.
The offset voltage compensation process of equalizer 201 may be, for example, to first turn off the input of equalizer 201, set buffer 1011 to the high-gain low-bandwidth operating mode, and set low-pass filter 1013 to the 0 dB-gain operating mode, and then, when equalizer 201 includes one signal input end, make the signal input end access a first standard voltage, and when equalizer 201 includes two signal input ends, make the two signal input ends short-circuited or access the first standard voltage at the same time, where the voltage value of the first standard voltage is any voltage value within the input voltage range of equalizer 201, and the first standard voltage may be typically a dc common-mode voltage of the signal input end of equalizer 201, and may be typically 0.9V, etc.
In addition, the operation mode in which the buffer 1011 is set to the high gain low bandwidth and the operation mode in which the low pass filter 1013 is set to the gain of 0dB are explained here, and since the value of the offset voltage is generally small, it is necessary to set the operation mode of the buffer 1011 to the low gain high bandwidth operation mode, and at the same time, the analog multiplier 1012 is used to amplify the offset voltage so that the input signal of the low pass filter 1013 is an effective signal, and since the offset voltage signal is not a high frequency signal and does not have a serious attenuation, it is not necessary to use the low pass filter 1013 to perform gain compensation, and therefore, the operation mode of the low pass filter 1013 is set to the operation mode in which the gain of 0dB is set.
At this time, the digital memory 103 does not receive the first digital signal, but receives an external reference value input signal, which inputs a reference value into the digital memory 103, wherein the reference value specifically refers to a value of the first digital signal output by the analog-to-digital converter 102 when the equalizer 201 has no offset voltage, and different low-pass filters correspond to different reference values because the value of the first digital signal is determined by the output voltage of the low-pass filter 1013. In a specific example, when the equalizer 201 has no offset voltage, the output voltage of the low pass filter 1013 is one half of the reference voltage of the analog-to-digital converter 102, the number of valid bits of the analog-to-digital converter 102 is 5 bits, and then the reference value should be 16, and since the operation principle of the analog-to-digital converter belongs to the prior art, it will not be described in detail here.
Further, the digital comparator 104 compares the first digital signal output by the analog-to-digital converter 102 with the second digital signal output by the digital memory 103, and outputs a comparison result, at this time, the first digital accumulator 105 no longer receives the comparison result, the second digital accumulator 106 performs data accumulation according to the comparison result, and outputs the accumulated data to the equalizer 201, the equalizer 201 performs voltage compensation on the input signal according to the input data at the offset voltage input end, and, when the value of the first digital signal is smaller than the value of the second digital signal, the digital comparator 104 continues to compare the first digital signal (generated by the output signal generated by the equalizer 201 performing offset voltage compensation on the input signal) with the second digital signal and outputs the comparison result until the value of the first digital signal is greater than or equal to the value of the second digital signal, thus, the offset voltage compensation process of the equalizer 201 is completed, and at this time, the equalizer 201 can perform accurate offset voltage compensation on the input working signal according to the value input by the offset voltage input end, so as to cancel the attenuation of the voltage amplitude of the output signal generated by the offset voltage of the equalizer itself.
The embodiment of the invention provides an equalizer setting device, by using a buffer 1011, an analog multiplier 1012, a low pass filter 1013, an analog-to-digital converter 102, a digital memory 103, a digital comparator 104, a first digital accumulator 105 and a second digital accumulator 106, and connecting the buffer 1011, the analog multiplier 1012, the low pass filter 1013, the analog-to-digital converter 102, the digital memory 103, the digital comparator 104 and the first digital accumulator 105 in sequence, the output end of an equalizer 201 is connected with the input end of the buffer 1011, the output end of the first digital accumulator 105 is connected with the set value input end of an equalizer 201, the output end of the analog-to-digital converter 102 is connected with the input end of the digital comparator 104, the input end of the second digital accumulator 106 is connected with the output end of the digital comparator 104, the output end of the second digital accumulator 106 is connected with the offset voltage input end of the equalizer 201, the technical problems that in the prior art, the set value and the offset compensation voltage of the equalizer are accurately set, time and labor are wasted, and the cost is high are solved, the set value of the equalizer is accurately set at a single time, quickly, simply, conveniently, accurately and at a low cost, and labor force is saved to a certain degree.
EXAMPLE III
Fig. 3 is a structural diagram of an equalizer setting apparatus according to a third embodiment of the present invention, where the third embodiment is optimized based on the foregoing embodiment, and in this embodiment, as shown in fig. 3, the optimization further includes: the input switch 107, the third digital accumulator 108 and the offset voltage compensation module 109, the input end of the input switch 107 is connected with the output end of the equalizer 201, the output end of the input switch 107 is connected with the input end of the buffer 1011, the input end of the third digital accumulator 108 is connected with the output end of the digital comparator 104, the output end of the third digital accumulator 108 is connected with the input end of the offset voltage compensation module 109, and the output end of the offset voltage compensation module 109 is connected with the compensation input end of the analog multiplier 102.
It can be understood by those skilled in the art that there may be offset voltages in the buffer, the analog multiplier, and other devices, and therefore, in this embodiment, the input switch 107, the third digital accumulator 108, and the offset voltage compensation module 109 are added to compensate for the offset voltage of the equalizer setting device, and when there is an offset voltage in both the equalizer 201 and the equalizer setting device, it is necessary to first compensate for the offset voltage of the equalizer setting device, then compensate for the offset voltage of the equalizer 201, and finally adjust the setting value of the equalizer 201, that is, it is necessary to complete the offset voltage compensation process of the equalizer setting device in this embodiment first and then complete the offset voltage compensation process of the equalizer 201 in the second embodiment, so as to perform the adjustment process of the setting value of the equalizer 201 in the first embodiment.
Further, when the received signal of equalizer 201 is a differential signal, buffer 1011 has two signal inputs for receiving the differential signal output by equalizer 201, and in this embodiment, buffer 1011 has only one signal input or two signal inputs, which does not affect the method and accuracy for compensating the offset voltage of the equalizer setting apparatus.
The offset voltage compensation process of the equalizer setting apparatus may illustratively be that the input switch 107 is first turned off, the low-pass filter is set to an operation mode with a gain of 0dB, the buffer 1011 is set to an operation mode with a high gain and a low bandwidth, then, when the buffer 1011 includes one input end, the input end is connected to a second standard voltage, and when the buffer 1011 includes two input ends, the two input ends are connected to a short circuit or the second standard voltage, wherein the voltage value of the second standard voltage is any voltage value within the input voltage range of the buffer 1011, the second standard voltage may specifically be a dc common mode voltage at the output end of the equalizer 201, and may typically be 0.9V, and the like, wherein the input switch 107 may typically be a CMOS switch.
At this time, the digital memory 103 does not receive the first digital signal, but receives an external reference value input signal, which inputs a reference value into the digital memory 103, wherein the reference value specifically refers to a value of the first digital signal output by the analog-to-digital converter 102 when the equalizer setting device does not have an offset voltage.
Further, the digital comparator 104 compares the first digital signal output by the analog-to-digital converter 102 with the second digital signal output by the digital memory 103 to output a comparison result, at this time, the first digital accumulator 105 and the second digital accumulator 106 do not receive the comparison result, the third digital accumulator 108 performs data accumulation according to the comparison result and outputs the accumulated data to the offset voltage compensation module 109, the offset voltage compensation module 109 outputs the compensation electric signal to the analog multiplier 102, the analog multiplier 102 superimposes the output signal generated by the signal input from the signal input terminal with the signal input from the compensation input terminal and outputs the superimposed signal to the low pass filter 1013, and when the value of the first digital signal is smaller than that of the second digital signal, the digital comparator 104 continues to compare the first digital signal (at this time, the first digital signal is generated by the superimposed signal) with the second digital signal and outputs the comparison result As a result, until the value of the first digital signal is greater than or equal to the value of the second digital signal, the offset voltage compensation process of the equalizer setting device is completed, and at this time, the equalizer setting device can accurately compensate the internal offset voltage, so that the first digital accumulator 105 and the second digital accumulator 106 output the correct setting value and offset voltage compensation value of the equalizer 201, respectively.
The embodiment of the invention provides an equalizer setting device, by sequentially connecting an input switch 107, a buffer 1011, an analog multiplier 1012, a low-pass filter 1013, an analog-to-digital converter 102, a digital memory 103, a digital comparator 104, a third digital accumulator 108 and an offset voltage compensation module 109, respectively connecting the input end and the output end of a first digital accumulator 105 with the output end of the digital comparator 104 and the set value input end of an equalizer 201, respectively connecting the input end and the output end of a second digital accumulator 106 with the output end of the digital comparator 104 and the offset voltage input end of the equalizer 201, the technical problems that the setting of the equalizer and the offset compensation voltage is time-consuming and labor-consuming and has high cost in the prior art are solved, the setting of the set value of the equalizer is accurately set at a single time, quickly, simply, accurately and low cost, meanwhile, labor force is saved to a certain extent.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (8)
1. An equalizer setting apparatus, comprising: a filter circuit (101), an analog-to-digital converter (102), a digital memory (103), a digital comparator (104) and a first digital accumulator (105);
the filter circuit (101), the analog-to-digital converter (102), the digital memory (103), the digital comparator (104) and the first digital accumulator (105) are sequentially connected, the output end of the equalizer (201) is connected with the input end of the filter circuit (101), the output end of the first digital accumulator (105) is connected with the set value input end of the equalizer (201), and the output end of the analog-to-digital converter (102) is connected with the input end of the digital comparator (104);
the filter circuit (101) filters an equalized signal output by the equalizer (201) to obtain a filtered signal, the analog-to-digital converter (102) performs analog-to-digital conversion on the filtered signal to obtain a first digital signal, when the equalizer (201) inputs a test signal, the digital memory (103) receives the first digital signal, when the equalizer (201) inputs a working signal, the digital memory (103) no longer receives the first digital signal, the digital comparator (104) compares the first digital signal output by the analog-to-digital converter (102) with a second digital signal output by the digital memory (103) to output a comparison result, the first digital accumulator (105) performs data accumulation according to the comparison result and outputs the accumulated data to the equalizer (201), and the equalizer (201) adjusts the input signal according to input data of a set value, and completing the adjustment of the set value of the equalizer (201) until the value of the first digital signal is greater than or equal to the value of the second digital signal.
2. The apparatus of claim 1, further comprising: a second digital accumulator (106);
the input end of the second digital accumulator (106) is connected with the output end of the digital comparator (104), and the output end of the second digital accumulator (106) is connected with the offset voltage input end of the equalizer (201);
wherein the equalizer (201) comprises one or two signal inputs;
when the input of the equalizer (201) is switched off and the equalizer (201) comprises a signal input, when the signal input end is connected with a first standard voltage or comprises two signal input ends, and when the two signal input ends are short-circuited or are simultaneously connected with the first standard voltage, the digital memory (103) does not receive the first digital signal, receiving an external reference value input signal, the first digital accumulator (105) no longer receiving the comparison result, the second digital accumulator (106) performing data accumulation based on the comparison result, and outputting the accumulated data to an equalizer (201), wherein the equalizer (201) performs voltage compensation on the input signal according to the input data of the offset voltage input end until the value of the first digital signal is greater than or equal to the value of the second digital signal, and the offset voltage compensation process of the equalizer (201) is completed.
3. The apparatus of claim 2, wherein the filter circuit (101) comprises: a buffer (1011), an analog multiplier (1012), and a low-pass filter (1013);
the buffer (1011), the analog multiplier (1012) and the low-pass filter (1013) are connected in sequence, wherein the output end of the buffer (1011) is simultaneously connected with two signal input ends of the analog multiplier (1012).
4. The apparatus of claim 3, further comprising: an input switch (107), a third digital accumulator (108) and an offset voltage compensation module (109);
the input end of the input switch (107) is connected with the output end of the equalizer (201), the output end of the input switch (107) is connected with the input end of the buffer (1011), the input end of the third digital accumulator (108) is connected with the output end of the digital comparator (104), the output end of the third digital accumulator (108) is connected with the input end of the offset voltage compensation module (109), and the output end of the offset voltage compensation module (109) is connected with the compensation input end of the analog multiplier (1012);
wherein the buffer (1011) comprises one or two inputs;
when the input switch (107) is turned off and the buffer (1011) comprises an input end which is connected with a second standard voltage, or comprises two input ends which are short-circuited or simultaneously connected with the second standard voltage, the digital memory (103) does not receive the first digital signal but receives an external reference value input signal, the first digital accumulator (105) and the second digital accumulator (106) do not receive the comparison result, the third digital accumulator (108) performs data accumulation according to the comparison result and outputs the accumulated data to the offset voltage compensation module (109), the offset voltage compensation module (109) outputs a compensation electric signal to the analog multiplier (1012) until the value of the first digital signal is larger than or equal to the value of the second digital signal, and completing the offset voltage compensation process of the equalizer setting device.
5. The apparatus according to any of claims 1, 2 or 4, wherein the analog-to-digital converter (102) is a 5-bit analog-to-digital converter.
6. The apparatus of claim 4, wherein the buffer (1011) is operable in modes comprising a high gain low bandwidth mode and a low gain high bandwidth mode.
7. The apparatus of claim 4, wherein the input switch (107) is a CMOS analog switch.
8. The apparatus of claim 4, wherein the modes of operation of the low pass filter (1013) comprise a 0dB gain mode and a 6dB gain mode.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102480449A (en) * | 2010-11-19 | 2012-05-30 | 马克西姆综合产品公司 | Method and apparatus for controlling a continuous time linear equalizer |
| EP2688260A2 (en) * | 2012-07-18 | 2014-01-22 | LSI Corporation | Methods and apparatus for adapting transmitter equalization coefficients based on receiver gain adaptation |
| CN103733192A (en) * | 2011-10-17 | 2014-04-16 | 松下电器产业株式会社 | Adaptive equalizer |
| CN104378321A (en) * | 2014-11-26 | 2015-02-25 | 英特格灵芯片(天津)有限公司 | Method and circuit for integrating adaptive equalization parameter adjusting and transmission performance testing |
-
2017
- 2017-02-10 CN CN201710073300.6A patent/CN106953818B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102480449A (en) * | 2010-11-19 | 2012-05-30 | 马克西姆综合产品公司 | Method and apparatus for controlling a continuous time linear equalizer |
| CN103733192A (en) * | 2011-10-17 | 2014-04-16 | 松下电器产业株式会社 | Adaptive equalizer |
| EP2688260A2 (en) * | 2012-07-18 | 2014-01-22 | LSI Corporation | Methods and apparatus for adapting transmitter equalization coefficients based on receiver gain adaptation |
| CN104378321A (en) * | 2014-11-26 | 2015-02-25 | 英特格灵芯片(天津)有限公司 | Method and circuit for integrating adaptive equalization parameter adjusting and transmission performance testing |
Non-Patent Citations (1)
| Title |
|---|
| A 10 Gbps ADC-based equalizer for serial I/O receiver.;Khaled A. El-Gammal et al.;《2015 10th International Design & Test Symposium (IDT)》;20151216;全文 * |
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