CN103646887A - Defect inspection method of automatic noise reduction - Google Patents
Defect inspection method of automatic noise reduction Download PDFInfo
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- CN103646887A CN103646887A CN201310612742.5A CN201310612742A CN103646887A CN 103646887 A CN103646887 A CN 103646887A CN 201310612742 A CN201310612742 A CN 201310612742A CN 103646887 A CN103646887 A CN 103646887A
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Abstract
The invention relates to a large-scale integrated circuit manufacturing field, particularly, a defect inspection method of automatic noise reduction. The method can be applied to newly creating a defect detection program. The method comprises the following steps that: optimized defect classification data are timely fed back to defect detection equipment, such that the defect detection program can be optimized; and after automatic adjustment of several batches of wafers, the sensitivity of the defect detection program can be automatically adjusted to a reasonable range, namely, the sensitivity of the defect detection program is adaptable to actual process parameters. With the method adopted, defects of a large number of wafers can be effectively observed in production, and therefore, the efficiency of the production and the accuracy of engineering judgment can be greatly improved.
Description
Technical field
The present invention relates to large scale integrated circuit and manufacture field, relate in particular to a kind of method of automatic reduction defects detection noise.
Background technology
At present, in advanced integrated circuit fabrication process, generally all include the operation of hundreds of step, and in the small mistake of any one process links, all likely cause the inefficacy of whole chip, especially, along with constantly the dwindling of circuit critical size, its requirement to technology controlling and process is stricter; So, in order to find in time to conciliate in process of production, decided existing problem, all need to configure high sensitivity optical defect checkout equipment, so that device products is detected online, and then find timely the mistake that product occurs in preparation process.
The basic functional principle of defects detection is that the optical imagery conversion on chip is changed into the data image that the different bright dull grays rank of serving as reasons represent.Fig. 1～3 are for being converted into the optical imagery on chip the schematic flow sheet of the data image being represented by the bright dull gray of difference rank; As shown in Figures 1 to 3, first, utilize light microscope to obtain the optical imagery (as shown in Figure 1) of a chip, then utilize sample devices to sample (as shown in Figure 2) to the optical imagery of this chip, carry out obtaining the data image being formed by the bright dull gray of difference rank as shown in Figure 3 after GTG processing, finally utilize defect detection equipment that the datagraphic feature of adjacent chip is compared, with detection chip, whether have abnormal defect and defect position.
Wherein, at above-mentioned defect detection equipment, chip is carried out before defects detection technique, need to create a defects detection program adapting with this chip, and in this new defects detection program creation, because new technology exists very large uncertainty, often need the sensitivity of defects detection program to set higher, and because itself just there is certain difference between wafer and wafer, so chip on detection wafer, and when the data-signal of on-chip circuitry is compared, will inevitably be subject to the interference of substrate signal, thereby produce a lot of noises, in actual production technology, because can making the defects count between the different wafers of same batch, the existence of above-mentioned noise can differ greatly.
Fig. 4 is the same batch of defects count schematic diagram on different wafers; Fig. 5 is the defects count block diagram corresponding with its ID on each wafer in Fig. 4; As shown in Figures 4 and 5, in the wafer of same batch (ID=21～25), existence due to noise, cause the difference of quantity of defect between different wafers (wafer) (defect count) huge, as the ID wafer that is 24 on it quantity of defect only have 8, ID is that the defect on 23 wafer has reached 140, and the defects count difference between it reaches 132 (shown in Figure 5).
In addition, because product wafer is after defect detection equipment scanning, all will be through the observation of electron microscope, could determine that the detected defect of defect detection equipment is genuine defect or noise, as shown in Figure 6, product, after through a procedure A, first carries out defects detection to this product, continuation is classified after (utilizing the detected defect of electron microscope judgement defect detection equipment is genuine defect or noise) to detected defect, just can carry out next process B; Like this, just greatly reduce the efficiency of electron microscope to the observation of real defect on wafer, and also need engineer to be optimized the defects detection program in defect detection equipment, and then significantly reduced the efficiency of work.
Chinese patent (publication number: CN1877292A) recorded a kind of defect inspection method.First, semiconductor detection piece is provided, and this semiconductor detection piece comprises at least one defect, then utilize a FAILURE ANALYSIS TECHNOLOGY, in the back side of this semiconductor detection piece, detect at least one suspicious abnormal region, then utilize a physical energy, this suspicious abnormal region in this semiconductor detection piece back side forms a plurality of reference markers around, finally, utilize those reference markers, in the front of this semiconductor detection piece, calibrate the relative position of this defect.
Chinese patent (publication number: CN103000548A) recorded a kind of method of utilizing fpga chip to carry out integrated circuit fabrication process defects detection, comprise the steps: that (1) carry out retaking of a year or grade test to the config memory of fpga chip, obtain the test data of config memory; (2) detect test data, obtain the coordinate information of the config memory breaking down; (3), according to fault coordinate information, count submodule rank, chip level and other fault distribution map of three kinds of levels of disk rank; (4) the fault distribution map under three kinds of ranks is stacked respectively, obtain fault point distribution density; (5) distribution density uniformity is detected, obtain accurate defective workmanship region occurred frequently and possible cause.
Summary of the invention
For the problem of above-mentioned existence, the present invention has disclosed a kind of method (Akind of defect inspection method of automatic noise reduction) of automatic reduction defects detection noise, and wherein, described method comprises:
Provide a wafer for defects detection and to store the server of genetic defects grouped data;
Defect detection equipment is transferred described genetic defects grouped data, and described wafer is carried out to defects detection, and exports defective data to defect scope;
After described defect scope is classified to described defective data, output classification of defects data are to described server;
Described server upgrades described genetic defects grouped data after these classification of defects data are optimized, and generates new classification of defects data;
Described defect detection equipment is transferred described new classification of defects data, and after defects detection program being upgraded according to these new classification of defects data, continues another wafer for defects detection to carry out defects detection.
The method of above-mentioned automatic reduction defects detection noise, wherein, described defect detection equipment upgrades the sensitivity of described defects detection program automatically according to the classification of defects data of transferring.
The method of above-mentioned automatic reduction defects detection noise, wherein, is provided with several chips, and on each chip, is provided with several surveyed area on wafer described in each.
The method of above-mentioned automatic reduction defects detection noise, wherein, the automatic renewal of described sensitivity is controlled according to the zones of different classification on chip described in each
The method of above-mentioned automatic reduction defects detection noise, wherein, carries out the setting of described surveyed area according to the noise size producing on described chip.
The method of above-mentioned automatic reduction defects detection noise, wherein, described surveyed area comprises high density memory block, dense logic district, low-density logic area and low-density peripheral circuit region.
The method of above-mentioned automatic reduction defects detection noise, wherein, the sensitivity that described defect detection equipment carries out defects detection to described high density memory block and described dense logic district is 0～10%.
The method of above-mentioned automatic reduction defects detection noise, wherein, the sensitivity that described defect detection equipment carries out defects detection to described low-density logic area and described low-density peripheral circuit region is 0～30%.
The method of above-mentioned automatic reduction defects detection noise, wherein, described method also comprises:
Successively a plurality of wafers are carried out after above-mentioned defects detection technique, the sensitivity of the defects detection program on described defect detection equipment is adjusted in the scope that meets process requirements automatically.
The method of above-mentioned automatic reduction defects detection noise, wherein, the quantity of described a plurality of wafers is 2～100.
In sum, the method of a kind of automatic reduction defects detection noise of the present invention, be applied to newly create in the technique of defects detection program, by the classification of defects data after optimizing are fed back to defect detection equipment timely, so that defects detection program is optimized, after the automatic adjustment through several batches of wafers, the sensitivity of this defects detection program can be adjusted to a rational scope automatically, adapt with actual technological parameter, and then realize on producing the defect of considerable wafer is effectively observed, significantly to improve the efficiency of production and the correctness of engineering judgement.
Accompanying drawing explanation
Fig. 1～3 are for being converted into the optical imagery on chip the schematic flow sheet of the data image being represented by the bright dull gray of difference rank;
Fig. 4 is the same batch of defects count schematic diagram on different wafers;
Fig. 5 is the defects count block diagram corresponding with its ID on each wafer in Fig. 4;
Fig. 6 is traditional defects detection and observes schematic flow sheet;
Fig. 7 is the schematic flow sheet of an embodiment in the method for a kind of automatic reduction defects detection noise of the present invention;
Fig. 8 is the structural representation that chip arranges different surveyed areas;
Fig. 9 is that the method for utilizing the present invention automatically to reduce defects detection noise is carried out the self-adjusting schematic diagram of flaw detection sensitivity.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
Fig. 7 is the schematic flow sheet of an embodiment in the method for a kind of automatic reduction defects detection noise of the present invention; As shown in Figure 7, a kind of method of automatic reduction defects detection noise, comprising:
First, provide several wafers for defects detection (2～100 wafers are preferably provided) and to store the server of genetic defects grouped data.
Secondly, adopt above-mentioned defect detection equipment to transfer genetic defects grouped data (or server feeds back to defect detection equipment by this genetic defects grouped data automatically), after this defect detection equipment is adjusted the sensitivity of defects detection program according to this genetic defects grouped data, a wafer is carried out to defects detection, and the defective data of exporting this wafer is to defect scope.
Preferably, above-mentioned defect detection equipment be high sensitivity optical defect checkout equipment as light microscope etc., the equipment such as defect scope is electron microscope.
Further, on each above-mentioned wafer, be provided with some chips, and the noise size all producing according to its surfacial pattern on each chip is provided with several surveyed areas; Wherein, Fig. 8 is the structural representation that chip arranges different surveyed areas; As shown in Figure 8, on each chip, be provided with high density memory block, dense logic district, low-density logic area and low-density peripheral circuit region.
Afterwards, after utilizing defect scope to classify to above-mentioned defective data, output classification of defects data are to middle server; This server upgrades the genetic defects grouped data of its storage, to generate new classification of defects data after these classification of defects data being optimized again.
Finally, defect detection equipment is transferred above-mentioned new classification of defects data (or server automatically by new classification of defects data feedback in defect detection equipment), and after defects detection program being upgraded according to these new classification of defects data, to continue that another follow-up wafer for defects detection is carried out to defects detection technique.
Wherein, according to new classification of defects data, defects detection program being upgraded is mainly that the sensitivity of its defects detection is carried out upgrading and adjusting automatically, and is to control according to zones of different classification on each above-mentioned chip.
In addition, pass through successively a plurality of batches of wafers (preferably 1～100, as 1, 2, 3, 20, 50, 80 or 100) during defects detection, above-mentioned defects detection technique is all redefined in the scope being consistent with process requirements in its sensitivity of zones of different of chip, as being set as 0～10%(as 0 by being difficult for the generation dense logic district of noise and the flaw detection sensitivity of high density memory block, 2%, 5%, 7% or 10%), easily produce the low-density logic area of noise and the flaw detection sensitivity of low-density peripheral circuit region is set as 0～30%(as 0, 10%, 15%, 20% or 30%).
Fig. 9 is that the method for utilizing the present invention automatically to reduce defects detection noise is carried out the self-adjusting schematic diagram of flaw detection sensitivity, and its transverse axis represents to carry out the number of defects detection technique wafer, and the longitudinal axis represents the sensitivity of defects detection technique; As shown in Figure 9, by utilizing after the method for above-mentioned a kind of automatic reduction defects detection noise, the sensitivity of defects detection technique tending to be steady gradually, and be finally arranged in the zone of reasonableness that meets process requirements, and then can be widely used in the middle of the defects detection and observation in production technology, saved greatly human and material resources.
Concrete, when carrying out the establishment of a new defects detection program, by adopting the method for above-mentioned automatic reduction defects detection noise, successively through 10 of setting batch wafer automatically adjust after, and the ratio that presets low-density logic area and the noise sensitivity adjustment of low-density peripheral circuit region is 20%, the ratio of high density memory block and the noise sensitivity adjustment of dense logic district is 5%, after certain hour, the sensitivity of defect detection equipment can be adjusted to a rational scope as shown in Figure 9 automatically, thereby realize for the effective observation of producing upper considerable wafer, improve widely the efficiency of producing and the correctness that promotes engineering judgement.
In addition, the method of a kind of automatic reduction defects detection noise of the present embodiment, on a plurality of technology platforms such as Logic, Memory, RF, HV, Analog/Power, MEMS, CIS, Flash, eFlash, can be applicable to >=130nm, 90nm, 65/55nm, 45/40nm, 32/28nm or≤technique of a plurality of technology node such as 22nm in.
In sum, owing to having adopted technique scheme, the embodiment of the present invention proposes by the classification of defects data after optimizing are fed back to defect detection equipment timely, so that defects detection program is optimized, after the automatic adjustment through several batches of wafers, the sensitivity of this defects detection program can be adjusted to a rational scope automatically, adapt with actual technological parameter, and then realize on producing the defect of considerable wafer is effectively observed, significantly to improve the efficiency of production and the correctness of engineering judgement.
By explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.
For a person skilled in the art, read after above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Within the scope of claims, scope and the content of any and all equivalences, all should think and still belong to the intent and scope of the invention.
Claims (10)
1. automatically reduce a method for defects detection noise, it is characterized in that, described method comprises:
Provide a wafer for defects detection and to store the server of genetic defects grouped data;
Defect detection equipment is transferred described genetic defects grouped data, and described wafer is carried out to defects detection, and exports defective data to defect scope;
After described defect scope is classified to described defective data, output classification of defects data are to described server;
Described server upgrades described genetic defects grouped data after these classification of defects data are optimized, and generates new classification of defects data;
Described defect detection equipment is transferred described new classification of defects data, and after defects detection program being upgraded according to these new classification of defects data, continues another wafer for defects detection to carry out defects detection.
2. the method for automatic reduction defects detection noise according to claim 1, is characterized in that, described defect detection equipment upgrades the sensitivity of described defects detection program automatically according to the classification of defects data of transferring.
3. the method for automatic reduction defects detection noise according to claim 2, is characterized in that, is provided with several chips described in each on wafer, and on each chip, is provided with several surveyed area.
4. the method for automatic reduction defects detection noise according to claim 3, is characterized in that, the automatic renewal of described sensitivity is controlled according to the zones of different classification on chip described in each.
5. the method for automatic reduction defects detection noise according to claim 3, is characterized in that, carries out the setting of described surveyed area according to the noise size producing on described chip.
6. the method for automatic reduction defects detection noise according to claim 3, is characterized in that, described surveyed area comprises high density memory block, dense logic district, low-density logic area and low-density peripheral circuit region.
7. the method for automatic reduction defects detection noise according to claim 6, is characterized in that, the sensitivity that described defect detection equipment carries out defects detection to described high density memory block and described dense logic district is 0～10%.
8. the method for automatic reduction defects detection noise according to claim 6, is characterized in that, the sensitivity that described defect detection equipment carries out defects detection to described low-density logic area and described low-density peripheral circuit region is 0～30%.
9. according to the method for the automatic reduction defects detection noise described in any one in claim 1～8, it is characterized in that, described method also comprises:
Successively a plurality of wafers are carried out after above-mentioned defects detection technique, the sensitivity of the defects detection program on described defect detection equipment is adjusted in the scope that meets process requirements automatically.
10. the method for automatic reduction defects detection noise according to claim 9, is characterized in that, the quantity of described a plurality of wafers is 2～100.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024066279A1 (en) * | 2022-09-28 | 2024-04-04 | 东方晶源微电子科技（北京）有限公司 | Wafer defect detection method, device and apparatus, and computer-readable storage medium |
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| US20050159909A1 (en) * | 2004-01-15 | 2005-07-21 | Long-Hui Lin | Method of defect review |
| CN101526485A (en) * | 2008-03-06 | 2009-09-09 | 奥林巴斯株式会社 | Inspection detecting method |
| CN102422405A (en) * | 2009-03-13 | 2012-04-18 | 恪纳腾公司 | Methods and systems for generating an inspection process for a wafer |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050159909A1 (en) * | 2004-01-15 | 2005-07-21 | Long-Hui Lin | Method of defect review |
| CN101526485A (en) * | 2008-03-06 | 2009-09-09 | 奥林巴斯株式会社 | Inspection detecting method |
| CN102422405A (en) * | 2009-03-13 | 2012-04-18 | 恪纳腾公司 | Methods and systems for generating an inspection process for a wafer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024066279A1 (en) * | 2022-09-28 | 2024-04-04 | 东方晶源微电子科技（北京）有限公司 | Wafer defect detection method, device and apparatus, and computer-readable storage medium |
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