CN103645877A - Division operation control unit for multiple floating-point operands - Google Patents
Division operation control unit for multiple floating-point operands Download PDFInfo
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Abstract
A division operation control unit for multiple floating-point operands comprises a command word and operand write time sequence control module, an operand memory, a floating-point operand read time sequence control module and an operand configuration and operation control module. The control unit applies an FPGA (field programmable gate array) for designing a hard link control circuit, command words and floating-point operands of a write time sequence impulse control command generated in the control unit are continuously written in and stored in sequence; under the action of a read time sequence impulse generated in the control unit, the floating-point operands are read in sequence, and a division operation is executed; after the last operand is written in, the division operation execution process is not controlled by a system, and the system can process other instruction programs; a middle operation result and a final operation result can be read while the division operation process is executed; and each instruction can have 127 floating-point operands, and one instruction is equivalent to multiple microprocessor division operation instructions, so that operation processes of fetch and decoding of the system, transmission of the floating-point operands and writing back of the operation results are reduced, and the processing speed is increased.
Description
Technical field
The present invention relates to a kind of many floating-point operations number division operation controller, relate in particular to a kind of based on adopting FPGA parallel work-flow circuit hardwired many floating-point operations number division arithmetic control circuit and sequential control method thereof.
Background technology
Floating number divider is realized 2 32 the floating number division arithmetics that meet IEEE754 standard; Arithmetical unit input participates in two floating-point operation numbers of computing, and one is that 1, one of operand is operand 2, carries out an operation result of a division arithmetic output, and in calculating process, operand 1 and operand 2 must remain stable; Operand 1 input end of arithmetical unit is connected with the output terminal of a working storage, and operand 2 is connected with the output terminal of another working storage; Time cycle add/the subtraction of ratio of division arithmetic, multiplicative operator are long, and microprocessor is transferred to two operands that participate in computing after floating number divider, can turn other programs of processing, and after computing finishes, operation result is read in timesharing; For the division arithmetic of a plurality of operands of continuous execution, and operation result is as dividend, and microprocessor needs repeatedly timesharing transmission as the operand of divisor, the operation that operation result writes back; The mode that the design of floating number divider also adopts streamline to carry out, calculating process is divided into some modules, under the control of the time sequential pulse sending at microprocessor control assembly, the instruction of many floating number division arithmetics is carried out according to sequence of modules, and every ordering calculation in streamline finishes all to need operation result to write back; But need to apply the operation result of a upper operational order as the instruction of dividend for performed floating number division arithmetic, the stream line operation of floating number division arithmetic is ineffective, affected the speed that the instruction of floating number division arithmetic is carried out.
Summary of the invention
The object of the present invention is to provide a kind of many floating-point operations number division operation controller, for realizing a plurality of 32 division arithmetics that meet the floating number of IEEE754 standard; This controller application FPGA designs the hard connecting circuit of many floating-point operations number division operation controller, for floating-point operation more than, counts the command word of division arithmetic instruction and the method that many floating-point operations number takes to write continuously storage, and ablation process takies system bus; Controller is after receiving order and first operand, controller is inner produce synchronize with system clock Clock signal read time sequential pulse signal, read floating-point operation number and carry out division arithmetic reading independently to complete under time sequential pulse signal controlling, division arithmetic command execution process does not take system bus, writes many floating-point operations of storage number process and can walk abreast and carry out with the process of carrying out division arithmetic order; The 1st operand that this controller participates in division arithmetic for transmission arranges division mode and type code, can realize: the 1st operand/2nd operand, be stored in operation result/1st operand in controller, the 1st operand/be stored in three kinds of processing modes of operation result in controller; At controller, carry out in division arithmetic command procedure, system can be read intermediate operations result and the final operation result of carrying out in division arithmetic command procedure.
The technical scheme solving the problems of the technologies described above is: a kind of many floating-point operations number division operation controller, comprises that command word and operand thereof write time-sequence control module, operand store, floating-point operation number and read time-sequence control module, operand configuration s operation control module;
Described command word and operand thereof write that time-sequence control module and operand store, floating-point operation number are read time-sequence control module, operand configuration s operation control module is connected;
Described operand store is also read time-sequence control module with floating-point operation number, operand configuration s operation control module is connected;
Described floating-point operation number is read time-sequence control module and is also connected with operand configuration s operation control module;
Described command word and operand thereof are write time-sequence control module and have been controlled writing and storing of instruction, need to take system bus; Article one, instruction comprises 9 order of the bit words and several operands, and operand mostly is 127 most; When described command word and operand thereof are write time-sequence control module and chosen by system, startup command word and operand thereof are write time-sequence control module work, inner produce synchronize with system WR signal write time sequential pulse sequence; Under the control of writing time sequential pulse, latch the command word of many floating-point operations number divide instruction, write many floating-point operations number and stored; Last operand is written into after storage, and described command word and operand thereof are write time-sequence control module and quit work;
Described operand store is dual-ported memory, write port, and read port, for storing floating-point operation number (under be called operand); There is not the situation that needs arbitration in write and the reading of read port operand of the write port operand of described operand store; The write port of described operand store is subject to command word and operand thereof to write time-sequence control module to control, and the operand write operation of system data bus DB transmission is counted to storer; Read port is subject to floating-point operation number to read time-sequence control module to control, and operand is read and is transferred to operand configuration s operation control module;
Described floating-point operation number is read time-sequence control module and in inside, is read, under the control of time sequential pulse, independently to complete floating-point operation number reading from operand store, does not need to take system bus; Described floating-point operation number is read time-sequence control module and is write after time-sequence control module writes the 1st operand and be activated work at command word and operand thereof, output busy signal Busy is by " 1 " → " 0 ", and according to the 1st operand type, inner produce synchronize with system clock Clock signal read time sequential pulse sequence, in order operand is read to participation division arithmetic; After last 1 operand of participation computing is read, again through time cycle of a division arithmetic, output busy signal Busy, by " 0 " → " 1 ", sends after the result latch pulse of a clock period Clock, stops the work that floating-point operation number is read time-sequence control module;
Described operand configuration s operation control module is according to division mode and the type of the 1st operand of operand store transmission, operand 1 and the operand 2 of two input ends of gating configuration divider, can latch the operation result of each division arithmetic, judge that whether operation result is abnormal; System can configure the final operation result of reading intermediate operations result and command execution s operation control module from operand.
Its further technical scheme is: described command word and operand thereof write time-sequence control module comprise controller identification, write address counter, write operation count pulse generation control module, mode type register and with door I;
The input end of described controller identification and the A31 of system address bus AB are connected to A27 line, CS signal output part and write operation count pulse generation control module write enabling signal input end, operand configures s operation control module and is connected; Described controller identification input A31 identifies with controller the address value setting to the address value of A27 and equates, the CS signal output part of controller identification is " 0 ", otherwise CS signal output part is " 1 ";
The operand number input end of described write address counter is connected to D0 line with the D6 of system data bus DB, writing pulse 1. _ 1 output terminal that presetting pulse input end counts pulse generation control module with write operation is connected, writing pulse 3. _ 1 output terminal that count pulse input end counts pulse generation control module with write operation is connected, write address output terminal is connected with the write address input end AB_1 of operand store, writes to overflow output terminal and be connected with an input end of door I;
The clock terminal of writing that described write operation is counted pulse generation control module is connected with system write signal WR line, the RESET input be connected with the output terminal of door I, pulse 1. _ 1 output terminal is also connected with mode type register latch signal input end, as reading presetting pulse, read time-sequence control module with floating-point operation number and be connected, pulse 2. _ 1 output terminal is connected with the WR_1 input end of operand store write port, as reading starting impulse, reads time-sequence control module be connected with floating-point operation number;
When CS is " 0 ", described write operation is counted the startup work under the effect of the 1st WR signal of system of pulse generation control module, export in order pulse 1. _ 1, pulse 2. _ 1, pulse 3. _ 1, until reset signal input end is just quit work by " 1 " → " 0 ", putting pulse 1. _ 1, pulse 2. _ 1 and pulse 3. _ 1 output terminal is one state;
The input end of described mode type register is connected with D7 line with the D8 of system data bus DB, and mode output terminal is connected with operand configuration s operation control module, and class type output terminal is read time-sequence control module with floating-point operation number and is connected;
Describedly be connected with systematic reset signal Rst line, operand configuration s operation control module respectively with another two input ends of door I;
When the CS signal of controller identification output is during by " 1 " → " 0 ", described command word and operand thereof are write time-sequence control module and are started write operation and count the work of pulse generation control module
,write operation is counted pulse generation control module and is sent the time sequential pulse sequence signal of synchronizeing with system WR signal, under the effect of pulse 1. _ 1 negative edge, the division mode of the 1st operand of the command word of instruction and type are latched in mode type register, by an operand data presetting to write address counter, as the counting initial value of write address counter and the write address initial value of operand store write port, juxtaposition writes that to overflow output terminal be one state; Pulse 2. _ 1, as the WR_1 signal of operand store write port, is counted operand write operation in storer; Pulse 3. _ 1 is as the count pulse of writing of write address counter, so often write an operand, produce 1 count pulse, address value-1 point operation of write address output terminal output is counted the address of the next storage unit of storer write port, when the address value of write address output terminal output reduces to " 0 " by prevalue, write and overflow output terminal by " 1 " → " 0 ", reset write operand pulse generation control module 3, putting all pulse output ends is one state.
Its further technical scheme is: described floating-point operation number read time-sequence control module comprise read address counter, read operation count pulse generation control module, with door an II, with door III and with door IV;
The operand number input end of described read address counter is connected with D0 line with the D6 of system data bus DB, reading pulse 1. _ 1 output terminal that presetting pulse input end counts pulse generation control module with write operation is connected, read count pulse input end and be connected with the output terminal of door IV, read address output end and be connected with the address input end AB_2 that reads of operand store, read to overflow output terminal and read operation count pulse generation control module read overflow input end and be connected;
Described read address counter is read address initial value using the operand number of input command as counting initial value, operand store read port under the effect of reading presetting pulse, and it is one state that juxtaposition reads to overflow output end signal; Often come one to read count pulse, read address counter read address value-1, retouching operation is counted storer read port memory unit address value, when the reading address value and reduce to " 0 " by prevalue of read address counter output, read to overflow output terminal by " 1 " → " 0 ", reading to overflow output signal is the sign that operand readout finishes;
The clock terminal of reading that pulse generation control module is counted in described read operation is connected with system clock Clock line, the RESET input be connected with the output terminal of door III, read to start pulse 2. _ 1 output terminal that input end counts pulse generation control module with write operation and be connected, read sequential control input end and be connected with the class type output terminal of mode type register; Pulse 1. _ 2 output terminals are connected with an input end, operand configuration s operation control module with door II; Pulse 2. _ 2 output terminals are connected with an input end with door IV, operand configuration s operation control module, pulse 3. _ 2 output terminals be connected with another input end of door II; Pulse 4. _ 2 output terminals be connected with another input end of door IV; Pulse 5. _ 2 output terminals, pulse 6. _ 2 output terminals are connected with operand configuration s operation control module; Busy output terminal is to system output Busy busy signal;
Describedly be connected with the door output terminal of II and the read signal input end RD_2 of operand store;
Describedly be connected with systematic reset signal Rst line, operand configuration s operation control module respectively with two input ends of door III;
When the RESET input is " 1 ", described floating-point operation number is read time-sequence control module the reading under presetting pulse effect an operand data presetting to read address counter of pulse 1. _ 1, and the address initial value of operand store read port is an operand numerical value; First pulse 2. _ 1 read under starting impulse effect, start the work that pulse generation control module is counted in read operation, Busy output terminal is by " 1 " → " 0 ";
The type signal of reading sequential control input end input of counting pulse generation control module when read operation is during for " 0 ", pulse 3. _ 2 is sent in circulation in order, pulse 4. _ 2, pulse 5. _ 2, and send a pulse 6. _ 2, when reading to overflow input end signal by " 1 " → " 0 ", put pulse 3. _ 2, pulse 4. _ 2 output terminals are " 1 ", stop pulse 3. _ 2 and pulse 4. _ 2 produce, through an execution cycle time, Busy output terminal is by " 0 " → one state, the latch result pulse 5. _ 2 of a clock period Clock of output, then put pulse 5. _ 2 output terminals for " 1 ", floating-point operation number is read time-sequence control module and is quit work,
The type signal of reading sequential control input end input of counting pulse generation control module when read operation is during for " 1 ", send in order pulse 1. _ 2 and pulse 2. _ 2,5. _ 2 circulation sends pulse 3. _ 2, pulse 4. _ 2, pulse in order again, and pulse 3. _ 2, pulse 4. _ 2, pulse 5. _ 2 production processes are identical while being " 0 " with type signal.
Its further technical scheme is: described operand configuration s operation control module comprises that gate, result register, operand interchanger, floating number divider, computing abnormality mark are controlled, 32 triple gate groups, with a door V, with door VI or door I and or door II;
Two input ends of described gate are connected with the operand output terminal DB_2 of operand store, the operation result output terminal of floating number divider respectively, and the input end of output terminal and result register is connected; Gating control input end be connected with the output terminal of door V;
Several 1 input ends of exchange, 32 triple gate group input ends of the output terminal of described result register and operand interchanger are connected; Result latch signal input end be connected with the output terminal of door VI;
Several 2 input ends of exchange of described operand interchanger are connected with the operand output terminal DB_2 of operand store, exchange control end and or the output terminal of I be connected, two output terminals are connected with operand 1 input end, operand 2 input ends of floating number divider respectively;
The operation result output terminal of described floating number divider is also connected with the operation result input end that computing abnormality mark is controlled;
The output terminal of described 32 triple gate groups is connected with system data bus DB, control input end with or door II output terminal be connected;
Described with door V two input ends count the pulse 1. _ 2 of pulse generation control module, the output terminal of pulse 2. _ 2 is connected with read operation respectively;
Described with door VI two input ends count the pulse 2. _ 2 of pulse generation control module, the output terminal of pulse 5. _ 2 is connected with read operation respectively;
An input end described or door I is connected with the mode output terminal of mode type register, and another input end is connected with pulse 6. _ 2 output terminals that pulse generation control module is counted in read operation;
Two input ends described or door II are connected with CS signal output part, the system read signal RD line of controller identification respectively; When CS is " 0 ", under the effect of system RD signal, read the final operation result of intermediate operations result or command execution.
Its further technical scheme is: described floating-point operation number is read time-sequence control module and is connected with the class type output terminal of mode type register; Described operand configuration s operation control module is connected with the mode output terminal of mode type register; The definition of type is the type of the 1st operand reading from operand store, and the definition of mode is that the 1st operand participated in the processing mode of division arithmetic when type is during for " 0 ";
0: the 1 operand of type is as the operand 2 that participates in division operation, and operation result is as operand 1;
Class1: the 1st operand as 1, the 2 operand of operand that participates in division operation as operand 2;
2. _ 2 types in the output of mode type register of pulse 1. _ 2, pulse that pulse generation control module output is counted in described read operation produce during for " 1 "; When pulse 1. _ 2 or pulse 2. _ 2 are " 0 ", the gating control input end of gate is " 0 ", the 1st operand that gate output is read from operand store; When pulse 1. _ 2 and pulse 2. _ 2 are all " 1 ", gate output operation result;
The 1st operand reading from operand store participated in division arithmetic, and the mode of mode type register output and type signal are just controlled the division mode at exectorial the 1st operand and operation result:
Mode is " 0 ", type is " 0 ": type is operation result for the output of " 0 " result register, several 1 input ends of exchange of operand interchanger are operation result, 1st operand of several 2 input ends of exchange of operand interchanger for reading from operand store; When reading the 1st operand, now pulse 6. _ 2 is that " 0 " is effective, because mode is " 0 " state, the control end that makes operand interchanger is " 0 ", the operation result of several 1 input ends of exchange of operand interchanger is as the operand 2 of operand interchanger output, the 1st operand of several 2 input ends of exchange of operand interchanger is as the operand 1 of operand interchanger output, 2 inputs and 2 outputs that are operand interchanger exchange transmission, carry out the division arithmetic of the 1st operand/operation result;
Mode is " 1 ", type is " 0 ": when reading the 1st operand, although that now pulse 6. _ 2 is " 0 " is effective, mode is one state, making the control end of operand interchanger is " 1 ", and 2 inputs of operand interchanger and 2 outputs do not exchange transmission; Operation result as operand 2, is carried out the division arithmetic of operation result/1st operand as 1, the 1 operand of operand of floating number divider;
When type is " 1 ", the configuration of the 1st operand and the mode signal condition of input are irrelevant, pulse generation control module is counted in read operation can not produce pulse 6. _ 2 signals, pulse 6. _ 2 output terminals are one state, making the control end of operand interchanger is " 1 ", and 2 inputs of operand interchanger and 2 outputs do not exchange transmission; The 1st operand as operand 2, carried out the computing of the 1st operand/2nd operand as 1, the 2 operand of operand of floating number divider.
Owing to adopting above structure, floating-point operation is counted division operation controller and is had following beneficial effect more than the present invention:
One, the command word of an instruction and many floating-point operations number thereof can write storage continuously
More than the present invention, floating-point operation is counted division operation controller inside and is provided with an operand store, inner, count under the control of time sequential pulse with the write operation of system WR impulsive synchronization, after the command word of many floating-point operations number divide instruction is written into, the floating-point operation number of this instruction all can be write in order and is stored in operand store.
Two, from main control, complete the computing of many floating-point operations number division
More than the present invention, floating-point operation is counted division operation controller after receiving the command word and first floating-point operation number of instruction, start the inner read operation of controller and count pulse generation control module, counting under the control of time sequential pulse with the read operation of system clock Clock impulsive synchronization, independently complete the division arithmetic of all floating-point operation numbers of instruction, the division arithmetic order that controller is carried out many floating-point operations number is not controlled by system.
Three, automatically select the 1st processing mode that division operation is counted in floating-point operation
More than the present invention, floating-point operation is counted division operation controller when the 1st floating-point operation number carried out to division arithmetic, has three kinds of processing modes, one be the 1st floating-point operation number as dividend, implement the computing of a 1st floating-point operation number/2nd floating-point operation number; Two be the 1st floating-point operation number as dividend, implement the computing of the 1st floating-point operation number/operation result; Three be the 1st floating-point operation number as divisor, implement the computing of an operation result/1st floating-point operation number.
Four, controller cost performance is high
More than the present invention, floating-point operation is counted division operation controller to take the hard connection control circuit of FPGA is core, realizes the division arithmetic of many floating-point operations number, and calculating process is not controlled by system; In division arithmetic command execution process, can read intermediate operations result, division arithmetic command execution finishes, and can read final operation result; Every instruction can have 127 floating-point operation numbers, such instruction is equivalent to many instructions of identical division arithmetic, has reduced the transmission operating process that system writes back the fetching of instruction and decoding, floating-point operation number and operation result; On the other hand, controller can be applied and carry out the operation result of a upper instruction and carry out computing with the 1st the floating-point operation number that newly writes instruction; Article one, instruction is equivalent to many instructions of identical operation, has improved processing speed, has higher cost performance.
The technical characterictic of floating-point operation more than the present invention being counted to division operation controller below in conjunction with drawings and Examples is further described.
Accompanying drawing explanation
Fig. 1: more than the present invention, the system architecture diagram of division operation controller is counted in floating-point operation;
Fig. 2: more than the present invention, the command word of division operation controller and the circuit connection diagram that operand is write time-sequence control module thereof are counted in floating-point operation;
Fig. 3: the floating-point operation number that more than the present invention, division operation controller is counted in floating-point operation is read the circuit connection diagram of time-sequence control module;
Fig. 4: more than the present invention, the circuit connection diagram of the operand configuration s operation control module of division operation controller is counted in floating-point operation;
Fig. 5: more than the present invention, write order word and many floating-point operations number sequential chart of division operation controller counted in floating-point operation;
Fig. 6: the type 0 that more than the present invention, division operation controller is counted in floating-point operation reads many floating-point operations number and result latchs sequential chart;
Fig. 7: the Class1 that more than the present invention, division operation controller is counted in floating-point operation reads many floating-point operations number and result latchs sequential chart.
In figure:
I-command word and operand thereof are write time-sequence control module, II-operand store, and III-floating-point operation number is read time-sequence control module, IV-operand configuration s operation control module;
The identification of 1-controller, 2-write address counter, 3-write operation is counted pulse generation control module, 4-mode type register, 5-with door an I, 6-read address counter, pulse generation control module is counted in 7-read operation, 8-with door an II, 9-with door an III, 10-with door an IV, 11-gate, 12-result register, 13-operand interchanger, 14-floating number divider, 15-computing abnormality mark is controlled, 16-32 triple gate groups, 17-with door a V, 18-with door a VI, 19-or door I, 20-or door II.
Abbreviation explanation in literary composition:
FPGA-Field Programmable Gate Array, field programmable gate array;
DB-Data Bus, data bus;
AB-Address Bus, address bus;
CS-Chip Select, sheet selects or enables, CS representative " enable signal " in figure;
Clock-clock;
RD-Read, reads, representative " read signal " in figure;
WR-Write, writes, representative " write signal " in figure;
IRQ-Interrupt Request, interrupts application, representative " interrupt request singal " in figure;
Busy-busy signal;
Rst-Reset, resets.
Embodiment
Embodiment:
A kind of many floating-point operations number division operation controller, as shown in Figure 1, realize a plurality of 32 floating number division arithmetics that meet IEEE754 standard, this controller comprises that command word and operand thereof write time-sequence control module I, operand store II, floating-point operation number and read time-sequence control module III, operand configuration s operation control module IV;
Described command word and operand thereof write that time-sequence control module I and operand store II, floating-point operation number are read time-sequence control module III, operand configuration s operation control module IV is connected;
Described operand store II is also read time-sequence control module III with floating-point operation number, operand configuration s operation control module IV is connected;
Described floating-point operation number is read time-sequence control module III and is also connected with operand configuration s operation control module IV;
Described command word and operand thereof are write time-sequence control module I and have been controlled writing and storing of instruction, need to take system bus; Article one, instruction comprises 9 order of the bit words and several operands, and operand mostly is 127 most; When described command word and operand thereof are write time-sequence control module I and chosen by system, startup command word and operand thereof are write the work of time-sequence control module I, inner produce synchronize with system WR signal write time sequential pulse sequence; Under the control of writing time sequential pulse, latch the command word of many floating-point operations number divide instruction, write many floating-point operations number and stored; Last operand is written into after storage, and described command word and operand thereof are write time-sequence control module I and quit work;
Described operand store II is dual-ported memory, write port, and read port, for storing floating-point operation number (under be called operand); There is not the situation that needs arbitration in write and the reading of read port operand of the write port operand of described operand store II; The write port of described operand store II is subject to command word and operand thereof to write time-sequence control module I to control, and the operand write operation of system data bus DB transmission is counted to storer II; Read port is subject to floating-point operation number to read time-sequence control module III to control, and operand is read and is transferred to operand configuration s operation control module IV;
Described floating-point operation number is read time-sequence control module III and in inside, is read, under the control of time sequential pulse, independently to complete floating-point operation number reading from operand store II, does not need to take system bus; Described floating-point operation number is read time-sequence control module III and is write after time-sequence control module I writes the 1st operand and be activated work at command word and operand thereof, output busy signal Busy is by " 1 " → " 0 ", and according to the 1st operand type, inner produce synchronize with system clock Clock signal read time sequential pulse sequence, in order operand is read to participation division arithmetic; After last 1 operand of participation computing is read, again through time cycle of a division arithmetic, output busy signal Busy, by " 0 " → " 1 ", sends after the result latch pulse of a clock period Clock, stops the work that floating-point operation number is read time-sequence control module III;
Described operand configuration s operation control module IV is according to division mode and the type of the 1st operand of operand store II transmission, operand 1 and the operand 2 of two input ends of gating configuration divider, can latch the operation result of each division arithmetic, judge that whether operation result is abnormal; System can configure the final operation result of reading intermediate operations result and command execution s operation control module IV from operand.
As shown in Figure 2, described command word and operand thereof write time-sequence control module I comprise controller identification 1, write address counter 2, write operation count pulse generation control module 3, mode type register 4 and with door I 5;
The input end of described controller identification 1 and the A31 of system address bus AB are connected to A27 line, CS signal output part and write operation count pulse generation control module 3 write enabling signal input end, operand configures s operation control module IV and is connected; Described controller identification 1 input A31 identifies 1 address value setting to the address value of A27 with controller and equates, the CS signal output part of controller identification 1 is " 0 ", otherwise CS signal output part is " 1 ";
The operand number input end of described write address counter 2 is connected with D0 line with the D6 of system data bus DB, writing pulse 1. _ 1 output terminal that presetting pulse input end counts pulse generation control module 3 with write operation is connected, writing pulse 3. _ 1 output terminal that count pulse input end counts pulse generation control module 3 with write operation is connected, write address output terminal is connected with the write address input end AB_1 of operand store II, writes to overflow output terminal and be connected with an input end of door I 5;
The clock terminal of writing that described write operation is counted pulse generation control module 3 is connected with system write signal WR line, the RESET input be connected with the output terminal of door I 5, pulse 1. _ 1 output terminal is also connected with mode type register 4 latch signal input ends, as reading presetting pulse, read time-sequence control module III with floating-point operation number and be connected, pulse 2. _ 1 output terminal is connected with the WR_1 input end of operand store II write port, as reading starting impulse, reads time-sequence control module III be connected with floating-point operation number;
When CS is " 0 ", described write operation is counted pulse generation control module 3 startup work under the effect of the 1st WR signal of system, export in order pulse 1. _ 1, pulse 2. _ 1, pulse 3. _ 1(is referring to Fig. 5), until reset signal input end is just quit work by " 1 " → " 0 ", putting pulse 1. _ 1, pulse 2. _ 1 and pulse 3. _ 1 output terminal is one state;
The input end of described mode type register 4 is connected with D7 line with the D8 of system data bus DB, and mode output terminal is connected with operand configuration s operation control module IV, and class type output terminal is read time-sequence control module III with floating-point operation number and is connected;
Describedly be connected with systematic reset signal Rst line, operand configuration s operation control module IV respectively with another two input ends of door I 5;
When controller is identified the 1 CS signal of exporting by " 1 " → " 0 ", described command word and operand thereof are write time-sequence control module I startup write operation and are counted 3 work of pulse generation control module
,write operation is counted pulse generation control module 3 and is sent the time sequential pulse sequence signal (referring to Fig. 5) of synchronizeing with system WR signal, under the effect of pulse 1. _ 1 negative edge, the division mode of the 1st operand of the command word of instruction and type are latched in mode type register 4, by an operand data presetting to write address counter 2, as the counting initial value of write address counter 2 and the write address initial value of operand store II write port, juxtaposition writes that to overflow output terminal be one state; Pulse 2. _ 1, as the WR_1 signal of operand store II write port, is counted operand write operation in storer II; Pulse 3. _ 1 is as the count pulse of writing of write address counter 2, so often write an operand, produce 1 count pulse, address value-1 point operation of write address output terminal output is counted the address of the next storage unit of storer II write port, when the address value of write address output terminal output reduces to " 0 " by prevalue, write and overflow output terminal by " 1 " → " 0 ", reset write operand pulse generation control module 3, putting all pulse output ends is one state.
As shown in Figure 3, described floating-point operation number read time-sequence control module III comprise read address counter 6, read operation count pulse generation control module 7, with door an II 8, with door III 9 and with door IV 10;
The operand number input end of described read address counter 6 is connected with D0 line with the D6 of system data bus DB, reading pulse 1. _ 1 output terminal that presetting pulse input end counts pulse generation control module 3 with write operation is connected, read count pulse input end and be connected with the output terminal of door IV 10, read address output end and be connected with the address input end AB_2 that reads of operand store II, read to overflow output terminal and read operation count pulse generation control module 7 read overflow input end and be connected;
Described read address counter 6 is read address initial value using the operand number of input command as counting initial value, operand store II read port under the effect of reading presetting pulse, and it is one state that juxtaposition reads to overflow output end signal; Often come one to read count pulse, read address counter 6 read address value-1, retouching operation is counted storer II read port memory unit address value, when the reading address value and reduce to " 0 " by prevalue of read address counter 6 output, read to overflow output terminal by " 1 " → " 0 ", reading to overflow output signal is the sign that operand readout finishes;
The clock terminal of reading that pulse generation control module 7 is counted in described read operation is connected with system clock Clock line, the RESET input be connected with the output terminal of door III 9, read to start pulse 2. _ 1 output terminal that input end counts pulse generation control module 3 with write operation and be connected, read sequential control input end and be connected with the class type output terminal of mode type register 4; Pulse 1. _ 2 output terminals are connected with an input end, operand configuration s operation control module IV with door II 8; Pulse 2. _ 2 output terminals are connected with an input end with door IV 10, operand configuration s operation control module IV, pulse 3. _ 2 output terminals be connected with another input end of door II 8; Pulse 4. _ 2 output terminals be connected with another input end of door IV 10; Pulse 5. _ 2 output terminals, pulse 6. _ 2 output terminals are connected with operand configuration s operation control module IV; Busy output terminal is to system output Busy busy signal;
Describedly be connected with the door output terminal of II 8 and the read signal input end RD_2 of operand store II;
Describedly be connected with systematic reset signal Rst line, operand configuration s operation control module IV respectively with two input ends of door III 9;
When the RESET input is " 1 ", described floating-point operation number is read time-sequence control module III the reading under presetting pulse effect an operand data presetting to read address counter 6 of pulse 1. _ 1, and the address initial value of operand store II read port is an operand numerical value; First pulse 2. _ 1 read under starting impulse effect, start the work that pulse generation control module 7 is counted in read operation, Busy output terminal is by " 1 " → " 0 ";
The type signal of reading sequential control input end input of counting pulse generation control module 7 when read operation is during for " 0 ", pulse 3. _ 2 is sent in circulation in order, pulse 4. _ 2, pulse 5. _ 2, and send a pulse 6. _ 2(is referring to Fig. 6), when reading to overflow input end signal by " 1 " → " 0 ", put pulse 3. _ 2, pulse 4. _ 2 output terminals are " 1 ", stop pulse 3. _ 2 and pulse 4. _ 2 produce, through an execution cycle time, Busy output terminal is by " 0 " → one state, the latch result pulse 5. _ 2 of a clock period Clock of output, then put pulse 5. _ 2 output terminals for " 1 ", floating-point operation number is read time-sequence control module III and is quit work,
The type signal of reading sequential control input end input of counting pulse generation control module 7 when read operation is during for " 1 ", send in order pulse 1. _ 2 and pulse 2. _ 2, again in order circulation send pulse 3. _ 2, pulse 4. _ 2, pulse 5. _ 2(is referring to Fig. 7), pulse 3. _ 2, pulse 4. _ 2, pulse 5. _ 2 production processes are identical while being " 0 " with type signal.
As shown in Figure 4, described operand configuration s operation control module IV comprise gate 11, result register 12, operand interchanger 13, floating number divider 14, computing abnormality mark control 15,32 triple gate groups 16, with a door V 17, with door VI 18 or door I 19 and or door II 20;
Two input ends of described gate 11 are connected with the operand output terminal DB_2 of operand store II, the operation result output terminal of floating number divider 14 respectively, and output terminal is connected with the input end of result register 12; Gating control input end be connected with the output terminal of door V 17;
Several 1 input ends of exchange, 32 triple gate group 16 input ends of the output terminal of described result register 12 and operand interchanger 13 are connected; Result latch signal input end be connected with the output terminal of door VI 18;
Several 2 input ends of exchange of described operand interchanger 13 are connected with the operand output terminal DB_2 of operand store II, exchange control end and or the output terminal of I 19 be connected, two output terminals are connected with operand 1 input end, operand 2 input ends of floating number divider 14 respectively;
The operation result output terminal of described floating number divider 14 is also connected with the operation result input end of computing abnormality mark control 15;
The output terminal of described 32 triple gate groups 16 is connected with system data bus DB, control input end with or door II 20 output terminal be connected;
Described with door V 17 two input ends count the pulse 1. _ 2 of pulse generation control module 7, the output terminal of pulse 2. _ 2 is connected with read operation respectively;
Described with door VI 18 two input ends count the pulse 2. _ 2 of pulse generation control module 7, the output terminal of pulse 5. _ 2 is connected with read operation respectively;
An input end described or door I 19 is connected with the mode output terminal of mode type register 4, and another input end is connected with pulse 6. _ 2 output terminals that pulse generation control module 7 is counted in read operation;
Two input ends described or door II 20 are connected with CS signal output part, the system read signal RD line of controller identification 1 respectively; When CS is " 0 ", under the effect of system RD signal, read the final operation result of intermediate operations result or command execution.
As shown in Figure 2, Figure 3, Figure 4, described floating-point operation number is read time-sequence control module III and is connected with the class type output terminal of mode type register 4; Described operand configuration s operation control module IV is connected with the mode output terminal of mode type register 4; The definition of type is the type of the 1st operand reading from operand store II, and the definition of mode is that the 1st operand participated in the processing mode of division arithmetic when type is during for " 0 ";
0: the 1 operand of type is as the operand 2 that participates in division operation, and operation result is as operand 1;
Class1: the 1st operand as 1, the 2 operand of operand that participates in division operation as operand 2;
2. _ 2 types in 4 outputs of mode type register of pulse 1. _ 2, pulse that pulse generation control module 7 output is counted in described read operation produce during for " 1 "; When pulse 1. _ 2 or pulse 2. _ 2 are " 0 ", the gating control input end of gate 11 is " 0 ", the 1st operand that gate 11 outputs are read from operand store II; When pulse 1. _ 2 and pulse 2. _ 2 are all " 1 ", gate 11 output operation results;
The 1st operand reading from operand store II participated in division arithmetic, and the mode of mode type register 4 outputs and type signal are just controlled the division mode at exectorial the 1st operand and operation result:
Mode is " 0 ", type is " 0 ": type is operation result for 12 outputs of " 0 " result register, several 1 input ends of exchange of operand interchanger 13 are operation result, 1st operand of several 2 input ends of exchange of operand interchanger 13 for reading from operand store II; When reading the 1st operand, now pulse 6. _ 2 is that " 0 " is effective, because mode is " 0 " state, the control end that makes operand interchanger 13 is " 0 ", the operation result of several 1 input ends of exchange of operand interchanger 13 is as the operand 2 of operand interchanger 13 outputs, the exchange number of operand interchanger 13, the 1st operand of 2 input ends is as the operand 1 of operand interchanger 13 outputs, 2 inputs and 2 outputs that are operand interchanger 13 exchange transmission, carry out the division arithmetic of the 1st operand/operation result;
Mode is " 1 ", type is " 0 ": when reading the 1st operand, although that now pulse 6. _ 2 is " 0 " is effective, mode is one state, making the control end of operand interchanger 13 is " 1 ", and 2 inputs of operand interchanger 13 and 2 outputs do not exchange transmission; Operation result as operand 2, is carried out the division arithmetic of operation result/1st operand as 1, the 1 operand of operand of floating number divider 14;
When type is " 1 ", the configuration of the 1st operand and the mode signal condition of input are irrelevant, pulse generation control module 7 is counted in read operation can not produce pulse 6. _ 2 signals, pulse 6. _ 2 output terminals are one state, making the control end of operand interchanger 13 is " 1 ", and 2 inputs of operand interchanger 13 and 2 outputs do not exchange transmission; The 1st operand as operand 2, carried out the computing of the 1st operand/2nd operand as 1, the 2 operand of operand of floating number divider 14.
Claims (5)
1. more than one kind, division operation controller is counted in floating-point operation, realize a plurality of 32 floating number division arithmetics that meet IEEE754 standard, it is characterized in that: this controller comprises that command word and operand thereof write time-sequence control module (I), operand store (II), floating-point operation number and read time-sequence control module (III), operand configuration s operation control module (IV);
Described command word and operand thereof write that time-sequence control module (I) and operand store (II), floating-point operation number are read time-sequence control module (III), operand configuration s operation control module (IV) is connected;
Described operand store (II) is also read time-sequence control module (III) with floating-point operation number, operand configuration s operation control module (IV) is connected;
Described floating-point operation number is read time-sequence control module (III) and is also connected with operand configuration s operation control module (IV);
Described command word and operand thereof are write time-sequence control module (I) and have been controlled writing and storing of instruction, need to take system bus; Article one, instruction comprises 9 order of the bit words and several operands, and operand mostly is 127 most; When described command word and operand thereof are write time-sequence control module (I) and chosen by system, startup command word and operand thereof are write time-sequence control module (I) work, inner produce synchronize with system WR signal write time sequential pulse sequence; Under the control of writing time sequential pulse, latch the command word of many floating-point operations number divide instruction, write many floating-point operations number and stored; Last operand is written into after storage, and described command word and operand thereof are write time-sequence control module (I) and quit work;
Described operand store (II) is dual-ported memory, write port, and read port, for storing floating-point operation number (under be called operand); There is not the situation that needs arbitration in write and the reading of read port operand of the write port operand of described operand store (II); The write port of described operand store (II) is subject to command word and operand thereof to write time-sequence control module (I) control, and the operand write operation of system data bus DB transmission is counted to storer (II); Read port is subject to floating-point operation number to read time-sequence control module (III) control, and operand is read and is transferred to operand configuration s operation control module (IV);
Described floating-point operation number is read time-sequence control module (III) and in inside, is read under the control of time sequential pulse, independently completes floating-point operation number reading from operand store (II), does not need to take system bus; Described floating-point operation number is read time-sequence control module (III) and is write after time-sequence control module (I) writes the 1st operand and be activated work at command word and operand thereof, output busy signal Busy is by " 1 " → " 0 ", and according to the 1st operand type, inner produce synchronize with system clock Clock signal read time sequential pulse sequence, in order operand is read to participation division arithmetic; After last 1 operand of participation computing is read, again through time cycle of a division arithmetic, output busy signal Busy, by " 0 " → " 1 ", sends after the result latch pulse of a clock period Clock, stops the work that floating-point operation number is read time-sequence control module (III);
Described operand configuration s operation control module (IV) is according to division mode and the type of the 1st operand of operand store (II) transmission, operand 1 and the operand 2 of two input ends of gating configuration divider, can latch the operation result of each division arithmetic, judge that whether operation result is abnormal; System can configure the final operation result of reading intermediate operations result and command execution s operation control module (IV) from operand.
2. many floating-point operations number division operation controller as claimed in claim 1, is characterized in that: described command word and operand thereof write time-sequence control module (I) comprise controller identification (1), write address counter (2), write operation count pulse generation control module (3), mode type register (4) and with door I (5);
The described controller identification input end of (1) and the A31 of system address bus AB are connected to A27 line, CS signal output part and write operation count pulse generation control module (3) write enabling signal input end, operand configures s operation control module (IV) and is connected; Described controller identification (1) input A31 identifies to the address value of A27 and controller the address value that (1) set and equates, to identify the CS signal output part of (1) be " 0 " to controller, otherwise CS signal output part is " 1 ";
The operand number input end of described write address counter (2) is connected to D0 line with the D6 of system data bus DB, writing pulse 1. _ 1 output terminal that presetting pulse input end counts pulse generation control module (3) with write operation is connected, writing pulse 3. _ 1 output terminal that count pulse input end counts pulse generation control module (3) with write operation is connected, write address output terminal is connected with the write address input end AB_1 of operand store (II), writes to overflow output terminal and be connected with an input end of door I (5);
The clock terminal of writing that described write operation is counted pulse generation control module (3) is connected with system write signal WR line, the RESET input be connected with the output terminal of door I (5), pulse 1. _ 1 output terminal is also connected with mode type register (4) latch signal input end, as reading presetting pulse, read time-sequence control module (III) with floating-point operation number and be connected, pulse 2. _ 1 output terminal is connected with the WR_1 input end of operand store (II) write port, as reading starting impulse, reads time-sequence control module (III) be connected with floating-point operation number;
When CS is " 0 ", described write operation is counted pulse generation control module (3) startup work under the effect of the 1st WR signal of system, export in order pulse 1. _ 1, pulse 2. _ 1, pulse 3. _ 1, until reset signal input end is just quit work by " 1 " → " 0 ", putting pulse 1. _ 1, pulse 2. _ 1 and pulse 3. _ 1 output terminal is one state;
The input end of described mode type register (4) is connected with D7 line with the D8 of system data bus DB, and mode output terminal is connected with operand configuration s operation control module (IV), and class type output terminal is read time-sequence control module (III) with floating-point operation number and is connected;
Describedly be connected with systematic reset signal Rst line, operand configuration s operation control module (IV) respectively with another two input ends of door I (5);
When the CS signal of controller identification (1) output is during by " 1 " → " 0 ", described command word and operand thereof are write time-sequence control module (I) and are started write operation and count pulse generation control module (3) work
,write operation is counted pulse generation control module (3) and is sent the time sequential pulse sequence signal of synchronizeing with system WR signal, under the effect of pulse 1. _ 1 negative edge, the division mode of the 1st operand of the command word of instruction and type are latched in mode type register (4), by an operand data presetting to write address counter (2), as the counting initial value of write address counter (2) and the write address initial value of operand store (II) write port, juxtaposition writes that to overflow output terminal be one state; Pulse 2. _ 1, as the WR_1 signal of operand store (II) write port, is counted operand write operation in storer (II); Pulse 3. _ 1 is as the count pulse of writing of write address counter (2), so often write an operand, produce 1 count pulse, address value-1 point operation of write address output terminal output is counted the address of the next storage unit of storer (II) write port, when the address value of write address output terminal output reduces to " 0 " by prevalue, write and overflow output terminal by " 1 " → " 0 ", reset write operand pulse generation control module (3), putting all pulse output ends is one state.
3. many floating-point operations number division operation controller as claimed in claim 1, is characterized in that: described floating-point operation number read time-sequence control module (III) comprise read address counter (6), read operation count pulse generation control module (7), with door an II (8), with door III (9) and with door IV (10);
The operand number input end of described read address counter (6) is connected to D0 line with the D6 of system data bus DB, reading pulse 1. _ 1 output terminal that presetting pulse input end counts pulse generation control module (3) with write operation is connected, read count pulse input end and be connected with the output terminal of door IV (10), read address output end and be connected with the address input end AB_2 that reads of operand store (II), read to overflow output terminal and read operation count pulse generation control module (7) read overflow input end and be connected;
Described read address counter (6) is read address initial value using the operand number of input command as counting initial value, operand store (II) read port under the effect of reading presetting pulse, and it is one state that juxtaposition reads to overflow output end signal; Often come one to read count pulse, read address counter (6) read address value-1, retouching operation is counted storer (II) read port memory unit address value, when the reading address value and reduce to " 0 " by prevalue of read address counter (6) output, read to overflow output terminal by " 1 " → " 0 ", reading to overflow output signal is the sign that operand readout finishes;
The clock terminal of reading that pulse generation control module (7) is counted in described read operation is connected with system clock Clock line, the RESET input be connected with the output terminal of door III (9), read to start pulse 2. _ 1 output terminal that input end counts pulse generation control module (3) with write operation and be connected, read sequential control input end and be connected with the class type output terminal of mode type register (4); Pulse 1. _ 2 output terminals are connected with an input end, operand configuration s operation control module (IV) with door II (8); Pulse 2. _ 2 output terminals are connected with an input end with door IV (10), operand configuration s operation control module (IV), pulse 3. _ 2 output terminals be connected with another input end of door II (8); Pulse 4. _ 2 output terminals be connected with another input end of door IV (10); Pulse 5. _ 2 output terminals, pulse 6. _ 2 output terminals are connected with operand configuration s operation control module (IV); Busy output terminal is to system output Busy busy signal;
Described with door II (8) an output terminal be connected with the read signal input end RD_2 of operand store (II);
Describedly be connected with systematic reset signal Rst line, operand configuration s operation control module (IV) respectively with two input ends of door III (9);
When the RESET input is " 1 ", described floating-point operation number is read time-sequence control module (III) the reading under presetting pulse effect an operand data presetting to read address counter (6) of pulse 1. _ 1, and the address initial value of operand store (II) read port is an operand numerical value; First pulse 2. _ 1 read under starting impulse effect, start the work that pulse generation control module (7) are counted in read operation, Busy output terminal is by " 1 " → " 0 ";
The type signal of reading sequential control input end input of counting pulse generation control module (7) when read operation is during for " 0 ", pulse 3. _ 2 is sent in circulation in order, pulse 4. _ 2, pulse 5. _ 2, and send a pulse 6. _ 2, when reading to overflow input end signal by " 1 " → " 0 ", put pulse 3. _ 2, pulse 4. _ 2 output terminals are " 1 ", stop pulse 3. _ 2 and pulse 4. _ 2 produce, through an execution cycle time, Busy output terminal is by " 0 " → one state, the latch result pulse 5. _ 2 of a clock period Clock of output, then put pulse 5. _ 2 output terminals for " 1 ", floating-point operation number is read time-sequence control module (III) and is quit work,
The type signal of reading sequential control input end input of counting pulse generation control module (7) when read operation is during for " 1 ", send in order pulse 1. _ 2 and pulse 2. _ 2,5. _ 2 circulation sends pulse 3. _ 2, pulse 4. _ 2, pulse in order again, and pulse 3. _ 2, pulse 4. _ 2, pulse 5. _ 2 production processes are identical while being " 0 " with type signal.
4. many floating-point operations number division operation controller as claimed in claim 1, is characterized in that: described operand configuration s operation control module (IV) comprise gate (11), result register (12), operand interchanger (13), floating number divider (14), computing abnormality mark control (15), 32 triple gate groups (16), with a door V (17), with door VI (18) or door I (19) and or an II (20);
Two input ends of described gate (11) respectively with the operand output terminal DB_2 of operand store (II), the operation result output terminal of floating number divider (14) is connected, output terminal is connected with the input end of result register (12); Gating control input end be connected with the output terminal of door V (17);
Several 1 input ends of exchange, 32 triple gate groups (16) input end of the output terminal of described result register (12) and operand interchanger (13) are connected; Result latch signal input end be connected with the output terminal of door VI (18);
Several 2 input ends of exchange of described operand interchanger (13) are connected with the operand output terminal DB_2 of operand store (II), exchange control end and or the output terminal of I (19) be connected, two output terminals are connected with operand 1 input end, operand 2 input ends of floating number divider (14) respectively;
The operation result output terminal of described floating number divider (14) is also connected with the operation result input end of computing abnormality mark control (15);
Latch result pulse 5. _ 2 output terminals that the latch result pulse input end of described computing abnormality mark control (15) is counted pulse generation control module (7) with read operation are connected; IRQ output terminal is with another input end with door I (5), is connected with another input end of door III (9), and IRQ output terminal is also exported interrupt request singal IRQ to system; When middle operation result or final operation result occur that when abnormal, described computing abnormality mark is controlled (15) and sent interrupt request singal IRQ to system, and pulse generation control module (7) is counted in reset write operand pulse generation control module (3) and read operation;
The output terminal of described 32 triple gate groups (16) is connected with system data bus DB, control input end with or door II (20) output terminal be connected;
Described with door V (17) two input ends count the pulse 1. _ 2 of pulse generation control module (7), the output terminal of pulse 2. _ 2 is connected with read operation respectively;
Described with door VI (18) two input ends count the pulse 2. _ 2 of pulse generation control module (7), the output terminal of pulse 5. _ 2 is connected with read operation respectively;
An input end described or door I (19) is connected with the mode output terminal of mode type register (4), and another input end is connected with pulse 6. _ 2 output terminals that pulse generation control module (7) is counted in read operation;
Two input ends described or door II (20) are connected with CS signal output part, the system read signal RD line of controller identification (1) respectively; When CS is " 0 ", under the effect of system RD signal, read the final operation result of intermediate operations result or command execution.
5. many floating-point operations number division operation controller as claimed in claim 1, is characterized in that: described floating-point operation number is read time-sequence control module (III) and is connected with the class type output terminal of mode type register (4); Described operand configuration s operation control module (IV) is connected with the mode output terminal of mode type register (4); The definition of type is the type of the 1st operand reading from operand store (II), and the definition of mode is that the 1st operand participated in the processing mode of division arithmetic when type is during for " 0 ";
When operand type is " 0 ": the operation result of gate (1) Output rusults output register (16) output, in the pulse of pulse producer (9) output 1. under the effect of negative edge, the operation result of operation result register (2) latch result output register (16) output, or the output terminal of door II (7) is by " 1 " → " 0 ", with the output terminal of door I (8) by " 1 " → " 0 ", operand register (3) latchs the operand from system bus DB, the division arithmetic of the 1st operand of reading from operand store (II) be treated to following two kinds of modes:
Compute mode is " 0 ": what result register (12) was exported is operation result, several 1 input ends of exchange of operand interchanger (13) are operation result, 1st operand of several 2 input ends of exchange of operand interchanger (13) for reading from operand store (II), when reading the 1st operand, now pulse 6. _ 2 is that " 0 " is effective, because mode is " 0 " state, the control end that makes operand interchanger (13) is " 0 ", the operation result of several 1 input ends of exchange of operand interchanger (13) is as the operand 2 of operand interchanger (13) output, the 1st operand of several 2 input ends of exchange of operand interchanger (13) is as the operand 1 of operand interchanger (13) output, 2 inputs and 2 outputs that are operand interchanger (13) exchange transmission, carry out the division arithmetic of the 1st operand/operation result,
Compute mode is " 1 ": when reading the 1st operand, although it is effective that now pulse 6. _ 2 is " 0 ", but mode is one state, making the control end of operand interchanger (13) is " 1 ", and 2 inputs of operand interchanger (13) and 2 outputs do not exchange transmission; Operation result as operand 2, is carried out the division arithmetic of operation result/1st operand as 1, the 1 operand of operand of floating number divider (14);
When operand type is " 1 ", the configuration of the 1st operand and the mode signal condition of input are irrelevant, pulse generation control module (7) is counted in read operation can not produce pulse 6. _ 2 signals, pulse 6. _ 2 output terminals are one state, making the control end of operand interchanger (13) is " 1 ", and 2 inputs of operand interchanger (13) and 2 outputs do not exchange transmission; The 1st operand as operand 2, carried out the computing of the 1st operand/2nd operand as 1, the 2 operand of operand of floating number divider (14).
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