CN103645877A - Division operation control unit for multiple floating-point operands - Google Patents

Abstract

A multi-floating-point operand division operation controller, including a command word and its operand write timing control module, an operand memory, a floating-point operand read timing control module, and an operand configuration operation control module; the controller is designed using FPGA The control circuit is hard-wired, and the internally generated write timing pulses are sequentially written into the command word and the floating-point operands of the instruction, and under the action of the internally generated read timing pulses, the floating-point operands are read out in sequence to perform division operations; After the last floating-point operand is input, the process of executing the division operation command is not controlled by the system, and the system can transfer to process other instruction programs; during the process of executing the division operation, the intermediate operation and final operation results can be read; each instruction can be There are 127 floating-point operands, and one instruction is equivalent to multiple microprocessor division instructions, which reduces the transfer operation process of system instruction fetching and decoding, floating-point operands and operation result write-back, and improves the processing speed.

Description

Multiple floating-point operand division controller

technical field

The invention relates to a multi-floating-point operand division operation controller, in particular to a multi-floating-point operand division operation control circuit and a timing control method based on the hard connection of an FPGA parallel operation circuit.

Background technique

The floating-point number division operator implements two 32-bit floating-point number division operations that conform to the IEEE754 standard; the operator inputs two floating-point operands involved in the operation, one is operand 1, and the other is operand 2. Perform a division operation and output a The operation result, during the operation, operand 1 and operand 2 must remain stable; the operand 1 input terminal of the arithmetic unit is connected to the output terminal of a temporary register, and the operand 2 is connected to the output terminal of another temporary register ;The time period of the division operation is longer than that of the addition/subtraction and multiplication operators. After the microprocessor transmits the two operands involved in the operation to the floating-point number division operator, it can be transferred to process other programs. After the operation is completed, the time-sharing read operation result; for the division operation of multiple operands performed continuously, and the operation result is used as the dividend, the microprocessor needs to transmit the operand as the divisor multiple times, and the operation of writing back the operation result; the design of the floating-point number division operator is also The operation process is divided into several modules by means of pipeline execution. Under the control of the timing pulse issued by the microprocessor control unit, multiple floating-point number division operation instructions are executed in the order of the modules. Each instruction in the pipeline needs to be completed after the operation is completed. Write back the operation result; but for the executed floating-point number division operation that needs to use the operation result of the previous operation instruction as the dividend instruction, the pipeline operation of the floating-point number division operation will lose its effect, which will affect the execution speed of the floating-point number division operation instruction .

Contents of the invention

The object of the present invention is to provide a multi-floating-point operand division controller, which is used to realize the division operation of a plurality of 32-bit floating-point numbers conforming to the IEEE754 standard; the controller uses FPGA to design a multi-floating-point operand division controller The hard-wired circuit of a multi-floating-point operand division operation instruction adopts the method of continuously writing and storing the command word and the multi-floating-point operand, and the writing process occupies the system bus; the controller receives the command and the first operand Finally, the controller internally generates a read timing pulse signal synchronized with the system clock Clock signal. Under the control of the read timing pulse signal, it independently completes the reading of the floating-point operand and performs the division operation. The execution process of the division operation command does not occupy the system bus. The floating-point operand process and the process of executing the division operation command can be carried out in parallel; the controller sets the division mode and type flag for the first operand that participates in the division operation, and can realize: the first operand/the second operation number, the operation result stored in the controller/the first operand, the first operand/the operation result stored in the controller; when the controller executes the division operation command, the system can read Intermediate operation results and final operation results during the execution of the division operation command.

The technical solution for solving the above-mentioned technical problems is: a multi-floating-point operand division operation controller, including a command word and its operand write sequence control module, an operand memory, a floating-point operand read sequence control module, and an operand configuration operation control module;

The command word and its operand write sequence control module are connected with the operand memory, the floating point operand read sequence control module, and the operand configuration operation control module;

The operand memory is also connected with the floating-point operand read timing control module and the operand configuration operation control module;

The floating-point operand read timing control module is also connected to the operand configuration operation control module;

The command word and its operand write timing control module control completes the writing and storage of the instruction, which needs to occupy the system bus; an instruction includes a 9-bit command word and several operands, and the operands are at most 127; the command word and its operand write sequence control module are selected by the system, start the command word and its operand write sequence control module to work, and internally generate a write sequence pulse sequence synchronous with the system WR signal; under the control of the write sequence pulse, latch multiple The command word of the floating-point operand division instruction is written into multiple floating-point operands for storage; after the last operand is written and stored, the command word and its operand writing timing control module stop working;

The operand memory is a dual-port memory, with a write-only port and a read-only port for storing floating-point operands (hereinafter referred to as operands); the writing and reading of operands in the write port of the operand memory The readout of the port operand does not have the situation that requires arbitration; the write port of the operand memory is controlled by the command word and its operand write timing control module, and the operand transmitted by the system data bus DB is written into the operand memory; The port is controlled by the floating-point operand read timing control module, and the operand read is transmitted to the operand configuration operation control module;

The floating-point operand read timing control module is under the control of the internal read timing pulse, and independently completes the reading of the floating-point operand from the operand memory without occupying the system bus; the floating-point operand read timing control module After the command word and its operand writing timing control module is written into the first operand, it will start to work, and the output busy signal Busy will change from "1" to "0", and according to the type of the first operand, the internal generation and system clock Clock signal synchronous read timing pulse sequence, read the operands in order to participate in the division operation; after the last operand involved in the operation is read out, after a division operation time period, the output busy signal Busy changes from "0" → "1", after sending the result latch pulse of one clock cycle Clock, stop the work of the floating-point operand read timing control module;

According to the division mode and type of the first operand transmitted by the operand memory, the operand configuration operation control module gates and configures the operand 1 and operand 2 of the two input terminals of the division operator, and can latch each division The operation result of the operation is used to judge whether the operation result is abnormal; the system can read the intermediate operation result and the final operation result of command execution from the operand configuration operation control module.

Its further technical solution is: the command word and its operand write timing control module includes controller identification, write address counter, write operand pulse generation control module, mode type register and AND gate I;

The input terminal identified by the controller is connected to the A31 to A27 lines of the system address bus AB, and the CS signal output terminal is connected to the write start signal input terminal of the write operand pulse generation control module and the operand configuration operation control module; the control If the address value of the controller identification input A31 to A27 is equal to the address value set by the controller identification, the CS signal output terminal identified by the controller is "0", otherwise the CS signal output terminal is "1";

The operand number input end of the write address counter is connected to the D6 to D0 lines of the system data bus DB, the write preset pulse input end is connected to the pulse ①_1 output end of the write operand pulse generation control module, and the write count pulse input end It is connected with the pulse ③_1 output terminal of the write operand pulse generation control module, the write address output terminal is connected with the write address input terminal AB_1 of the operand memory, and the write overflow output terminal is connected with an input terminal of AND gate I;

The write synchronization pulse input terminal of the write operand pulse generation control module is connected to the system write signal WR line, the reset input terminal is connected to the output terminal of AND gate I, and the pulse ①_1 output terminal is also connected to the mode type register latch signal input terminal , used as a read preset pulse to connect to the floating-point operand read timing control module, the pulse ②_1 output terminal is connected to the WR_1 input terminal of the operand memory write port, and used as a read start pulse to connect to the floating-point operand read timing control module;

When CS is "0", the write operand pulse generation control module starts to work under the action of the first WR signal of the system, and outputs pulse ①_1, pulse ②_1, and pulse ③_1 in sequence until the input terminal of the reset signal changes from "1 "→"0" to stop working, set the output terminals of pulse ①_1, pulse ②_1 and pulse ③_1 to "1" state;

The input end of the mode type register is connected with the D8 and D7 lines of the system data bus DB, the mode output end is connected with the operand configuration operation control module, and the type output end is connected with the floating-point operand read timing control module;

The other two input terminals of the AND gate I are respectively connected to the system reset signal Rst line and the operand configuration operation control module;

When the controller recognizes that the output CS signal is from "1" to "0", the command word and its operand write sequence control module start the write operand pulse generation control module to work , and the write operand pulse generation control module sends out and communicates with the system The timing pulse sequence signal synchronized with the WR signal, under the action of the falling edge of pulse ①_1, the division mode and type of the first operand of the command word of the instruction are latched in the mode type register, and the value of the operand is preset to write The address counter is used as the counting initial value of the write address counter and the write address initial value of the operand memory write port, and sets the write overflow output terminal to "1"state; pulse ②_1 is used as the WR_1 signal of the operand memory write port, and the operand Write into the operand memory; pulse ③_1 is used as the write count pulse of the write address counter, so that each time an operand is written, a count pulse is generated, and the address value -1 output by the write address output terminal points to the lower end of the write port of the operand memory For the address of a storage unit, when the address value output by the write address output terminal decreases from the preset value to "0", the write overflow output terminal changes from "1" to "0", resets the write operand pulse generation control module 3, and sets All pulse outputs are in "1" state.

Its further technical solution is: the floating-point operand read timing control module includes a read address counter, a read operand pulse generation control module, AND gate II, AND gate III, and AND gate IV;

The operand number input end of the read address counter is connected with the D6 and D0 lines of the system data bus DB, the read preset pulse input end is connected with the pulse ①_1 output end of the write operand pulse generation control module, and the count pulse input end is read It is connected with the output terminal of AND gate IV, the read address output terminal is connected with the read address input terminal AB_2 of the operand memory, and the read overflow output terminal is connected with the read overflow input terminal of the read operand pulse generation control module;

The read address counter uses the number of operands of the input command as the initial value of counting and the initial value of the read address of the read port of the operand memory under the action of the read preset pulse, and sets the read overflow output terminal signal to "1" state; A read count pulse comes, the read address value of the read address counter is -1, and the address value of the operand memory read port storage unit is modified. When the read address value output by the read address counter is reduced from the preset value to "0", the read overflow output The terminal is from "1" to "0", and the read overflow output signal is a sign of the end of the operand read process;

The read synchronization pulse input terminal of the read operand pulse generation control module is connected to the system clock Clock line, the reset input terminal is connected to the output terminal of AND gate III, and the read start input terminal is output to the pulse ②_1 of the write operand pulse generation control module connection, the read timing control input terminal is connected to the type output terminal of the mode type register; the pulse ①_2 output terminal is connected to an input terminal of the AND gate II, and the operand configuration operation control module; the pulse ②_2 output terminal is connected to an input terminal of the AND gate IV terminal, operand configuration operation control module connection, pulse ③_2 output terminal is connected with the other input terminal of AND gate II; pulse ④_2 output terminal is connected with the other input terminal of AND gate IV; pulse ⑤_2 output terminal, pulse ⑥_2 output terminal and The operand configuration operation control module is connected; the Busy output terminal outputs a Busy busy signal to the system;

The output end of the AND gate II is connected to the read signal input end RD_2 of the operand memory;

The two input ends of the AND gate III are respectively connected to the system reset signal Rst line and the operand configuration operation control module;

When the reset input terminal is "1", the floating-point operand read timing control module presets the operand value to the read address counter under the action of the read preset pulse of pulse ①_1, and the address of the operand memory read port starts The value is a number of operands; under the action of the read start pulse of the first pulse ②_1, the work of the read operand pulse generation control module is started, and the Busy output terminal changes from "1" to "0";

When the input type signal of the read timing control input terminal of the read operand pulse generation control module is "0", pulses ③_2, pulse ④_2, pulse ⑤_2, and a pulse ⑥_2 are sent out in sequence, and when the read overflow input signal is When "1"→"0", set the output terminals of pulse ③_2 and pulse ④_2 to "1", stop the generation of pulse ③_2 and pulse ④_2, and after one operation cycle time, the Busy output terminal changes from "0" to "1", and the output The latch result pulse ⑤_2 of a clock cycle Clock, then set the output terminal of pulse ⑤_2 as "1", and the floating-point operand read timing control module stops working;

When the input type signal of the read timing control input terminal of the read operand pulse generation control module is "1", pulse ①_2 and pulse ②_2 are issued in sequence, and then pulse ③_2, pulse ④_2, pulse ⑤_2, pulse ③_2, The generation process of pulse ④_2 and pulse ⑤_2 is the same as when the type signal is "0".

Its further technical solution is: the operand configuration operation control module includes a strobe, a result register, an operand switch, a floating-point number division operator, an operation exception flag control, a 32-bit tri-state gate group, an AND gate V, and an AND gate. Gate VI, OR Gate I and OR Gate II;

The two input terminals of the strobe are respectively connected with the operand output terminal DB_2 of the operand memory and the operation result output terminal of the floating-point number division operator, and the output terminal is connected with the input terminal of the result register; the strobe control input terminal and Connect with the output terminal of gate V;

The output end of the result register is connected to the exchange number 1 input end of the operand switcher and the input end of the 32-bit tri-state gate group; the result latch signal input end is connected to the output end of the AND gate VI;

The exchange number 2 input terminal of the operand switch is connected to the operand output terminal DB_2 of the operand memory, the exchange control terminal is connected to the output terminal of the OR gate I, and the two output terminals are respectively connected to the operand of the floating-point number division operator. 1 input terminal, operand 2 input terminal connection;

The operation result output terminal of the floating-point number division operator is also connected to the operation result input terminal controlled by the abnormal operation flag;

The latch result pulse input terminal controlled by the abnormal operation flag is connected to the latch result pulse ⑤_2 output terminal of the read operand pulse generation control module; the IRQ output terminal is connected to the other input terminal of AND gate I, and the other input terminal of AND gate III The input terminal is connected, and the IRQ output terminal also outputs an interrupt request signal IRQ to the system; when the intermediate operation result or the final operation result is abnormal, the operation abnormality flag control sends an interrupt request signal IRQ to the system, and resets the write operand pulse generation control module and read operand pulse generation control module;

The output end of the 32-bit tri-state gate group is connected to the system data bus DB, and the control input end is connected to the output end of the OR gate II;

The two input terminals of the AND gate V are respectively connected to the output terminals of pulse ①_2 and pulse ②_2 of the read operand pulse generation control module;

The two input terminals of the AND gate VI are respectively connected to the output terminals of pulse ②_2 and pulse ⑤_2 of the read operand pulse generation control module;

An input end of the OR gate I is connected to the mode output end of the mode type register, and the other input end is connected to the pulse ⑥_2 output end of the read operand pulse generation control module;

The two input terminals of the OR gate II are respectively connected to the CS signal output terminal identified by the controller and the system read signal RD line; when CS is "0", under the action of the system RD signal, the intermediate calculation result or The final operation result of command execution.

Its further technical scheme is: described floating-point operand read timing control module is connected with the type output end of mode type register; Described operand configuration operation control module is connected with the mode output end of mode type register; The definition of type is from operation The type of the first operand read from the number memory, the definition of the method is when the type is "0", the first operand participates in the processing method of the division operation;

Type 0: The first operand is used as operand 2 participating in the division operation, and the operation result is used as operand 1;

Type 1: The first operand is used as operand 1 participating in the division operation, and the second operand is used as operand 2;

The pulse ①_2 and pulse ②_2 output by the read operand pulse generation control module are only generated when the type of the mode type register output is "1"; when the pulse ①_2 or pulse ②_2 is "0", the gating control of the strobe When the input terminal is "0", the strobe outputs the first operand read from the operand memory; when both pulse ①_2 and pulse ②_2 are "1", the strobe outputs the operation result;

The first operand read from the operand memory participates in the division operation, and the mode and type signal output by the mode type register control the division mode of the first operand and the operation result of the command being executed:

The mode is "0", the type is "0": the type is "0", the output of the result register is the operation result, the input terminal of the exchange number 1 of the operand switch is the operation result, and the input terminal of the exchange number 2 of the operand switch is The first operand read from the operand memory; when the first operand is read, the pulse ⑥_2 is "0" valid at this time, and because the mode is "0", the control terminal of the operand switch is " 0", the operation result of the input terminal of the exchange number 1 of the operand exchange is used as the operand 2 output by the operand exchange, and the first operand of the exchange number 2 input of the operand exchange is used as the output operand of the operand exchange 1, that is, the 2 inputs and 2 outputs of the operand switch are exchanged and transmitted, and the division operation of the first operand/operation result is performed;

The mode is "1" and the type is "0": when reading the first operand, although the pulse ⑥_2 is "0" is valid at this time, but the mode is "1", so that the control terminal of the operand switch is " 1", the 2 inputs and 2 outputs of the operand switcher are not exchanged and transmitted; the operation result is used as operand 1 of the floating-point number division operator, the first operand is used as operand 2, and the operation result/first operand division operation;

When the type is "1", the configuration of the first operand has nothing to do with the signal state of the input mode. The pulse generation control module of the read operand will not generate the pulse ⑥_2 signal, and the output terminal of the pulse ⑥_2 is in the "1" state, making the operand The control terminal of the switch is "1", and the 2 inputs and 2 outputs of the operand switch are not exchanged and transmitted; the first operand is used as operand 1 of the floating-point number division operator, and the second operand is used as the operation Number 2, perform the operation of the 1st operand/2nd operand.

Due to the adoption of the above structure, the multi-floating-point operand division operation controller of the present invention has the following beneficial effects:

1. The command word of an instruction and its multiple floating-point operands can be continuously written into the storage

The multi-floating-point operand division operation controller of the present invention is provided with an operand memory inside, and under the control of the write operand timing pulse synchronous with the system WR pulse inside, the command word of the multi-floating-point operand division instruction is written After input, all the floating-point operands of the instruction can be written in order and stored in the operand memory.

2. Autonomous control to complete the operation of multi-floating-point operand division

After the multi-floating-point operand division operation controller of the present invention receives the command word and the first floating-point operand of the instruction, it starts the internal read operand pulse generation control module of the controller, and performs the read operation synchronously with the system clock Clock pulse. Under the control of the number timing pulse, the division operation of all floating-point operands of the instruction is completed independently, and the controller executes the division operation command of multiple floating-point operands without being controlled by the system.

3. Automatically select the processing method of the division operation of the first floating-point operand

The multi-floating-point operand division operation controller of the present invention has three processing methods when performing division operation on the first floating-point operand. One is that the first floating-point operand is used as the dividend to implement the first floating-point operation. number/the second floating-point operand; the second is that the first floating-point operand is used as the dividend, and the first floating-point operand/operation result is implemented; the third is that the first floating-point operand is used as the divisor, Carry out the operation of the operation result/the first floating-point operand.

Fourth, the controller is cost-effective

The multi-floating-point operand division operation controller of the present invention takes the hard-wired control circuit of FPGA as the core to realize the division operation of multi-floating-point operands, and the operation process is not controlled by the system; during the execution of the division operation command, it can read the intermediate The operation result, the division operation command is executed, and the final operation result can be read out; each instruction can have 127 floating-point operands, so that one instruction is equivalent to multiple instructions of the same division operation, which reduces the number of instructions fetched by the system and The transmission operation process of decoding, floating-point operand and operation result write-back; on the other hand, the controller can apply the operation result of the previous instruction to perform operation with the first floating-point operand of the newly written instruction; one instruction It is equivalent to multiple instructions of the same operation, which improves the processing speed and has a high cost performance.

The technical features of the multi-floating-point operand division controller of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.

Description of drawings

Fig. 1: the system structural block diagram of multi-floating-point operand division operation controller of the present invention;

Fig. 2: the circuit connection diagram of the command word of multi-floating-point operand division controller of the present invention and its operand writing sequence control module;

Fig. 3: the circuit connection diagram of the floating-point operand reading timing control module of the multi-floating-point operand division operation controller of the present invention;

Fig. 4: the circuit connection diagram of the operand configuration operation control module of the multi-floating-point operand division operation controller of the present invention;

Fig. 5: write command word and multi-floating-point operand sequence diagram of multi-floating-point operand division operation controller of the present invention;

Fig. 6: the type 0 read multi-floating-point operand and result latch timing diagram of multi-floating-point operand division operation controller of the present invention;

Fig. 7: A timing diagram of type 1 reading of multiple floating-point operands and result latching of the multi-floating-point operand division operation controller of the present invention.

In the picture:

Ⅰ—command word and its operand write sequence control module, Ⅱ—operand memory, Ⅲ—floating point operand read sequence control module, Ⅳ—operand configuration operation control module;

1—controller identification, 2—write address counter, 3—write operand pulse generation control module, 4—mode type register, 5—AND gate I, 6—read address counter, 7—read operand pulse generation control module, 8—AND gate II, 9—AND gate III, 10—AND gate IV, 11—selector, 12—result register, 13—operand switch, 14—floating-point number division operator, 15—operation exception flag control , 16-32-bit tri-state gate group, 17-AND gate V, 18-AND gate VI, 19-OR gate I, 20-OR gate II.

Explanation of abbreviations in the text:

FPGA－Field Programmable Gate Array, Field Programmable Gate Array;

DB－Data Bus, data bus;

AB-Address Bus, address bus;

CS-Chip Select, chip select or enable, CS in the figure represents "enable signal";

Clock - clock;

RD-Read, read, the figure represents "read signal";

WR-Write, write, the figure represents "write signal";

IRQ－Interrupt Request, interrupt application, the figure represents "interrupt request signal";

Busy - busy signal;

Rst-Reset, reset.

Detailed ways

Example:

A multi-floating-point operand division controller, as shown in Figure 1, realizes a plurality of 32-bit floating-point number division operations that meet the IEEE754 standard. The controller includes a command word and its operand write timing control module I, operand Memory II, floating-point operand read timing control module III, operand configuration operation control module IV;

The command word and its operand writing sequence control module I are connected with the operand memory II, the floating-point operand reading sequence control module III, and the operand configuration operation control module IV;

The operand memory II is also connected to the floating-point operand read timing control module III and the operand configuration operation control module IV;

The floating-point operand read timing control module III is also connected to the operand configuration operation control module IV;

The command word and its operand write timing control module I control the writing and storage of the instruction, which needs to occupy the system bus; an instruction includes a 9-bit command word and several operands, and the operands are at most 127; the order When the word and its operand write sequence control module Ⅰ is selected by the system, the command word and its operand write sequence control module Ⅰ work, and internally generate a write sequence pulse sequence synchronous with the system WR signal; under the control of the write sequence pulse, Latch the command word of the multi-floating-point operand division instruction, and write the multi-floating-point operand to be stored; after the last operand is written and stored, the command word and its operand writing timing control module I stop working;

The operand memory II is a dual-port memory, with a write-only port and a read-only port for storing floating-point operands (hereinafter referred to as operands); the write port operand of the operand memory II There is no need for arbitration in the readout of the operand of the read port; the write port of the operand memory II is controlled by the command word and its operand write timing control module I, and the operand transmitted by the system data bus DB is written into the operation The read port is controlled by the floating-point operand read sequence control module III, and the operand read is transmitted to the operand configuration operation control module IV;

The floating-point operand read timing control module III, under the control of the internal read timing pulse, independently completes the reading of the floating-point operand from the operand memory II without occupying the system bus; the floating-point operand read timing The control module III is started to work after the command word and its operand writing sequence control module I write the first operand, the output busy signal Busy changes from "1" to "0", and according to the type of the first operand, the internal Generate a read timing pulse sequence synchronized with the system clock Clock signal, and read out the operands in order to participate in the division operation; after the last operand involved in the operation is read out, after a time period of the division operation, the busy signal Busy is output From "0" to "1", after sending a clock cycle Clock result latch pulse, stop the work of the floating-point operand read timing control module III;

According to the division mode and type of the first operand transmitted by the operand memory II, the operand configuration operation control module IV gates and configures the operand 1 and operand 2 of the two input terminals of the division operator, and can latch each The operation result of the second division operation is judged whether the operation result is abnormal; the system can read the intermediate operation result and the final operation result of command execution from the operand configuration operation control module IV.

As shown in Figure 2, the command word and its operand write sequence control module I include controller identification 1, write address counter 2, write operand pulse generation control module 3, mode type register 4 and AND gate I5;

The input terminal of the controller identification 1 is connected to the A31 to A27 lines of the system address bus AB, and the CS signal output terminal is connected to the write start signal input terminal of the write operand pulse generation control module 3 and the operand configuration operation control module IV; The address value of the controller identification 1 input A31 to A27 is equal to the address value set by the controller identification 1, then the CS signal output terminal of the controller identification 1 is "0", otherwise the CS signal output terminal is "1" ;

The operand number input end of the write address counter 2 is connected with the D6 and D0 lines of the system data bus DB, the write preset pulse input end is connected with the pulse ①_1 output end of the write operand pulse generation control module 3, and the write count pulse The input terminal is connected to the pulse ③_1 output terminal of the write operand pulse generation control module 3, the write address output terminal is connected to the write address input terminal AB_1 of the operand memory II, and the write overflow output terminal is connected to an input terminal of the AND gate I5;

The write synchronization pulse input terminal of the write operand pulse generation control module 3 is connected to the system write signal WR line, the reset input terminal is connected to the output terminal of the AND gate I5, and the pulse ①_1 output terminal is also connected to the mode type register 4 latch signal input Connected as a read preset pulse to the floating-point operand read timing control module III, the output of pulse ②_1 is connected to the WR_1 input of the operand memory II write port, used as a read start pulse and the floating-point operand read timing control module Ⅲ connection;

When CS is "0", the write operand pulse generation control module 3 starts to work under the action of the first WR signal of the system, and outputs pulse ①_1, pulse ②_1, and pulse ③_1 in sequence (see Figure 5) until reset The signal input terminal stops working from "1"→"0", and the output terminals of pulse ①_1, pulse ②_1 and pulse ③_1 are set to "1" state;

The input end of the mode type register 4 is connected to the D8 and D7 lines of the system data bus DB, the mode output end is connected to the operand configuration operation control module IV, and the type output end is connected to the floating-point operand read timing control module III;

The other two input terminals of the AND gate I5 are respectively connected to the system reset signal Rst line and the operand configuration operation control module IV;

When the controller recognizes that the CS signal output by 1 changes from "1" to "0", the command word and its operand write sequence control module I start the write operand pulse generation control module 3 to work , and the write operand pulse generation control module 3 Send out a timing pulse train signal (see Figure 5) synchronous with the system WR signal, under the action of the falling edge of pulse ①_1, the division mode and type of the first operand of the command word of the instruction are latched in the mode type register 4 , preset the value of the operand to the write address counter 2 as the initial count value of the write address counter 2 and the write address initial value of the operand memory II write port, and set the write overflow output terminal to "1"state; pulse ②_1 As the WR_1 signal of the write port of the operand memory II, the operand is written into the operand memory II; the pulse ③_1 is used as the write count pulse of the write address counter 2, so that each time an operand is written, a count pulse is generated, and the write address The address value -1 output by the output terminal points to the address of the next storage unit of the operand memory II write port. When the address value output by the write address output terminal decreases from the preset value to "0", the write overflow output terminal changes from "1" to "1". "→"0", reset the write operand pulse generation control module 3, and set all pulse output terminals to "1" state.

As shown in Figure 3, the floating-point operand read timing control module III includes a read address counter 6, a read operand pulse generation control module 7, an AND gate II8, an AND gate III9 and an AND gate IV10;

The operand number input end of the read address counter 6 is connected with the D6 and D0 lines of the system data bus DB, the read preset pulse input end is connected with the pulse ①_1 output end of the write operand pulse generation control module 3, and the count pulse is read The input terminal is connected with the output terminal of AND gate IV 10, the read address output terminal is connected with the read address input terminal AB_2 of the operand memory II, and the read overflow output terminal is connected with the read overflow input terminal of the read operand pulse generation control module 7;

The read address counter 6 uses the number of operands of the input command as the initial value of counting and the initial value of the read address of the operand memory II read port under the action of the read preset pulse, and sets the read overflow output terminal signal to "1" state ; Every time a read count pulse comes, the read address value of the read address counter 6 is -1, and the address value of the storage unit of the operand memory II read port is modified, when the read address value output by the read address counter 6 is reduced from the preset value to "0" When , the read overflow output terminal changes from "1" to "0", and the read overflow output signal is a sign of the end of the operand read process;

The read synchronization pulse input end of the read operand pulse generation control module 7 is connected to the system clock Clock line, the reset input end is connected to the output end of the AND gate III 9, and the read start input end is connected to the write operand pulse generation control module 3. ②_1 output terminal connection, the read timing control input terminal is connected with the type output terminal of the mode type register 4; the pulse ①_2 output terminal is connected with an input terminal of the AND gate II 8, and the operand configuration operation control module IV; the pulse ②_2 output terminal is connected with the AND gate An input terminal of Ⅳ10 is connected to the operand configuration operation control module Ⅳ, the output terminal of pulse ③_2 is connected to the other input terminal of AND gate Ⅱ8; the output terminal of pulse ④_2 is connected to the other input terminal of AND gate Ⅳ10; the output terminal of pulse ⑤_2, The pulse ⑥_2 output terminal is connected to the operand configuration operation control module IV; the Busy output terminal outputs a Busy busy signal to the system;

The output end of the AND gate II 8 is connected to the read signal input end RD_2 of the operand memory II;

The two input terminals of the AND gate III9 are respectively connected to the system reset signal Rst line and the operand configuration operation control module IV;

When the reset input terminal is "1", the floating-point operand read timing control module III presets the operand value to the read address counter 6 under the action of the read preset pulse of pulse ①_1, and the operand memory II reads the port The initial value of the address is the value of the number of operands; under the action of the read start pulse of the first pulse ②_1, the work of the read operand pulse generation control module 7 is started, and the Busy output terminal changes from "1" to "0";

When the type signal input by the read timing control input terminal of the read operand pulse generation control module 7 is "0", pulses ③_2, pulse ④_2, pulse ⑤_2, and a pulse ⑥_2 are sent cyclically in sequence (see Figure 6). When the signal at the read overflow input terminal changes from "1" to "0", set the output terminals of pulse ③_2 and pulse ④_2 to "1", stop the generation of pulse ③_2 and pulse ④_2, and after one operation cycle time, the Busy output terminal changes from "0" to "0" In the "1" state, output the latch result pulse ⑤_2 of a clock cycle Clock, and then set the output terminal of pulse ⑤_2 to "1", and the floating-point operand read timing control module III stops working;

When the input type signal of the read timing control input terminal of the read operand pulse generation control module 7 is "1", pulse ①_2 and pulse ②_2 are sent out in sequence, and then pulse ③_2, pulse ④_2, and pulse ⑤_2 are sent cyclically in sequence (see Fig. 7), the generation process of pulse ③_2, pulse ④_2 and pulse ⑤_2 is the same as when the type signal is "0".

As shown in Figure 4, the operand configuration operation control module IV includes a strobe 11, a result register 12, an operand switch 13, a floating-point number division operator 14, an operation exception flag control 15, and a 32-bit tri-state gate group 16. AND gate V17, AND gate VI18, OR gate I19 and OR gate II20;

The two input terminals of the strobe 11 are respectively connected with the operand output terminal DB_2 of the operand memory II and the operation result output terminal of the floating-point number division operator 14, and the output terminal is connected with the input terminal of the result register 12; The control input terminal is connected with the output terminal of the AND gate V17;

The output end of the result register 12 is connected to the exchange number 1 input end of the operand switcher 13 and the 32-bit tri-state gate group 16 input ends; the result latch signal input end is connected to the output end of the AND gate VI18;

The exchange number 2 input terminal of the operand switcher 13 is connected to the operand output terminal DB_2 of the operand memory II, the exchange control terminal is connected to the output terminal of the OR gate I19, and the two output terminals are respectively connected to the floating-point number division operator 14 The input terminal of operand 1 and the input terminal of operand 2 are connected;

The operation result output end of described floating-point number division operator 14 is also connected with the operation result input end of operation exception flag control 15;

The latch result pulse input end of the operation abnormality flag control 15 is connected with the latch result pulse ⑤_2 output end of the read operand pulse generation control module 7; The other input terminal is connected, and the IRQ output terminal also outputs the interrupt request signal IRQ to the system; when the intermediate operation result or the final operation result is abnormal, the operation exception flag control 15 sends the interrupt request signal IRQ to the system, and resets the write operand Pulse generation control module 3 and read operand pulse generation control module 7;

The output end of the 32-bit tri-state gate group 16 is connected to the system data bus DB, and the control input end is connected to the output end of the OR gate II 20;

The two input terminals of the AND gate V17 are respectively connected with the output terminals of pulse ①_2 and pulse ②_2 of the read operand pulse generation control module 7;

The two input terminals of the AND gate VI18 are respectively connected to the output terminals of the pulse ②_2 and the pulse ⑤_2 of the read operand pulse generation control module 7;

An input end of the OR gate I19 is connected to the mode output end of the mode type register 4, and the other input end is connected to the pulse ⑥_2 output end of the read operand pulse generation control module 7;

The two input terminals of the OR gate II 20 are respectively connected to the CS signal output terminal of the controller identification 1 and the system read signal RD line; when CS is "0", under the action of the system RD signal, the intermediate operation result is read out Or the final operation result of command execution.

As shown in Figure 2, Figure 3 and Figure 4, the floating-point operand read timing control module III is connected to the type output of the mode type register 4; the operand configuration operation control module IV and the mode of the mode type register 4 The output terminal is connected; the definition of type is the type of the first operand read from the operand memory II, and the definition of mode is the processing method for the first operand to participate in the division operation when the type is "0";

Type 0: The first operand is used as operand 2 participating in the division operation, and the operation result is used as operand 1;

Type 1: The first operand is used as operand 1 participating in the division operation, and the second operand is used as operand 2;

The pulse 1._2 and pulse 2._2 output of the read operand pulse generation control module 7 are only generated when the type of the mode type register 4 output is "1"; When the gating control input terminal is "0", the gating device 11 outputs the first operand read from the operand memory II; when both pulse ①_2 and pulse ②_2 are "1", the gating device 11 outputs the operation result;

The first operand read from the operand memory II participates in the division operation, and the mode and type signal output by the mode type register 4 controls the division mode of the first operand and the operation result of the command being executed:

The mode is "0", the type is "0": what the type is "0" the output of the result register 12 is the operation result, the exchange number 1 input terminal of the operand switcher 13 is the operation result, and the exchange number 2 of the operand switcher 13 The input terminal is the first operand read from the operand memory II; when the first operand is read, the pulse ⑥_2 is "0" valid, and the operand switch 13 The control terminal of the operand switcher 13 is "0", the operation result of the input terminal of the switch number 1 of the operand switcher 13 is used as the operand 2 output by the operand switcher 13, the switch number of the operand switcher 13, and the first operand of the 2 input terminal As the operand 1 output by the operand switcher 13, that is, the 2 inputs and 2 outputs of the operand switcher 13 are exchanged and transmitted, and the division operation of the first operand/operation result is performed;

The mode is "1", and the type is "0": when reading the first operand, although the pulse ⑥_2 is "0" valid at this time, the mode is in the "1" state, so that the control terminal of the operand switch 13 is "1", the 2 inputs and 2 outputs of the operand switcher 13 are not exchanged and transmitted; the operation result is used as the operand 1 of the floating-point number division operator 14, and the first operand is used as the operand 2, and the operation result/ The division operation of the first operand;

When the type is "1", the configuration of the first operand has nothing to do with the signal state of the input mode, the read operand pulse generation control module 7 will not generate the pulse ⑥_2 signal, and the output terminal of the pulse ⑥_2 is in the "1" state, making the operation The control terminal of number switcher 13 is " 1 ", and 2 inputs and 2 outputs of operand switcher 13 do not exchange and transmit; The operand is operand 2, and the operation of the 1st operand/2nd operand is performed.

Claims (5)

1. A multi-floating-point operand division operation controller realizes multiple 32-bit floating-point number division operations that meet the IEEE754 standard, and is characterized in that: the controller includes a command word and its operand write sequence control module (I), Operand memory (II), floating-point operand read timing control module (III), operand configuration operation control module (IV); The command word and its operand writing sequence control module (I) are connected with the operand memory (II), the floating-point operand reading sequence control module (III), and the operand configuration operation control module (IV); The operand memory (II) is also connected to the floating-point operand read timing control module (III) and the operand configuration operation control module (IV); The floating-point operand read timing control module (III) is also connected to the operand configuration operation control module (IV); The command word and its operand write timing control module (I) controls and completes the writing and storage of the instruction, which needs to occupy the system bus; an instruction includes a 9-bit command word and several operands, and the operands are at most 127; When the command word and its operand write timing control module (Ⅰ) is selected by the system, the command word and its operand write timing control module (Ⅰ) is started to work, and the write timing pulse sequence synchronous with the system WR signal is generated internally; Under the control of the timing pulse, the command word of the multi-floating-point operand division instruction is latched, and the multi-floating-point operand is written into and stored; after the last operand is written into storage, the command word and its operand write timing control Module (I) stops working; The operand memory (II) is a dual-port memory, with a write-only port and a read-only port for storing floating-point operands (hereinafter referred to as operands); the write port operation of the operand memory (II) There is no need for arbitration for the writing of data and the reading of the read port operand; the write port of the operand memory (II) is controlled by the command word and its operand write timing control module (I), and the system data bus The operand transmitted by DB is written into the operand memory (II); the read port is controlled by the floating-point operand read timing control module (III), and the operand read is transmitted to the operand configuration operation control module (IV); The floating-point operand read timing control module (III) independently completes the reading of the floating-point operand from the operand memory (II) under the control of the internal read timing pulse, without occupying the system bus; the floating-point The operand read sequence control module (Ⅲ) is started to work after the command word and its operand write sequence control module (Ⅰ) write the first operand, and the output busy signal Busy changes from "1" to "0", and according to The first operand type, internally generates a read timing pulse sequence synchronized with the system clock Clock signal, and reads out the operands in order to participate in the division operation; after the last operand participating in the operation is read out, a division operation is performed In the time period, the output busy signal Busy changes from "0" to "1", and after sending a clock cycle Clock result latch pulse, stop the work of the floating-point operand read timing control module (Ⅲ); The operand configuration operation control module (IV) gates and configures operand 1 and operand 2 of the two input terminals of the division operator according to the division mode and type of the first operand transmitted by the operand memory (II), The operation result of each division operation can be latched to judge whether the operation result is abnormal; the system can read the intermediate operation result and the final operation result of command execution from the operand configuration operation control module (Ⅳ). 2. The multi-floating-point operand division operation controller as claimed in claim 1 is characterized in that: the command word and its operand write timing control module (I) includes a controller identification (1), a write address counter ( 2), write operand pulse generation control module (3), mode type register (4) and AND gate I (5); The input terminal of the controller identification (1) is connected to the A31 to A27 lines of the system address bus AB, the CS signal output terminal is connected to the write start signal input terminal of the write operand pulse generation control module (3), and the operand configuration operation control Module (Ⅳ) is connected; the address value of the controller identification (1) input A31 to A27 is equal to the address value set by the controller identification (1), then the CS signal output terminal of the controller identification (1) is " 0", otherwise the CS signal output terminal is "1"; The operand number input terminal of the write address counter (2) is connected to the D6 to D0 lines of the system data bus DB, and the write preset pulse input terminal is connected to the pulse ①_1 output terminal of the write operand pulse generation control module (3) , the write count pulse input terminal is connected to the pulse ③_1 output terminal of the write operand pulse generation control module (3), the write address output terminal is connected to the write address input terminal AB_1 of the operand memory (II), the write overflow output terminal and the AND gate One input terminal of Ⅰ(5) is connected; The write synchronization pulse input terminal of the write operand pulse generation control module (3) is connected to the system write signal WR line, the reset input terminal is connected to the output terminal of AND gate I (5), and the pulse ①_1 output terminal is also connected to the mode type register (4) The input terminal of the latch signal is connected as a read preset pulse to the floating-point operand read timing control module (Ⅲ), and the output terminal of pulse ②_1 is connected to the WR_1 input terminal of the write port of the operand memory (II) as a read The start pulse is connected to the floating-point operand read timing control module (Ⅲ); When CS is "0", the write operand pulse generation control module (3) starts working under the action of the first WR signal of the system, and outputs pulse ①_1, pulse ②_1, pulse ③_1 in sequence until the reset signal input terminal Stop working from "1"→"0", set the output terminals of pulse ①_1, pulse ②_1 and pulse ③_1 to "1" state; The input end of the mode type register (4) is connected to the D8 and D7 lines of the system data bus DB, the mode output end is connected to the operand configuration operation control module (IV), and the type output end is connected to the floating-point operand read timing control module (Ⅲ) connection; The other two input terminals of the AND gate I (5) are respectively connected to the system reset signal Rst line and the operand configuration operation control module (IV); When the controller recognizes (1) that the output CS signal changes from "1" to "0", the command word and its operand write timing control module (I) starts the write operand pulse generation control module (3) to work , write The operand pulse generation control module (3) sends out a timing pulse sequence signal synchronized with the system WR signal, and under the action of the falling edge of pulse ①_1, the division mode and type of the first operand of the command word of the instruction are latched in the mode type In the register (4), the value of the operand is preset to the write address counter (2) as the initial count value of the write address counter (2) and the write address initial value of the write port of the operand memory (II), and write The overflow output terminal is in the "1"state; pulse ②_1 is used as the WR_1 signal of the write port of the operand memory (II), and the operand is written into the operand memory (II); pulse ③_1 is used as the write count pulse of the write address counter (2) , so that every time an operand is written, a count pulse is generated, and the address value -1 output by the write address output terminal points to the address of the next storage unit of the operand memory (II) write port. When the address output by the write address output terminal When the value is reduced from the preset value to "0", the write overflow output terminal changes from "1" to "0", resets the write operand pulse generation control module (3), and sets all pulse output terminals to the "1" state. 3. The multi-floating-point operand division controller according to claim 1, characterized in that: the floating-point operand read timing control module (Ⅲ) includes a read address counter (6), a read operand pulse generation control Module (7), AND gate II (8), AND gate III (9) and AND gate IV (10); The operand number input terminal of the read address counter (6) is connected to the D6 to D0 lines of the system data bus DB, and the read preset pulse input terminal is connected to the pulse ①_1 output terminal of the write operand pulse generation control module (3) , the read count pulse input terminal is connected to the output terminal of AND gate IV (10), the read address output terminal is connected to the read address input terminal AB_2 of the operand memory (II), and the read overflow output terminal is connected to the read operand pulse generation control module ( 7) The read overflow input terminal connection; The read address counter (6) uses the number of operands of the input command as the initial value of the count and the initial value of the read address of the read port of the operand memory (II) under the action of the read preset pulse, and sets the read overflow output terminal signal as "1" state; each time a read count pulse comes, the read address value of the read address counter (6) is -1, and the address value of the read port storage unit in the operand memory (II) is modified, when the read address output by the read address counter (6) When the value is reduced from the preset value to "0", the read overflow output terminal changes from "1" to "0", and the read overflow output signal is a sign of the end of the operand read process; The read synchronization pulse input terminal of the read operand pulse generation control module (7) is connected to the system clock Clock line, the reset input terminal is connected to the output terminal of AND gate III (9), and the read start input terminal is connected to the write operand pulse generation The pulse ②_1 output terminal of the control module (3) is connected, the read timing control input terminal is connected to the type output terminal of the mode type register (4); the pulse ①_2 output terminal is connected to an input terminal of the AND gate II (8), and the operand configuration operation The control module (IV) is connected; the pulse ②_2 output terminal is connected with one input terminal of the AND gate IV (10), the operand configuration operation control module (IV) is connected, the pulse ③_2 output terminal is connected with the other input terminal of the AND gate II (8) Connection; the pulse ④_2 output terminal is connected to the other input terminal of the AND gate IV (10); the pulse ⑤_2 output terminal and the pulse ⑥_2 output terminal are connected to the operand configuration operation control module (IV); the Busy output terminal outputs a Busy busy signal to the system ; The output end of the AND gate II (8) is connected to the read signal input end RD_2 of the operand memory (II); The two input terminals of the AND gate III (9) are respectively connected to the system reset signal Rst line and the operand configuration operation control module (IV); When the reset input terminal is "1", the floating-point operand read timing control module (Ⅲ) presets the value of the operand to the read address counter (6) under the action of the read preset pulse of pulse ①_1, and the operand The initial value of the address of the read port of the memory (II) is the number of operands; under the action of the read start pulse of the first pulse ②_1, the work of the read operand pulse generation control module (7) is started, and the Busy output terminal changes from "1" to "0"; When the input type signal of the read timing control input terminal of the read operand pulse generation control module (7) is "0", pulses ③_2, pulse ④_2, pulse ⑤_2, and a pulse ⑥_2 are sent out in sequence, and when the read overflow input When the terminal signal changes from "1" to "0", set the output terminals of pulse ③_2 and pulse ④_2 to "1", stop the generation of pulse ③_2 and pulse ④_2, and after one calculation cycle time, the Busy output terminal changes from "0" to "1" state, output the latch result pulse ⑤_2 of a clock cycle Clock, and then set the output terminal of pulse ⑤_2 to "1", and the floating-point operand read timing control module (Ⅲ) stops working; When the input type signal of the read timing control input terminal of the read operand pulse generation control module (7) is "1", pulse ①_2 and pulse ②_2 are sent out in sequence, and then pulse ③_2, pulse ④_2, and pulse ⑤_2 are sent out in sequence, The generation process of pulse ③_2, pulse ④_2 and pulse ⑤_2 is the same as when the type signal is "0". 4. The multi-floating-point operand division operation controller according to claim 1, characterized in that: the operand configuration operation control module (IV) includes a gate (11), a result register (12), an operand Switcher (13), floating-point number division operator (14), operation exception flag control (15), 32-bit tri-state gate group (16), AND gate V (17), AND gate VI (18), or gate I (19) and OR gate II (20); The two input terminals of the strobe (11) are respectively connected with the operand output terminal DB_2 of the operand memory (II) and the operation result output terminal of the floating-point number division operator (14), and the output terminal is connected with the result register (12 ) is connected to the input terminal; the gating control input terminal is connected to the output terminal of AND gate V (17); The output terminal of the result register (12) is connected to the input terminal of the exchange number 1 of the operand switch (13) and the input terminal of the 32-bit tri-state gate group (16); the input terminal of the result latch signal is connected to the AND gate VI (18 ) output connection; The exchange number 2 input terminal of the operand switch (13) is connected to the operand output terminal DB_2 of the operand memory (II), the exchange control terminal is connected to the output terminal of the OR gate I (19), and the two output terminals are respectively It is connected with the operand 1 input terminal and the operand 2 input terminal of the floating-point number division operator (14); The operation result output terminal of the floating-point number division operator (14) is also connected to the operation result input terminal of the abnormal operation flag control (15); The latch result pulse input terminal of the abnormal operation flag control (15) is connected to the latch result pulse ⑤_2 output terminal of the read operand pulse generation control module (7); the IRQ output terminal is connected to the other of the AND gate I (5) The input terminal is connected to the other input terminal of gate III (9), and the IRQ output terminal also outputs an interrupt request signal IRQ to the system; when the intermediate operation result or the final operation result is abnormal, the operation abnormal flag control (15) sends The system sends an interrupt request signal IRQ, and resets the write operand pulse generation control module (3) and the read operand pulse generation control module (7); The output end of the 32-bit tri-state gate group (16) is connected to the system data bus DB, and the control input end is connected to the output end of the OR gate II (20); The two input terminals of the AND gate V (17) are respectively connected to the output terminals of pulse ①_2 and pulse ②_2 of the read operand pulse generation control module (7); The two input ends of the AND gate VI (18) are respectively connected to the output ends of pulse ②_2 and pulse ⑤_2 of the read operand pulse generation control module (7); One input terminal of the OR gate I (19) is connected to the mode output terminal of the mode type register (4), and the other input terminal is connected to the pulse ⑥_2 output terminal of the read operand pulse generation control module (7); The two input terminals of the OR gate II (20) are respectively connected to the CS signal output terminal of the controller identification (1) and the system read signal RD line; when CS is "0", under the action of the system RD signal, Read out the intermediate operation result or the final operation result of command execution. 5. multi-floating-point operand division operation controller as claimed in claim 1, is characterized in that: described floating-point operand read timing control module (Ⅲ) is connected with the type output terminal of mode type register (4); The operand configuration operation control module (Ⅳ) is connected to the mode output terminal of the mode type register (4); the definition of the type is the type of the first operand read from the operand memory (II), and the definition of the mode is when When the type is "0", the first operand participates in the processing method of the division operation; When the operand type is "0": the strobe (1) outputs the operation result output by the output register (16), and under the action of the falling edge of the pulse ① output by the pulse generator (9), the operation result register (2 ) the operation result output by the latch result output register (16), the output terminal of the OR gate II (7) changes from "1" to "0", the output terminal of the AND gate I (8) changes from "1" to "0", The operand register (3) latches the operand from the system bus DB, then the division operation of the first operand read from the operand memory (II) is processed in the following two ways: The operation mode is "0": the output of the result register (12) is the operation result, the input terminal of the exchange number 1 of the operand switcher (13) is the operation result, and the input terminal of the exchange number 2 of the operand switcher (13) is the slave The first operand read from the operand memory (II); when the first operand is read, the pulse ⑥_2 is "0" valid at this time, and because the mode is "0", the operand switch (13) The control terminal of the operand switcher (13) is "0", and the operation result of the switch number 1 input terminal of the operand switcher (13) is used as the operand 2 output by the operand switcher (13), and the switch number 2 input terminal of the operand switcher (13) is The first operand is used as operand 1 output by the operand switch (13), that is, the two inputs and two outputs of the operand switch (13) are exchanged and transmitted, and the division of the first operand/operation result is performed operation; The operation mode is "1": When reading the first operand, although the pulse ⑥_2 is "0" at this time, it is valid, but the mode is "1", so that the control terminal of the operand switch (13) is "1" , the 2 inputs and 2 outputs of the operand switcher (13) are not exchanged and transmitted; the operation result is used as operand 1 of the floating-point number division operator (14), the first operand is used as operand 2, and the operation result is executed / Division of the first operand; When the operand type is "1", the configuration of the first operand has nothing to do with the signal state of the input mode, the read operand pulse generation control module (7) will not generate the pulse ⑥_2 signal, and the output of the pulse ⑥_2 is "1" state, so that the control end of the operand switch (13) is "1", and the 2 inputs and 2 outputs of the operand switch (13) do not exchange and transmit; the first operand is used as a floating-point number division operator ( 14) For operand 1, the second operand is used as operand 2, and the operation of the first operand/second operand is performed.

Images