CN103645880B - Double instruction many floating-point operations number plus/minus arithmetic and control units - Google Patents

Abstract

A kind of double instruction many floating-point operations number plus/minus arithmetic and control unit, writes time-sequence control mode, operand store, memorizer reading time-sequence control mode, memory data sky mark controller and computing and output control module including command word and multioperand thereof；This controller application FPGA design Hard link control circuit, it is possible to storage floating-point operation number plus/minus operational order more than two, wherein, an instruction performs, and another instruction is pending；Or an instruction performs, another instructs write；Or an instruction write, performed by reading simultaneously；In instruction ablation process, what internal generation was Tong Bu with system WR writes time sequential pulse sequence, the write of control command and the storage of operand；During order performs, the reading time sequential pulse sequence that internal generation is Tong Bu with system Clock, control the reading of operand, independently complete all of plus/minus computing, not by system control；System can read the intermediate object program of each computing and the final result of computing.

Description

Double instruction many floating-point operations numbers add / Subtract arithmetic and control unit

Technical field

The present invention relates to a kind of double instruction many floating-point operations number plus/minus arithmetic and control unit, particularly relate to a kind of based on using the hardwired double instruction many floating-point operations number plus/minus arithmetic control circuits of FPGA parallel work-flow circuit and sequential control method thereof.

Background technology

Floating number plus/minus realizes 2 32 the floating number plus/minus computings meeting IEEE754 standard arithmetical unit；Arithmetical unit, input participated in two floating-point operation numbers of computing, and one is operand 1, and one is operand 2, performed a sub-addition or subtraction one operation result of output, and in calculating process, operand 1 and operand 2 must remain stable；The outfan of operand 1 input of arithmetical unit and a buffer connects, and operand 2 input is directly connected with the internal data bus of microprocessor, or be connected with the outfan of another buffer；Its operating process is divided into two kinds of situations, a kind of situation is that timesharing is passed through the internal data bus of microprocessor operand 1 and operand 2 are transmitted separately to two buffers of arithmetical unit, computing terminates to be write back in the buffer leaving operand 1 in by operation result by the internal data bus of microprocessor again, and by data bus transmission a to memory element of memorizer；The second situation be operand 1 be the result of computing last time, last time operation result written-back operation number 1 buffer in after, then transmit operand 2, then carry out computing；It is the internal data bus time-sharing operation by microprocessor that operation result writes back the processing procedure with the transmission of operand 2, if the internalarithmetic time is 2 or 3 clock cycle, the transmission of floating-point operation number, write back and the computing of operation result will take multiple system clock cycle Clock；If there being multiple continuous print plus and minus calculation, such as 7 operands, 6 operational orders are needed to be achieved, perform these 6 instructions and need fetching and Instruction decoding 6 times, result writes back 6 times, and operand 2 sends the input of arithmetical unit to and result to write back to the process of operand 1 buffer be to be sent control pulse by microprocessor controls to process, be unfavorable for improving the speed that the instruction of arithmetical operation class performs further；The design of floating number plus/minus arithmetical unit is also adopted by the mode that streamline performs, calculating process is divided into some modules, under the control of the time sequential pulse sent at microprocessor controls, a plurality of floating number plus/minus operational order performs according to sequence of modules, and every ordering calculation in streamline terminates to be required for writing back operation result；But need the operation result applying a upper operational order as the instruction of operand for performed floating number plus/minus method instruction, then the pile line operation of floating number plus/minus computing is ineffective, have impact on the speed that floating number plus/minus operational order performs.

Summary of the invention

It is an object of the invention to provide a kind of double instruction many floating-point operations number plus/minus arithmetic and control unit, the hardware circuitry of application FPGA design double instruction many floating-point operations number plus/minus arithmetic and control unit；Many floating-point operations number plus/minus algorithm of this controller and the write of multioperand thereof need to take system bus, and the execution ordered is not take up system bus；Can also store floating-point operation number plus/minus operational order more than two, wherein, an instruction is carrying out processing, and the order of another instruction and many floating-point operations number (lower referred to as operand) thereof are pending；Or an instruction is carrying out processing, order and the multioperand thereof of another instruction are currently written into controller；Or the order of an instruction and multioperand thereof are currently written into controller, and two instructions simultaneously are performed process；During the order and multioperand writing controller thereof of an instruction, what the internal generation of controller was Tong Bu with system WR signal writes time series pulse signals, under the effect writing time series pulse signals, it is stored in built-in function number memorizer according to sequential write algorithm and operand；In order performs processing procedure, controller is internal produces the reading time series pulse signals Tong Bu with system clock Clock signal, computing is performed reading read operation number under time series pulse signals controls, it is independently to complete all of plus/minus computing, not by system control under time series pulse signals effect is read in inside that order performs processing procedure；In controller performs command process, system can read the intermediate object program in calculating process and final operation result.

The technical scheme solving above-mentioned technical problem is: a kind of double instruction many floating-point operations number plus/minus arithmetic and control units, relate to a kind of based on using the hardwired double instruction many floating-point operations number plus/minus arithmetic control circuits of FPGA parallel work-flow circuit and sequential control method thereof, write time-sequence control mode, memorizer reading time-sequence control mode, memory data sky mark controller, computing and output control module including operand store, command word and multioperand thereof；

Time-sequence control mode write by described operand store with command word and multioperand thereof, time-sequence control mode read by memorizer, computing is connected with output control module；

Described command word and multioperand thereof are write time-sequence control mode and are also connected with output control module with memorizer reading time-sequence control mode, memory data sky mark controller, computing；

Described memorizer is read time-sequence control mode and is also connected with output control module with memory data sky mark controller, computing；

Described operand store is dual-ported memory, write port, read port, is used for storing floating-point operation number (lower referred to as operand)；Described operand store is divided into memorizer 1 and 2 two memory areas of memorizer；The write address high position input AB5_1 of described operand store is " 0 ", or reading address high input AB5_2 is " 0 ", chooses 26 low address memory element of operand store, i.e. memorizer 1；Write address high position input AB5_1 is " 1 ", or reading address high input AB5_2 is " 1 ", chooses 26 high address memory element of operand store, i.e. memorizer 2；

Described command word and multioperand thereof are write time-sequence control mode and have been controlled write and the storage of instruction, need to take system bus；Article one, instruction includes 32 order of the bit words and several operands, and operand is up to 26；It is empty for data at memorizer 1 or the memorizer 2 of operand store that described command word and multioperand thereof write time-sequence control mode, and output write command allows signal, side to allow to be chosen by system；When being chosen write order word by system, under the effect of system WR signal, write plus/minus algorithm word；When being chosen write operation number by system, command word and multioperand thereof are write internal generation of time-sequence control mode and Tong Bu with system WR signal are write time sequential pulse；Under the control writing time sequential pulse, being stored in by operand in memorizer 1 or the memorizer 2 of operand store, after last operand of an instruction is written into storage, that changes operand store writes high address input AB5_1 state；If the memorizer of operand store 1 and memorizer 2 all non-NULLs, cease and desist order word and multioperand writes the work of time-sequence control mode；

Described memorizer reading time-sequence control mode, under the control of time sequential pulse is read in inside, independently completes many floating-point operations number and reads from operand store, it is not necessary to take system bus；Described memorizer is read time-sequence control mode and is produced the reading time sequential pulse sequence Tong Bu with system clock Clock signal, operand reads participation in order and adds deduct computing；After last operand participating in computing reads, produce and read address spill over, the most again through an execution cycle added deduct, send and read the signal that running status terminates, produce the result latch pulse of a clock cycle Clock, send startup the most again and enable signal；

Described memorizer is read time-sequence control mode and is performed according to the empty flag states read operation of memory data sky mark controller, has following 4 kinds of duties:

1) described memory data sky mark controller no memory 1 mark empty, memorizer 2 sky exports, show that memorizer 1, memorizer 2 are all data non-NULL, the memorizer of one non-NULL is currently written into instruction or write instruction process terminates, and another memorizer is just at read operation number；If the order computing being carrying out terminates, start and enable signal by " 1 " → " 0 ", transfer a memorizer sky to, the state of another memorizer non-NULL, the enabling signal that now trailing edge of the 1st system clock Clock after order calculating process terminates occurs as time sequential pulse, sends write command to system and allows signal；Start memorizer and read the work of time-sequence control mode；

2) described memory data sky mark controller exports the mark that any one memorizer is empty, can be in two kinds of modes of operation, and one is that the memorizer of non-NULL is currently written into operand, and this memorizer performs read operation simultaneously；Two is that the memorizer write instruction process of non-NULL terminates, is carrying out read operation；If order calculating process terminates, startup enable signal, by " 1 " → " 0 ", transfers memorizer 1 and the state of memorizer 2 all skies to；

3) described memory data sky mark controller output storage 1 sky, the mark of memorizer 2 sky simultaneously, stops memorizer and reads the work of time-sequence control mode, sends write command to system and allows signal；

4) described memory data sky mark controller output storage 1 sky, the mark of memorizer 2 sky simultaneously, and command word and multioperand thereof write time-sequence control mode and again chosen writing commands word, command word and multioperand thereof to write time-sequence control mode output by system to write presetting pulse and read the enabling signal of inside sequence timer of time-sequence control mode as floating-point operation number；

Described computing and output control module, according to operand type, carry out gating control to the 1st operand participating in computing, and it is from operation result or the 1st operand read from operand store that gating configuration participates in the operand 1 of plus/minus computing；Computing and output control module determine according to operator and carry out addition or subtraction, intermediate results of operations latches operation result under the result latch signal effect that time-sequence control mode sends read by memorizer, and judge that operation result is the most abnormal, if there is exception, send irq signal to system, stop memorizer and read the work of time-sequence control mode；When system needs to read operation result, intermediate calculation results and the final operation result of order execution can be read under the effect of system RD signal.

Its further technical scheme is: described command word and multioperand thereof write time-sequence control mode include module's address identification, write high address controller, write port address counter, write port pulsing controller, pending command register, operator depositor, perform command register, operator shift register, not gate I, not gate II or door I or door II or door III or door IV and door I and with door II；

A31 to the A27 line of described module's address identification input and system address bus AB connects, CS1 outfan and or input of door II connect, CS2 outfan and or an input of door III, the enable input of write port pulsing controller, computing be connected with output control module；

Arranging two address values inside described module's address identification, one is write order word address value, and one is write operation number address value；The address value of A31 to the A27 of the system address bus AB of described module's address identification input compares with the address value of setting in module's address identification, if with write order word address value is equal, then output CS1 is " 0 ", if equal with write operation number address value, then output CS2 is " 0 "；At any time, CS1 and CS2 only one of which is output as " 0 ", or output is all " 1 "；

The Writing overflow outfan of the described latch signal input and write port address counter writing high address controller is connected, the outfan writing high address input and not gate II connects, the RESET input and the outfan with door I are connected, and outfan and the input of not gate II, the write address high position input AB5_1 of operand store, memory data sky mark controller connect；

It is described that write the output of high address controller is highest addresses value AB5_1 of operand store；When the memorizer 1 of operand store and the data of memorizer 2 are all empty, or when systematic reset signal Rst is " 0 ", resetting and write high address controller, it is output as " 0 "；When writing the latch signal input of high address controller by " 1 " → " 0 ", write the AB5_1 state upset of high address controller output end output；

The operand number input of described write port address counter is connected with D4 to the D0 line of system data bus DB, write presetting pulse input and or door II outfan connect, write count pulse input to be connected with pulse 2. _ 1 outfan of write port pulsing controller, write the RESET input and systematic reset signal Rst line connects, the write address input AB_1 of write address outfan and operand store connects, and Writing overflow outfan also connects with the Writing overflow input of write port pulsing controller, the input of not gate I, memory data sky mark controller；

The described write port address counter substantially enumerator that subtracts 1, D4 to the D0 transmission of system DB is operand the numerical value participating in plus/minus computing, when the memorizer 1 of operand store is empty or memorizer 2 is empty, and when meeting the CS2 outfan of module's address identification for " 0 ", operand numerical value is preset to write port address counter as the low 5 bit address initial values of operand store write port as writing presetting pulse by WR signal, and Writing overflow outfan is set to one state；

Low 5 bit address values AB_1 of write port of described write port address counter output function number memorizer；When writing count pulse input and carrying out a count pulse, write port address counter carries out once-1 operation, until write address outfan is " 0 ", AB_1 is " 0 ", now Writing overflow signal output part is by " 1 " → " 0 ", Writing overflow signal is as the out-of-work mark of write port address counter so that when writing the latch signal input of high address controller by " 1 " → " 0 ", writes the AB5_1 state upset of high address controller output；Write port address counter under the effect of systematic reset signal Rst, reset write port address counter so that Writing overflow signal output part is " 0 " state；

The clock terminal of described write port pulsing controller is connected with system write signal WR line, starts input and the outfan with door II is connected, and the write signal input WR_1 of pulse 1. _ 1 outfan and operand store connects；

The enable input of described write port pulsing controller is " 0 ", work is started under the pulse signal effect starting input, send the pulse 1. _ 1 with system WR impulsive synchronization and pulse 2. _ 1, pulse 1. _ 1 writes count pulse as the write signal WR_1 of operand store, pulse 2. _ 1 as write port address counter；Described write port address is when Writing overflow signal output part is by " 1 " → " 0 ", and described write port pulsing controller quits work, and the outfan of pulse 1. _ 1 and pulse 2. _ 1 is one state；

D5 to the D0 line of the command input end of described pending command register and system data bus DB connects, latch signal input and or the outfan of door II connect, outfan and being connected with the command input end performing command register；

The operator input of described operator depositor and D31 to the D6 line of system data bus DB connect, latch input terminal and or the outfan connection of door II, the operator input connection of outfan and operator shift register；

The latch signal input of described execution command register is read time-sequence control mode with memorizer and is connected, and class type output terminal, the several several outfans of read operation are read time-sequence control mode with memorizer and are connected；

The operand type of described execution command register output is 2 kinds:

Type 0: the 1st operand in the memorizer 1 of write operation number memorizer or memorizer 2 is as the operand 2 of participation plus/minus computing, and operation result is as operand 1；

Class1: the 1st operand in the memorizer 1 of write operation number memorizer or memorizer 2 is as the operand 1 of participation plus/minus computing, and the 2nd operand is as operand 2；

The latch signal input of described operator shift register, shift pulse input are read time-sequence control mode with memorizer and are connected, and outfan is connected with output control module with computing；

Described operator shift register is under the effect of shift pulse, and the operator data in operator shift register move right 1 in order, and its lowest order exports as operator；

The outfan of described not gate I and an or input connection of door I；

Another input of described or door I and or the outfan of door IV connect, outfan allows signal to system output writer instruction；

Another two inputs of described or door II respectively and or the outfan of door IV, system WR write signal line connect, outfan is also read time-sequence control mode with memorizer and is connected as writing preset signal；

Another input described or door III is connected with system WR write signal line, outfan and being connected with an input of door II；

Described or door IV two inputs outfan empty with the memorizer 1 of memory data sky mark controller, the empty outfan of memorizer 2 respectively are connected, and outfan also and is connected with another input of door II；

Described outfan all empty with an input of door I and memorizer 1 memorizer 2 of memory data sky mark controller is connected, and another input is connected with system Rst reseting signal line.

Its further technical scheme is: described memorizer read time-sequence control mode include reading high address controller, read port address enumerator, read port pulsing controller, biconditional gate, not gate III, not gate IV or door V or door VI and door III and door IV and door V and door VI and with door VII；

The latch signal input of described reading high address controller overflows outfan with the reading of read port address enumerator and is connected, the outfan reading high address input and not gate III connects, the RESET input and the outfan with door III are connected, and the reading address high input AB5_2 of outfan and operand store, the input of not gate III connect；

What described reading high address controller exported is highest addresses value AB5_2 of operand store read port, when the memorizer 1 of operand store and the data of memorizer 2 are all empty, or when systematic reset signal Rst is " 0 ", resetting and read high address controller, its outfan is " 0 "；When the latch signal input of reading high address controller is by " 1 " → " 0 ", read the AB5_2 signal upset of high address controller output；

The presetting pulse input of reading of described read port address enumerator is connected with pulse 2. _ 2 outfan of read port pulsing controller, read count pulse input and the outfan with door VII is connected, the RESET input and the outfan with door V are connected, the several several inputs of read operation are connected with the several several outfans of read operation performing command register, read to overflow the outfan reading also with read port pulsing controller and overflow input, the reading of memory data sky mark controller is overflowed input and is connected, read address output end to be connected with the reading address input end AB_2 of operand store；

The described read port address enumerator substantially enumerator that subtracts 1, read presetting pulse and will be preset to read port address enumerator from the several number of read operation performing command register output, the address value AB_2 reading address output end output making read port address enumerator is the several number of read operation, and read port address enumerator proceeds by-1 counting from the several number of read operation；When reading count pulse input and carrying out a count pulse, the reading address value-1 of read port address enumerator output, until reading address output end is " 0 ", AB_2 is " 0 ", show that last operand reads, spill over outfan is by " 1 " → " 0 ", and spill over is also the out-of-work mark of read port address enumerator；When inputting reset signal and being " 0 ", reset read port address enumerator, read port address enumerator stops Counts, and overflowing outfan is " 0 "；

The clock terminal of described read port pulsing controller is connected with clock signal Clock line, starts input and is connected with door IV, and the RESET input and the outfan with door V are connected, and type input is connected with the class type output terminal performing command register；Pulse 1. _ 2 outfan is connected with the latch signal input performing command register and operator shift register, pulse 3. _ 2 outfan and an input with door VI, computing is connected with output control module, pulse 4. _ 2 outfan and an input with door VII, computing is connected with output control module, pulse 5. _ 2 outfan and being connected with another input of door VI, pulse 6. _ 2 outfan and being connected with another input of door VII, pulse 7. _ 2 outfan and computing are connected with output control module, read running status outfan to be connected with the reading running status input of memory data sky mark controller, start enable outfan and or an input of door VI, the startup of memory data sky mark controller enables input and connects；

The pulse of described read port pulsing controller output is Tong Bu with system clock Clock；When memorizer 1 or the memorizer 2 of operand store are that data are empty, when starting input by " 1 " → " 0 ", start read port pulsing controller and start working；When the memorizer 1 of operand store and memorizer 2 are all data sky, under the effect writing presetting pulse, start outfan by " 1 " → " 0 ", start read port pulsing controller and start working；The reading running status outfan putting read port pulsing controller while startup is one state for " 0 " and startup enable outfan；When reading running status and being " 1 ", show that the calculating process executed of the current command terminates；When starting enable signal and being " 0 ", show not order in execution, and exectorial operation result latches；

Described read port pulsing controller is " 0 " or for " 1 " according to type input signal, determines the pulse train reading to control operation；When the spill over of read port address enumerator output is produced trailing edge by " 1 " → " 0 ", read port pulsing controller is again through an execution cycle time, read running status outfan by " 0 " → " 1 ", and send a system clock Clock cycle and deposit the pulse 7. _ 2 of final operation result, start and enable outfan by " 1 " → " 0 ", stopping the work of read port pulsing controller, putting all pulse output ends is one state；When the reset signal of input is " 0 ", reset read port pulsing controller, resets and makes to read running status outfan to be one state, and starting enable outfan is " 0 ", putting all pulse output ends is one state, and stops the work of read port pulsing controller；

Two inputs of described biconditional gate outfan empty with the memorizer 1 of memory data sky mark controller, the empty outfan of memorizer 2 respectively are connected, outfan and or another input connection of door VI；

The input of described not gate IV and or the outfan of door II write preset signal and connect, outfan and or an input of door V connect；

The all empty outfan of memorizer 1 memorizer 2 of described or another input of door V and memory data sky mark controller connects, outfan and being connected with an input of door IV；

Described or the outfan of door VI and being connected with another input of door IV；

Described outfan all empty with an input of door III and memorizer 1 memorizer 2 of memory data sky mark controller is connected, and another input and systematic reset signal Rst line connect；

A described input with door V is connected with systematic reset signal Rst line, and another input and computing are connected with output control module；

Described it is connected with reading address input end RD_2, the shift pulse input of operator shift register of operand store with the outfan of door VI.

Its further technical scheme is: described computing and output control module include gate, result register, floating number plus/minus arithmetical unit, computing abnormality mark control, 32 triple gate groups or door VII or door VIII and or door Ⅸ；

Two inputs of described gate operation result outfan with the reading data output end DB_2 of operand store, floating number plus/minus arithmetical unit respectively is connected, gating control input and or door VII outfan connect, outfan is connected with the input of result register；

Described gate completes to perform the option and installment of the operand 1 of the 1st computing of order according to operand type, when operand type is " 1 ", read port pulsing controller sends and reads the pulse 3. _ 2 of first operand from operand store and write count pulse 4. _ 2；When pulse 3. _ 2 or pulse 4. _ 2 are " 0 ", the 1st operand that the output of described gate reads from operand store；When pulse 3. _ 2 and pulse 4. _ 2 are all " 1 ", gate output operation result；

The latch pulse input of described result register and or the outfan of door VIII connect, outfan and operand 1 input of floating number plus/minus arithmetical unit, 32 triple gate group inputs connect；

Operand 2 input of described floating number plus/minus arithmetical unit and the data output end DB_2 of operand store connect, the operator outfan of operator input and operator shift register connects, and the input that operation result outfan also controls with computing abnormality mark is connected；

Described floating number plus/minus carries out addition or subtraction according to operator arithmetical unit, when operator input is " 0 ", controls floating number plus/minus and carries out additive operation arithmetical unit, when operator input is " 1 ", carry out subtraction；

The latch pulse input that described computing abnormality mark controls is connected with pulse 7. _ 2 outfan of read port pulsing controller, outfan and being connected with an input of door V, and to system output interrupt request singal IRQ；

The operation result of described floating number plus/minus arithmetical unit is latched in result register, and in computing abnormality mark control module；When intermediate calculation results or final operation result occur abnormal, computing abnormality mark controls to send interrupt request singal IRQ to system, and reset read port address enumerator and read port pulsing controller, stop read port address enumerator and the work of read port pulsing controller；

The outfan of described 32 triple gate groups is connected with system data bus DB, controls end and or the outfan connection of door Ⅸ；

Described or door VII two inputs are connected with pulse 3. _ 2, pulse 4. _ 2 outfan of read port pulsing controller respectively；

Described or door VIII two inputs are connected with pulse 4. _ 2, pulse 7. _ 2 outfan of read port pulsing controller respectively；

Described or door Ⅸ two inputs are connected with CS2 outfan, the system read signal RD line of module's address identification respectively, when CS2 is " 0 ", under the effect of system RD signal, read intermediate calculation results and the final operation result of order execution.

Owing to using above structure, double instruction many floating-point operations number plus/minus arithmetic and control units of the present invention have the advantages that

One, Autonomous Control instruction performs function

Double instruction many floating-point operations number plus/minus arithmetic and control units of the present invention are in execution process instruction, controller is internal produces the reading time sequential pulse sequence Tong Bu with system Clock, under the control reading time sequential pulse sequence, read operation number from the memorizer of controller, independently complete the plus/minus computing of all operations number of this instruction, not by system control.

Two, double parallel instructions process function

It is provided with an operand store inside double instruction many floating-point operations number plus/minus arithmetic and control units of the present invention, it is divided into memorizer 1 and 2 two memory modules of memorizer, the algorithm of the plus/minus operational order of floating-point operation number more than two and multiple operand can be stored, in order ablation process, the internal generation write of writing time sequential pulse sequence control command Tong Bu with system WR and the storage of operand；During order performs, inside produces the read time sequential pulse sequence Tong Bu with system Clock and controls the reading of operand；Article one, instruction performs, and another instruction is pending；Or an instruction is carrying out, another instructs write；Or the instruction of a life is currently written into, performed by reading simultaneously.

Three, the plus/minus computing of the instruction multiple operands of execution

The present inventionItIn double instruction many floating-point operations number plus/minus arithmetic and control units, every plus/minus operational order can have26Individual operand, such instruction is equivalent to a plurality of instruction of identical plus/minus computing, and the system that decreases, to the decoding of command operation code and order transmission operating process, improves processing speed.

Four, controller cost performance is high

Double many floating-point operations number plus/minus arithmetic and control units Hard link control circuits with FPGA that instruct of the present invention are as core, application is write time sequential pulse control, is read time sequential pulse control, can reach independently to complete many floating-point operations number plus/minus computing, two instructions simultaneously can the purpose of parallel processing, multiple operand plus/minus computings are had only to send an instruction i.e. complete multioperand and add deduct computing, the system that improves performs the speed of job sequence, has higher cost performance.

With embodiment, the technical characteristic of double instruction execution controller for floating-point number addition/subtractionoperation operation of the present invention is further described below in conjunction with the accompanying drawings.

Accompanying drawing explanation

The system architecture diagram of double instruction many floating-point operations number plus/minus arithmetic and control units of Fig. 1: the present invention；

The operand store port map of double instruction many floating-point operations number plus/minus arithmetic and control units of Fig. 2: the present invention；

The command word of double instruction many floating-point operations number plus/minus arithmetic and control units of Fig. 3: the present invention and multioperand thereof write the circuit connection diagram of time-sequence control mode；

The memory data sky mark director port figure of double instruction many floating-point operations number plus/minus arithmetic and control units of Fig. 4: the present invention；

The circuit connection diagram of time-sequence control mode read by the memorizer of double instruction many floating-point operations number plus/minus arithmetic and control units of Fig. 5: the present invention；

The computing of double instruction many floating-point operations number plus/minus arithmetic and control units of Fig. 6: the present invention and the circuit connection diagram of output control module；

The empty logical judgment figure of memorizer 1 of double instruction many floating-point operations number plus/minus arithmetic and control units of Fig. 7: the present invention；

The empty logical judgment figure of memorizer 2 of double instruction many floating-point operations number plus/minus arithmetic and control units of Fig. 8: the present invention；

Double instruction many floating-point operations number plus/minus arithmetic and control units of Fig. 9: the present invention write sequential chart；

The memorizer 1 of double instruction many floating-point operations number plus/minus arithmetic and control units of Figure 10: the present invention and memorizer 2 empty startup sequential chart；

The memorizer 1 of double instruction many floating-point operations number plus/minus arithmetic and control units of Figure 11: the present invention or memorizer 2 empty startup sequential chart；

The reading sequential chart of double instruction many floating-point operations number plus/minus arithmetic and control units of Figure 12: the present invention；

The command word of double instruction many floating-point operations scale multiplication controllers of Figure 13: the embodiment of the present invention two and multioperand thereof write the circuit connection diagram of time-sequence control mode；

The computing of double instruction many floating-point operations scale multiplication controllers of Figure 14: the embodiment of the present invention two and the circuit connection diagram of output control module.

In figure:

I operand store, II command word and multioperand thereof write time-sequence control mode, and III memorizer reads time-sequence control mode, IV memory data sky mark controller, V computing and output control module；

null1 module's address identification，2 write high address controller，3 write port address counters，4 write port pulsing controller，5 pending command registers，6 operator depositors，7 perform command register，8 operator shift registers、9 not gates I，10 not gates II，11 or door I，12 or door II，13 or door III，14 or door IV，15 with door I，16 with door II，17 read high address controller，18 read port address enumerators，19 read port pulsing controller，20 biconditional gates，21 not gates III，22 not gates IV，23 or door V，24 or door VI，25 with door III，26 with door IV，27 with door V，28 with door VI，29 with door VII，30 gates，31 result registers，32a floating number plus/minus arithmetical unit，32b floating number multiplication device，33 computing abnormality marks control，34 32 triple gate groups，35 or door VII，36 or door VIII，37 or door Ⅸ.

Abbreviation explanation in literary composition:

FPGA-Field Programmable Gate Array, field programmable gate array；

DB-Data Bus, data/address bus；

AB-Address Bus, address bus；

CS-Chip Select, sheet choosing or enable, in figure, CS represents " enable signal "；

Clock-clock；

RD-Read, reads, and represents " read signal " in figure；

WR-Write, writes, and represents " write signal " in figure；

IRQ-Interrupt Request, interrupts application, represents " interrupt request singal " in figure；

Rst-Reset, resets.

Detailed description of the invention

Embodiment one:

A kind of double instruction many floating-point operations number plus/minus arithmetic and control unit, as it is shown in figure 1, this controller includes that operand store I, command word and multioperand thereof write time-sequence control mode II, memorizer reads time-sequence control mode III, memory data sky mark controller IV, computing and output control module V；

Time-sequence control mode II write by described operand store I with command word and multioperand thereof, time-sequence control mode III read by memorizer, computing is connected with output control module V；

Described command word and multioperand thereof are write time-sequence control mode II and are also connected with output control module V with memorizer reading time-sequence control mode III, memory data sky mark controller IV, computing；

Described memorizer is read time-sequence control mode III and is also connected with output control module V with memory data sky mark controller IV, computing；

Described operand store I is dual-ported memory, write port, read port, is used for storing floating-point operation number (lower referred to as operand)；Described operand store I is divided into memorizer 1 and 2 two memory areas of memorizer；The write address high position input AB5_1 of described operand store I is " 0 ", or reading address high input AB5_2 is " 0 ", chooses 26 low address memory element of operand store I, i.e. memorizer 1；Write address high position input AB5_1 is " 1 ", or reading address high input AB5_2 is " 1 ", chooses 26 high address memory element of operand store I, i.e. memorizer 2；

Described command word and multioperand thereof are write time-sequence control mode II control and are completed write and the storage of instruction, need to take system bus；Article one, instruction includes 32 order of the bit words and several operands, and operand is up to 26；It is empty for data at memorizer 1 or the memorizer 2 of operand store I that described command word and multioperand thereof write time-sequence control mode II, and output write command allows signal, side to allow to be chosen by system；When being chosen write order word by system, under the effect of system WR signal, write plus/minus algorithm word；When being chosen write operation number by system, command word and multioperand thereof are write internal generation of time-sequence control mode II and Tong Bu with system WR signal are write time sequential pulse；Under the control writing time sequential pulse, being stored in by operand in memorizer 1 or the memorizer 2 of operand store I, after last operand of an instruction is written into storage, that changes operand store I writes high address input AB5_1 state；If the memorizer 1 of operand store I and memorizer 2 all non-NULLs, cease and desist order word and multioperand writes the work of time-sequence control mode II；

Described memorizer reading time-sequence control mode III, under the control of time sequential pulse is read in inside, independently completes many floating-point operations number and reads from operand store I, it is not necessary to take system bus；Described memorizer is read time-sequence control mode III and is produced the reading time sequential pulse sequence Tong Bu with system clock Clock signal, operand reads participation in order and adds deduct computing；After last operand participating in computing reads, produce and read address spill over, the most again through an execution cycle added deduct, send and read the signal that running status terminates, produce the result latch pulse of a clock cycle Clock, send startup the most again and enable signal；

Described memorizer is read time-sequence control mode III and is performed according to the empty flag states read operation of memory data sky mark controller IV, has following 4 kinds of duties:

1) described memory data sky mark controller IV no memory 1 mark empty, memorizer 2 sky exports, show that memorizer 1, memorizer 2 are all data non-NULL, the memorizer of one non-NULL is currently written into instruction or write instruction process terminates, and another memorizer is just at read operation number；If the order computing being carrying out terminates, start and enable signal by " 1 " → " 0 ", transfer a memorizer sky to, the state of another memorizer non-NULL, the enabling signal that now trailing edge of the 1st system clock Clock after order calculating process terminates occurs as time sequential pulse, sends write command to system and allows signal；Start memorizer and read the work of time-sequence control mode III；

2) described memory data sky mark controller IV exports the mark that any one memorizer is empty, can be in two kinds of modes of operation, and one is that the memorizer of non-NULL is currently written into operand, and this memorizer performs read operation simultaneously；Two is that the memorizer write instruction process of non-NULL terminates, is carrying out read operation；If order calculating process terminates, startup enable signal, by " 1 " → " 0 ", transfers memorizer 1 and the state of memorizer 2 all skies to；

3) described memory data sky mark controller IV output storage 1 sky, the mark of memorizer 2 sky simultaneously, stops memorizer and reads the work of time-sequence control mode III, sends write command to system and allows signal；

4) described memory data sky mark controller IV output storage 1 sky, the mark of memorizer 2 sky simultaneously, and command word and multioperand thereof write time-sequence control mode II and again chosen writing commands word, command word and multioperand thereof to write time-sequence control mode II output by system to write presetting pulse and read the enabling signal of inside sequence timer of time-sequence control mode III as floating-point operation number；

Described computing and output control module V, according to operand type, carry out gating control to the 1st operand participating in computing, and it is from operation result or the 1st operand read from operand store I that gating configuration participates in the operand 1 of plus/minus computing；Computing and output control module V determine according to operator and carry out addition or subtraction, intermediate results of operations latches operation result under the result latch signal effect that time-sequence control mode III sends read by memorizer, and judge that operation result is the most abnormal, if there is exception, send irq signal to system, stop memorizer and read the work of time-sequence control mode III；When system needs to read operation result, intermediate calculation results and the final operation result of order execution can be read under the effect of system RD signal.

As it is shown on figure 3, described command word and multioperand thereof write time-sequence control mode II include module's address identification 1, write high address controller 2, write port address counter 3, write port pulsing controller 4, pending command register 5, operator depositor 6, perform command register 7, operator shift register 8, not gate I 9, not gate II 10 or door I 11 or door II 12 or door III 13 or door IV 14 and door I 15 and with door II 16；

A31 to the A27 line of described module's address identification 1 input and system address bus AB connects, CS1 outfan and or input of door II 12 connect, CS2 outfan and or an input of door III 13, the enable input of write port pulsing controller 4, computing be connected with output control module V；

Described module's address identification 1 is internal arranges two address values, and one is write order word address value, and one is write operation number address value；The address value of A31 to the A27 of the system address bus AB of described module's address identification 1 input compares with the address value of setting in module's address identification 1, if with write order word address value is equal, then output CS1 is " 0 ", if equal with write operation number address value, then output CS2 is " 0 "；At any time, CS1 and CS2 only one of which is output as " 0 ", or output is all " 1 "；

The Writing overflow outfan of the described latch signal input and write port address counter 3 writing high address controller 2 is connected, the outfan writing high address input and not gate II 10 connects, the RESET input and the outfan with door I 15 are connected, and outfan and the input of not gate II 10, the write address high position input AB5_1 of operand store I, memory data sky mark controller IV connect；

It is described that write high address controller 2 output is highest addresses value AB5_1 of operand store I；When the memorizer 1 of operand store I and the data of memorizer 2 are all empty, or when systematic reset signal Rst is " 0 ", resetting and write high address controller 2, it is output as " 0 "；When writing the latch signal input of high address controller 2 by " 1 " → " 0 ", write the AB5_1 state upset of high address controller 2 outfan output；

The operand number input of described write port address counter 3 is connected with D4 to the D0 line of system data bus DB, write presetting pulse input and or door II 12 outfan connect, write count pulse input to be connected with pulse 2. _ 1 outfan of write port pulsing controller 4, write the RESET input and systematic reset signal Rst line connects, the write address input AB_1 of write address outfan and operand store I connects, Writing overflow outfan also with the Writing overflow input of write port pulsing controller 4, the input of not gate I 9, memory data sky mark controller IV connects；

The described write port address counter 3 substantially enumerator that subtracts 1, D4 to the D0 transmission of system DB is operand the numerical value participating in plus/minus computing, when the memorizer 1 of operand store I is empty or memorizer 2 is empty, and when meeting the CS2 outfan of module's address identification 1 for " 0 ", operand numerical value is preset to write port address counter 3 as the low 5 bit address initial values of operand store I write port as writing presetting pulse by WR signal, and Writing overflow outfan is set to one state；

Low 5 bit address values AB_1 of write port of described write port address counter 3 output function number memorizer I；When writing count pulse input and carrying out a count pulse, write port address counter 3 carries out once-1 operation, until write address outfan is " 0 ", AB_1 is " 0 ", now Writing overflow signal output part is by " 1 " → " 0 ", Writing overflow signal is as the out-of-work mark of write port address counter 3 so that when writing the latch signal input of high address controller 2 by " 1 " → " 0 ", writes the AB5_1 state upset of high address controller 2 output；Write port address counter 3 under the effect of systematic reset signal Rst, reset write port address counter 3 so that Writing overflow signal output part is " 0 " state；

The clock terminal of described write port pulsing controller 4 is connected with system write signal WR line, starts input and the outfan with door II 16 is connected, and the write signal input WR_1 of pulse 1. _ 1 outfan and operand store I connects；

The enable input of described write port pulsing controller 4 is " 0 ", work is started under the pulse signal effect starting input, send the pulse 1. _ 1 with system WR impulsive synchronization and pulse 2. _ 1, pulse 1. _ 1 writes count pulse as the write signal WR_1 of operand store I, pulse 2. _ 1 as write port address counter 3；When Writing overflow signal output part is by " 1 " → " 0 ", described write port pulsing controller 4 quits work, and the outfan of pulse 1. _ 1 and pulse 2. _ 1 is one state；

D5 to the D0 line of the command input end of described pending command register 5 and system data bus DB connects, latch signal input and or the outfan of door II 12 connect, outfan and being connected with the command input end performing command register 7；

The operator input of described operator depositor 6 and D31 to the D6 line of system data bus DB connect, latch input terminal and or the outfan connection of door II 12, the operator input connection of outfan and operator shift register 8；

The latch signal input of described execution command register 7 is read time-sequence control mode III with memorizer and is connected, and class type output terminal, the several several outfans of read operation are read time-sequence control mode III with memorizer and are connected；

The operand type of described execution command register 7 output is 2 kinds:

Type 0: the 1st operand in the memorizer 1 of write operation number memorizer I or memorizer 2 is as the operand 2 of participation plus/minus computing, and operation result is as operand 1；

Class1: the 1st operand in the memorizer 1 of write operation number memorizer I or memorizer 2 is as the operand 1 of participation plus/minus computing, and the 2nd operand is as operand 2；

The latch signal input of described operator shift register 8, shift pulse input are read time-sequence control mode III with memorizer and are connected, and outfan is connected with output control module V with computing；

Described operator shift register 8 is under the effect of shift pulse, and the operator data in operator shift register 8 move right 1 in order, and its lowest order exports as operator；

The outfan of described not gate I 9 and an or input connection of door I 11；

Another input of described or door I 11 and or the outfan of door IV 14 connect, outfan allows signal to system output writer instruction；

Another two inputs of described or door II 12 respectively and or the outfan of door IV 14, system WR write signal line connect, outfan is also read time-sequence control mode III with memorizer and is connected as writing preset signal；

Another input described or door III 13 is connected with system WR write signal line, outfan and being connected with an input of door II 16；

Described or door IV 14 two inputs outfan empty with the memorizer 1 of memory data sky mark controller IV, the empty outfan of memorizer 2 respectively are connected, and outfan also and is connected with another input of door II 16；

Described outfan all empty with an input of door I 15 and memorizer 1 memorizer 2 of memory data sky mark controller IV is connected, and another input is connected with system Rst reseting signal line.

As it is shown in figure 5, described memorizer read time-sequence control mode III include reading high address controller 17, read port address enumerator 18, read port pulsing controller 19, biconditional gate 20, not gate III 21, not gate IV 22 or door V 23 or door VI 24 and door III 25 and door IV 26 and door V 27 and door VI 28 and with door VII 29；

The latch signal input of described reading high address controller 17 overflows outfan with the reading of read port address enumerator 18 and is connected, the outfan reading high address input and not gate III 21 connects, the RESET input and the outfan with door III 25 are connected, and the reading address high input AB5_2 of outfan and operand store I, the input of not gate III 21 connect；

What described reading high address controller 17 exported is highest addresses value AB5_2 of operand store I read port, when the memorizer 1 of operand store I and the data of memorizer 2 are all empty, or when systematic reset signal Rst is " 0 ", resetting and read high address controller 17, its outfan is " 0 "；When the latch signal input of reading high address controller 17 is by " 1 " → " 0 ", read the AB5_2 signal upset of high address controller 17 output；

The presetting pulse input of reading of described read port address enumerator 18 is connected with pulse 2. _ 2 outfan of read port pulsing controller 19, read count pulse input and the outfan with door VII 29 is connected, the RESET input and the outfan with door V 27 are connected, the several several inputs of read operation are connected with the several several outfans of read operation performing command register 7, read to overflow the outfan reading also with read port pulsing controller 19 and overflow input, the reading of memory data sky mark controller IV is overflowed input and is connected, read address output end to be connected with the reading address input end AB_2 of operand store I；

The described read port address enumerator 18 substantially enumerator that subtracts 1, read presetting pulse and the several number of read operation exported from execution command register 7 is preset to read port address enumerator 18, the address value AB_2 reading address output end output making read port address enumerator 18 is the several number of read operation, and read port address enumerator 18 proceeds by-1 counting from the several number of read operation；When reading count pulse input and carrying out a count pulse, the reading address value-1 of read port address enumerator 18 output, until reading address output end is " 0 ", AB_2 is " 0 ", show that last operand reads, spill over outfan is by " 1 " → " 0 ", and spill over is also the out-of-work mark of read port address enumerator 18；When inputting reset signal and being " 0 ", reset read port address enumerator 18, read port address enumerator 18 stops Counts, and overflowing outfan is " 0 "；

The clock terminal of described read port pulsing controller 19 is connected with clock signal Clock line, start input and be connected with door IV 26, the RESET input and the outfan with door V 27 are connected, and type input is connected with the class type output terminal performing command register 7；Pulse 1. _ 2 outfan is connected with the latch signal input performing command register 7 and operator shift register 8, pulse 3. _ 2 outfan and an input with door VI 28, computing is connected with output control module V, pulse 4. _ 2 outfan and an input with door VII 29, computing is connected with output control module V, pulse 5. _ 2 outfan and being connected with another input of door VI 28, pulse 6. _ 2 outfan and being connected with another input of door VII 29, pulse 7. _ 2 outfan and computing are connected with output control module V, read running status outfan to be connected with the reading running status input of memory data sky mark controller IV, start enable outfan and or an input of door VI 24, the startup of memory data sky mark controller IV enables input and connects；

The pulse of described read port pulsing controller 19 output is Tong Bu with system clock Clock；When memorizer 1 or the memorizer 2 of operand store I are that data are empty, when starting input by " 1 " → " 0 ", start read port pulsing controller 19 and start working；When the memorizer 1 of operand store I and memorizer 2 are all data sky, under the effect writing presetting pulse, start outfan by " 1 " → " 0 ", start read port pulsing controller 19 and start working；The reading running status outfan putting read port pulsing controller 19 while startup is one state for " 0 " and startup enable outfan；When reading running status and being " 1 ", show that the calculating process executed of the current command terminates；When starting enable signal and being " 0 ", show not order in execution, and exectorial operation result latches；

Described read port pulsing controller 19 is " 0 " or for " 1 " according to type input signal, determines the pulse train reading to control operation；When the spill over of read port address enumerator 18 output is produced trailing edge by " 1 " → " 0 ", read port pulsing controller 19 is again through an execution cycle time, read running status outfan by " 0 " → " 1 ", and send a system clock Clock cycle and deposit the pulse 7. _ 2 of final operation result, start and enable outfan by " 1 " → " 0 ", stopping the work of read port pulsing controller 19, putting all pulse output ends is one state；When the reset signal of input is " 0 ", reset read port pulsing controller 19, resets and makes to read running status outfan to be one state, and starting enable outfan is " 0 ", putting all pulse output ends is one state, and stops the work of read port pulsing controller 19；

Two inputs of described biconditional gate 20 outfan empty with the memorizer 1 of memory data sky mark controller IV, the empty outfan of memorizer 2 respectively are connected, outfan and or another input connection of door VI 24；

The input of described not gate IV 22 and or the outfan of door II 12 write preset signal and connect, outfan and or an input of door V 23 connect；

The all empty outfan of memorizer 1 memorizer 2 of described or another input of door V 23 and memory data sky mark controller IV connects, outfan and being connected with an input of door IV 26；

Described or the outfan of door VI 24 and being connected with another input of door IV 26；

Described outfan all empty with an input of door III 25 and memorizer 1 memorizer 2 of memory data sky mark controller IV is connected, and another input and systematic reset signal Rst line connect；

A described input with door V 27 is connected with systematic reset signal Rst line, and another input and computing are connected with output control module V；

Described it is connected with reading address input end RD_2, the shift pulse input of operator shift register 8 of operand store I with the outfan of door VI 28.

As shown in Figure 6, described computing and output control module V include that gate 30, result register 31, floating number plus/minus 32a arithmetical unit, computing abnormality mark control 33,32 triple gate groups 34 or door VII 35 or door VIII 36 and or door Ⅸ 37；

Two inputs of described gate 30 are connected with reading data output end DB_2, the operation result outfan of floating number plus/minus 32a arithmetical unit of operand store I respectively, gating control input and or door VII 35 outfan connect, outfan is connected with the input of result register 31；

Described gate 30 completes to perform the option and installment of the operand 1 of the 1st computing of order according to operand type, when operand type is " 1 ", read port pulsing controller 19 sends and reads the pulse 3. _ 2 of first operand from operand store I and write count pulse 4. _ 2；When pulse 3. _ 2 or pulse 4. _ 2 are " 0 ", described gate 30 exports the 1st operand read from operand store (I)；When pulse 3. _ 2 and pulse 4. _ 2 are all " 1 ", gate output operation result；

The latch pulse input of described result register 31 and or the outfan connection of door VIII 36, outfan and operand 1 input of floating number plus/minus 32a arithmetical unit, 32 triple gate group 34 inputs connections；

Operand 2 input of described floating number plus/minus 32a arithmetical unit and the data output end DB_2 of operand store I connect, the operator outfan of operator input and operator shift register 8 connects, and the input that operation result outfan also controls 33 with computing abnormality mark is connected；

Described floating number plus/minus 32a arithmetical unit carries out addition or subtraction according to operator, when operator input is " 0 ", controls floating number plus/minus 32a arithmetical unit and carries out additive operation, when operator input is " 1 ", carry out subtraction；

Described computing abnormality mark controls the latch pulse input of 33 and is connected with pulse 7. _ 2 outfan of read port pulsing controller 19, outfan and being connected with an input of door V 27, and to system output interrupt request singal IRQ；

The operation result of described floating number plus/minus 32a arithmetical unit is latched in result register 31, and computing abnormality mark controls in 33 modules；When intermediate calculation results or final operation result occur abnormal, computing abnormality mark controls 33 and sends interrupt request singal IRQ to system, and reset read port address enumerator 18 and read port pulsing controller 19, stop read port address enumerator 18 and the work of read port pulsing controller 19；

The outfan of described 32 triple gate groups 34 is connected with system data bus DB, controls end and or the outfan connection of door Ⅸ 37；

Described or door VII 35 two inputs are connected with pulse 3. _ 2, pulse 4. _ 2 outfan of read port pulsing controller 19 respectively；

Described or door VIII 36 two inputs are connected with pulse 4. _ 2, pulse 7. _ 2 outfan of read port pulsing controller 19 respectively；

Described or door Ⅸ 37 two inputs are connected with CS2 outfan, the system read signal RD line of module's address identification 1 respectively, when CS2 is " 0 ", under the effect of system RD signal, read intermediate calculation results and the final operation result of order execution.

Embodiment two:

Double instructions many floating-point operations scale multiplication controller (seeing Figure 13, Figure 14)；

Embodiment two is a kind of mapped structure of the embodiment of the present invention one, and the basic structure of this pair of instruction many floating-point operations scale multiplication controller is with embodiment one；Institute's difference is: cancelling the operator depositor 6 of embodiment one Fig. 3, operator shift register 8, the command word and the multioperand thereof that are transformed to Figure 13 write time-sequence control mode；Floating number plus/minus 32a arithmetical unit of embodiment one Fig. 6 is transformed to the floating number multiplication device 32b of Figure 14, and cancels the operator input signal end in embodiment one Fig. 6；In the readout sequence figure of Figure 12, it is transformed to the clock cycle required for the floating number multiplication time by completing a floating number plus/minus computing clock cycle.

Claims (4)

1. double instruction many floating-point operations number plus/minus arithmetic and control unit, it is characterised in that: this controller includes that operand store (I), command word and multioperand thereof write time-sequence control mode (II), memorizer reads time-sequence control mode (III), memory data sky mark controller (IV), computing and output control module (V)；

Time-sequence control mode (II) write by described operand store (I) with command word and multioperand thereof, time-sequence control mode (III) read by memorizer, computing is connected with output control module (V)；

Described command word and multioperand thereof are write time-sequence control mode (II) and are also connected with output control module (V) with memorizer reading time-sequence control mode (III), memory data sky mark controller (IV), computing；

Described memorizer is read time-sequence control mode (III) and is also connected with output control module (V) with memory data sky mark controller (IV), computing；

Described operand store (I) is dual-ported memory, write port, read port, is used for storing floating-point operation number (lower referred to as operand)；Described operand store (I) is divided into memorizer 1 and 2 two memory areas of memorizer；The write address high position input AB5_1 of described operand store (I) is " 0 ", or reading address high input AB5_2 is " 0 ", chooses 26 low address memory element of operand store (I), i.e. memorizer 1；Write address high position input AB5_1 is " 1 ", or reading address high input AB5_2 is " 1 ", chooses 26 high address memory element of operand store (I), i.e. memorizer 2；

Described command word and multioperand thereof are write time-sequence control mode (II) and have been controlled write and the storage of instruction, need to take system bus；Article one, instruction includes 32 order of the bit words and several operands, and operand is up to 26；It is empty for data at memorizer 1 or the memorizer 2 of operand store (I) that described command word and multioperand thereof write time-sequence control mode (II), and output write command allows signal, side to allow to be chosen by system；When being chosen write order word by system, under the effect of system WR signal, write plus/minus algorithm word；When being chosen write operation number by system, command word and multioperand thereof are write internal generation of time-sequence control mode (II) and Tong Bu with system WR signal are write time sequential pulse；Under the control writing time sequential pulse, operand is stored in memorizer 1 or the memorizer 2 of operand store (I)；Article one, after last operand of instruction is written into storage, that changes operand store (I) writes high address input AB5_1 state, if the memorizer 1 of operand store (I) and memorizer 2 all non-NULLs, cease and desist order word and multioperand writes the work of time-sequence control mode (II)；

Described memorizer reading time-sequence control mode (III), under the control of time sequential pulse is read in inside, independently completes many floating-point operations number and reads from operand store (I), it is not necessary to take system bus；Described memorizer is read time-sequence control mode (III) and is produced the reading time sequential pulse sequence Tong Bu with system clock Clock signal, operand reads participation in order and adds deduct computing；After last operand participating in computing reads, produce and read address spill over, the most again through an execution cycle added deduct, send and read the signal that running status terminates, produce the result latch pulse of a clock cycle Clock, send startup the most again and enable signal；

The time-sequence control mode (III) the empty flag states read operation according to memory data sky mark controller (IV) read by described memorizer, has following 4 kinds of duties:

1) described memory data sky mark controller (IV) no memory 1 mark empty, memorizer 2 sky exports, show that memorizer 1, memorizer 2 are all data non-NULL, the memorizer of one non-NULL is currently written into instruction or write instruction process terminates, and another memorizer is just at read operation number；If the order computing being carrying out terminates, start and enable signal by " 1 " → " 0 ", transfer a memorizer sky to, the state of another memorizer non-NULL, the enabling signal that now trailing edge of the 1st system clock Clock after order calculating process terminates occurs as time sequential pulse, sends write command to system and allows signal；Start memorizer and read the work of time-sequence control mode (III)；

2) described memory data sky mark controller (IV) exports the mark that any one memorizer is empty, can be in two kinds of modes of operation, and one is that the memorizer of non-NULL is currently written into operand, and this memorizer performs read operation simultaneously；Two is that the memorizer write instruction process of non-NULL terminates, is carrying out read operation；If order calculating process terminates, startup enable signal, by " 1 " → " 0 ", transfers memorizer 1 and the state of memorizer 2 all skies to；

3) described memory data sky mark controller (IV) output storage 1 simultaneously sky, the mark of memorizer 2 sky, stops memorizer and reads the work of time-sequence control mode (III), sends write command to system and allows signal；

4) described memory data sky mark controller (IV) output storage 1 simultaneously sky, the mark of memorizer 2 sky, and command word and multioperand thereof write time-sequence control mode (II) and again chosen writing commands word, command word and multioperand thereof to write time-sequence control mode (II) output by system to write presetting pulse and read the enabling signal of inside sequence timer of time-sequence control mode (III) as floating-point operation number；

Described computing and output control module (V) are according to operand type, the 1st operand participating in computing carries out gating control, and it is from operation result or the 1st operand read from operand store (I) that gating configuration participates in the operand 1 of plus/minus computing；Computing and output control module (V) determine according to operator and carry out addition or subtraction, intermediate results of operations latches operation result under the result latch signal effect that time-sequence control mode (III) sends read by memorizer, and judge that operation result is the most abnormal, if there is exception, send irq signal to system, stop memorizer and read the work of time-sequence control mode (III)；When system needs to read operation result, intermediate calculation results and the final operation result of order execution can be read under the effect of system RD signal.

2. double instruction many floating-point operations number plus/minus arithmetic and control unit as claimed in claim 1, it is characterized in that: described command word and multioperand thereof are write time-sequence control mode (II) and included module's address identification (1), write high address controller (2), write port address counter (3), write port pulsing controller (4), pending command register (5), operator depositor (6), perform command register (7), operator shift register (8), not gate I (9), not gate II (10), or door I (11), or door II (12), or door III (13), or door IV (14), with door I (15) and with door II (16)；

A31 to the A27 line of described module's address identification (1) input and system address bus AB connects, CS1 outfan and or input of door II (12) connect, CS2 outfan and or an input of door III (13), the enable input of write port pulsing controller (4), computing be connected with output control module (V)；

Described module's address identification (1) is internal arranges two address values, and one is write order word address value, and one is write operation number address value；The address value of A31 to the A27 of the system address bus AB that described module's address identification (1) inputs compares with the address value of setting in module's address identification (1), if with write order word address value is equal, then output CS1 is " 0 ", if with write operation number address value is equal, then output CS2 is " 0 "；At any time, CS1 and CS2 only one of which is output as " 0 ", or output is all " 1 "；

The Writing overflow outfan of the described latch signal input and write port address counter (3) writing high address controller (2) is connected, the outfan writing high address input and not gate II (10) connects, the RESET input and the outfan with door I (15) are connected, and outfan and the input of not gate II (10), the write address high position input AB5_1 of operand store (I), memory data sky mark controller (IV) connect；

It is described that write that high address controller (2) exports is highest addresses value AB5_1 of operand store (I)；When the memorizer 1 of operand store (I) and the data of memorizer 2 are all empty, or when systematic reset signal Rst is " 0 ", resetting and write high address controller (2), it is output as " 0 "；When writing the latch signal input of high address controller (2) by " 1 " → " 0 ", write the AB5_1 state upset of high address controller (2) outfan output；

The operand number input of described write port address counter (3) is connected with D4 to the D0 line of system data bus DB, write presetting pulse input and or door II (12) outfan connect, write count pulse input to be connected with pulse 2. _ 1 outfan of write port pulsing controller (4), write the RESET input and systematic reset signal Rst line connects, the write address input AB_1 of write address outfan and operand store (I) connects, Writing overflow outfan also with the Writing overflow input of write port pulsing controller (4), the input of not gate I (9), memory data sky mark controller (IV) connects；

Described write port address counter (3) the substantially enumerator that subtracts 1, D4 to the D0 transmission of system DB is operand the numerical value participating in plus/minus computing, when the memorizer 1 of operand store (I) is empty or memorizer 2 is empty, and when meeting the CS2 outfan of module's address identification (1) for " 0 ", operand numerical value is preset to write port address counter (3) as the low 5 bit address initial values of operand store (I) write port as writing presetting pulse by WR signal, and Writing overflow outfan is set to one state；

Low 5 bit address values AB_1 of write port of described write port address counter (3) output function number memorizer (I)；When writing count pulse input and carrying out a count pulse, write port address counter (3) carries out once-1 operation, until write address outfan is " 0 ", AB_1 is " 0 ", now Writing overflow signal output part is by " 1 " → " 0 ", Writing overflow signal is as write port address counter (3) out-of-work mark so that when writing the latch signal input of high address controller (2) by " 1 " → " 0 ", writes the AB5_1 state upset that high address controller (2) exports；Write port address counter (3) under the effect of systematic reset signal Rst, reset write port address counter (3) so that Writing overflow signal output part is " 0 " state；

The clock terminal of described write port pulsing controller (4) is connected with system write signal WR line, starts input and the outfan with door II (16) is connected, and the write signal input WR_1 of pulse 1. _ 1 outfan and operand store (I) connects；

The enable input of described write port pulsing controller (4) is " 0 ", work is started under the pulse signal effect starting input, send the pulse 1. _ 1 with system WR impulsive synchronization and pulse 2. _ 1, pulse 1. _ 1 writes count pulse as the write signal WR_1 of operand store (I), pulse 2. _ 1 as write port address counter (3)；When Writing overflow signal output part is by " 1 " → " 0 ", described write port pulsing controller (4) quits work, and the outfan of pulse 1. _ 1 and pulse 2. _ 1 is one state；

D5 to the D0 line of the command input end of described pending command register (5) and system data bus DB connects, latch signal input and or the outfan of door II (12) connect, outfan is connected with the command input end of execution command register (7)；

The operator input of described operator depositor (6) and D31 to the D6 line of system data bus DB connect, latch input terminal and or the outfan connection of door II (12), the operator input connection of outfan and operator shift register (8)；

The latch signal input of described execution command register (7) is read time-sequence control mode (III) with memorizer and is connected, and class type output terminal, the several several outfans of read operation are read time-sequence control mode (III) with memorizer and are connected；

The operand type that described execution command register (7) exports is 2 kinds:

Type 0: the 1st operand in the memorizer 1 of write operation number memorizer (I) or memorizer 2 is as the operand 2 of participation plus/minus computing, and operation result is as operand 1；

Class1: the 1st operand in the memorizer 1 of write operation number memorizer (I) or memorizer 2 is as the operand 1 of participation plus/minus computing, and the 2nd operand is as operand 2；

The latch signal input of described operator shift register (8), shift pulse input are read time-sequence control mode (III) with memorizer and are connected, and outfan is connected with output control module (V) with computing；

Described operator shift register (8) is under the effect of shift pulse, and the operator data in operator shift register (8) move right 1 in order, and its lowest order exports as operator；

The outfan of described not gate I (9) and an or input connection of door I (11)；

Another input of described or door I (11) and or the outfan of door IV (14) connect, outfan allows signal to system output writer instruction；

Another two inputs of described or door II (12) respectively and or the outfan of door IV (14), system WR write signal line connect, outfan is also read time-sequence control mode (III) with memorizer and is connected as writing preset signal；

Another input described or door III (13) is connected with system WR write signal line, outfan and being connected with an input of door II (16)；

Described or door IV (14) two inputs outfan empty with the memorizer 1 of memory data sky mark controller (IV), the empty outfan of memorizer 2 respectively are connected, and outfan also and is connected with another input of door II (16)；

Described outfan all empty with an input of door I (15) and memorizer 1 memorizer 2 of memory data sky mark controller (IV) is connected, and another input is connected with system Rst reseting signal line.

3. instruction many floating-point operations number plus/minus arithmetic and control units as claimed in claim 1 double, it is characterised in that: described memorizer read time-sequence control mode (III) include reading high address controller (17), read port address enumerator (18), read port pulsing controller (19), biconditional gate (20), not gate III (21), not gate IV (22) or door V (23) or door VI (24) and door III (25) and door IV (26) and door V (27) and door VI (28) and with door VII (29)；

The latch signal input of described reading high address controller (17) overflows outfan with the reading of read port address enumerator (18) and is connected, the outfan reading high address input and not gate III (21) connects, the RESET input and the outfan with door III (25) are connected, and the reading address high input AB5_2 of outfan and operand store (I), the input of not gate III (21) connect；

What described reading high address controller (17) exported is highest addresses value AB5_2 of operand store (I) read port, when the memorizer 1 of operand store (I) and the data of memorizer 2 are all empty, or when systematic reset signal Rst is " 0 ", resetting and read high address controller (17), its outfan is " 0 "；When the latch signal input of reading high address controller (17) is by " 1 " → " 0 ", read the AB5_2 signal upset that high address controller (17) exports；

The reading presetting pulse input of described read port address enumerator (18) is connected with pulse 2. _ 2 outfan of read port pulsing controller (19), read count pulse input and the outfan with door VII (29) is connected, the RESET input and the outfan with door V (27) are connected, the several several inputs of read operation are connected with the several several outfans of read operation performing command register (7), read to overflow the outfan reading also with read port pulsing controller (19) and overflow input, the reading of memory data sky mark controller (IV) is overflowed input and is connected, read address output end to be connected with the reading address input end AB_2 of operand store (I)；

Described read port address enumerator (18) the substantially enumerator that subtracts 1, read presetting pulse and the several number of read operation exported from execution command register (7) is preset to read port address enumerator (18), the address value AB_2 reading address output end output making read port address enumerator (18) is the several number of read operation, and read port address enumerator (18) proceeds by-1 counting from the several number of read operation；When reading count pulse input and carrying out a count pulse, the reading address value-1 that read port address enumerator (18) exports, until reading address output end is " 0 ", AB_2 is " 0 ", show that last operand reads, spill over outfan is by " 1 " → " 0 ", and spill over is also read port address enumerator (18) out-of-work mark；When inputting reset signal and being " 0 ", reset read port address enumerator (18), read port address enumerator (18) stops Counts, and overflowing outfan is " 0 "；

The clock terminal of described read port pulsing controller (19) is connected with clock signal Clock line, start input and be connected with door IV (26), the RESET input and the outfan with door V (27) are connected, and type input is connected with the class type output terminal performing command register (7)；nullPulse 1. _ 2 outfan is connected with the latch signal input performing command register (7) and operator shift register (8)，Pulse 3. _ 2 outfan and an input with door VI (28)、Computing is connected with output control module (V)，Pulse 4. _ 2 outfan and an input with door VII (29)、Computing is connected with output control module (V)，Pulse 5. _ 2 outfan and another input with door VI (28) are connected，Pulse 6. _ 2 outfan and another input with door VII (29) are connected，Pulse 7. _ 2 outfan and computing are connected with output control module (V)，Read running status outfan to be connected with the reading running status input of memory data sky mark controller (IV)，Start and enable outfan and an or input of door VI (24)、The startup of memory data sky mark controller (IV) enables input and connects；

The pulse that described read port pulsing controller (19) exports is Tong Bu with system clock Clock；When memorizer 1 or the memorizer 2 of operand store (I) are that data are empty, when starting input by " 1 " → " 0 ", start read port pulsing controller (19) and start working；When the memorizer 1 of operand store (I) and memorizer 2 are all data sky, under the effect writing presetting pulse, start outfan by " 1 " → " 0 ", start read port pulsing controller (19) and start working；The reading running status outfan putting read port pulsing controller (19) while startup is one state for " 0 " and startup enable outfan；When reading running status and being " 1 ", show that the calculating process executed of the current command terminates；When starting enable signal and being " 0 ", show not order in execution, and exectorial operation result latches；

Described read port pulsing controller (19) is " 0 " or for " 1 " according to type input signal, determines the pulse train reading to control operation；When the spill over that read port address enumerator (18) exports is produced trailing edge by " 1 " → " 0 ", read port pulsing controller (19) is again through an execution cycle time, read running status outfan by " 0 " → " 1 ", and send a system clock Clock cycle and deposit the pulse 7. _ 2 of final operation result, start and enable outfan by " 1 " → " 0 ", stopping the work of read port pulsing controller (19), putting all pulse output ends is one state；When the reset signal of input is " 0 ", reset read port pulsing controller (19), it is one state that reset makes to read running status outfan, starting enable outfan is " 0 ", putting all pulse output ends is one state, and stops the work of read port pulsing controller (19)；

Two inputs of described biconditional gate (20) outfan empty with the memorizer 1 of memory data sky mark controller (IV), the empty outfan of memorizer 2 respectively are connected, outfan and or another input connection of door VI (24)；

The input of described not gate IV (22) and or the outfan of door II (12) write preset signal and connect, outfan and or an input of door V (23) connect；

The all empty outfan of memorizer 1 memorizer 2 of described or another input of door V (23) and memory data sky mark controller (IV) connects, outfan and being connected with an input of door IV (26)；

Described or the outfan of door VI (24) and another input with door IV (26) are connected；

Described outfan all empty with an input of door III (25) and memorizer 1 memorizer 2 of memory data sky mark controller (IV) is connected, and another input and systematic reset signal Rst line connect；

A described input with door V (27) is connected with systematic reset signal Rst line, and another input and computing are connected with output control module (V)；

Described it is connected with reading address input end RD_2, the shift pulse input of operator shift register (8) of operand store (I) with the outfan of door VI (28).

4. double instruction many floating-point operations number plus/minus arithmetic and control unit as claimed in claim 1, it is characterised in that: described computing and output control module (V) include that gate (30), result register (31), floating number plus/minus arithmetical unit (32a), computing abnormality mark control (33), 32 triple gate groups (34) or door VII (35) or door VIII (36) and or door Ⅸ (37)；

Two inputs of described gate (30) are connected with reading data output end DB_2, the operation result outfan of floating number plus/minus arithmetical unit (32a) of operand store (I) respectively, gating control input and or door VII (35) outfan connect, outfan is connected with the input of result register (31)；

Described gate (30) completes to perform the option and installment of the operand 1 of the 1st computing of order according to operand type, when operand type is " 1 ", read port pulsing controller (19) sends and reads the pulse 3. _ 2 of first operand from operand store (I) and write count pulse 4. _ 2；When pulse 3. _ 2 or pulse 4. _ 2 are " 0 ", described gate (30) exports the 1st operand read from operand store (I)；When pulse 3. _ 2 and pulse 4. _ 2 are all " 1 ", gate (30) output operation result；

The latch pulse input of described result register (31) and or the outfan connection of door VIII (36), operand 1 input of outfan and floating number plus/minus arithmetical unit (32a), 32 triple gate group (34) inputs connections；

Operand 2 input of described floating number plus/minus arithmetical unit (32a) and the data output end DB_2 of operand store (I) connect, the operator outfan of operator input and operator shift register (8) connects, and the input that operation result outfan also controls (33) with computing abnormality mark is connected；

Described floating number plus/minus arithmetical unit (32a) carries out addition or subtraction according to operator, when operator input is " 0 ", controls floating number plus/minus arithmetical unit (32a) and carries out additive operation, when operator input is " 1 ", carry out subtraction；

Described computing abnormality mark controls the latch pulse input of (33) and is connected with pulse 7. _ 2 outfan of read port pulsing controller (19), outfan and being connected with an input of door V (27), and to system output interrupt request singal IRQ；

The operation result of described floating number plus/minus arithmetical unit (32a) is latched in result register (31), and computing abnormality mark controls in (33) module；When intermediate calculation results or final operation result occur abnormal, computing abnormality mark controls (33) and sends interrupt request singal IRQ to system, and reset read port address enumerator (18) and read port pulsing controller (19), stop read port address enumerator (18) and the work of read port pulsing controller (19)；

The outfan of described 32 triple gate groups (34) is connected with system data bus DB, controls end and or the outfan connection of door Ⅸ (37)；

Described or door VII (35) two inputs are connected with pulse 3. _ 2, pulse 4. _ 2 outfan of read port pulsing controller (19) respectively；

Described or door VIII (36) two inputs are connected with pulse 4. _ 2, pulse 7. _ 2 outfan of read port pulsing controller (19) respectively；

Described or door Ⅸ (37) two inputs are connected with CS2 outfan, the system read signal RD line of module's address identification (1) respectively, when CS2 is " 0 ", under the effect of system RD signal, read intermediate calculation results and the final operation result of order execution.