CN103633119B - Epitaxial wafer, production method thereof and super junction power device - Google Patents
Epitaxial wafer, production method thereof and super junction power device Download PDFInfo
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- CN103633119B CN103633119B CN201210311175.5A CN201210311175A CN103633119B CN 103633119 B CN103633119 B CN 103633119B CN 201210311175 A CN201210311175 A CN 201210311175A CN 103633119 B CN103633119 B CN 103633119B
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- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 238000009826 distribution Methods 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 25
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 9
- 229910052739 hydrogen Inorganic materials 0.000 claims description 9
- 239000001257 hydrogen Substances 0.000 claims description 9
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical group Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 claims description 6
- 239000005052 trichlorosilane Substances 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052787 antimony Inorganic materials 0.000 claims description 4
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- -1 silicon Alkane Chemical class 0.000 claims description 3
- 238000003780 insertion Methods 0.000 claims description 2
- 230000037431 insertion Effects 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 claims 19
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 description 17
- 239000004744 fabric Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 4
- 230000007812 deficiency Effects 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H01L21/2053—
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
The invention discloses an epitaxial wafer comprising a substrate and a first epitaxial layer; the epitaxial wafer is characterized in that the first epitaxial layer resistivity is distributed in a concentric circles shape. The resistivity of the epitaxial wafer is distributed in a concentric circles shape. A groove is etched and filled with epitaxial material, charge distribution is uniform, so electric property failure problem cannot happen. The epitaxial wafer can be used to improve collapse voltage of a super junction power device, and the collapse voltage can be improved by more than 50 volts. The collapse voltage of a super junction power device produced by an epitaxial wafer with non-concentric circles distribution is 580 volts; the collapse voltage of the super junction power device produced by the epitaxial wafer of the invention can increase to 630 volts.
Description
Technical field
The present invention relates to a kind of epitaxial wafer, its production method and super junction power device.
Background technology
Super junction power device possesses breakdown voltage higher with relatively low conducting resistance compared with traditional power device.
For super junction power device, under the logical Electricity resistances of identical Guide, the higher the better for breakdown voltage.As shown in figure 1, one of which is super
The epitaxial slice structure schematic diagram that knot power device is used, it includes substrate 1, the first epitaxial layer 2 with N-type on substrate 1.N
First epitaxial layer 2 of type is provided with groove（Not shown in figure）, the second epitaxial layer 4 is covered in the surface of the first epitaxial layer 2, the second extension
Layer 4 is embedded in the groove of the first epitaxial layer 2.One of main challenge of super junction power device is being uniformly distributed for electric charge.Superjunction
Need to etch groove in the first epitaxial layer 2 in the technique of power device, and the second epitaxial layer is embedded in the groove for being etched
4.And first epitaxial layer 2 it is different from the material of the second epitaxial layer 4.First epitaxial layer 2 is N-type, then the second epitaxial layer 4 is p-type；First
Epitaxial layer 2 is p-type, then the second epitaxial layer 4 is N-type.But because the groove etched on the first epitaxial layer 2 has middle narrow, edge
Distribution wide, the i.e. groove near the center of circle are narrow, near the ditch groove width at edge.So if using resistivity from epitaxial wafer edge edge
Radially-arranged first epitaxial layer, can cause the outer electrical property failure that makes a circle, and cause super junction power device breakdown voltage relatively low, it is impossible to
Reach use requirement.
The content of the invention
An object of the present invention is to overcome deficiency of the prior art, there is provided one kind is suitable for superjunction power device
The epitaxial wafer of part.
To realize object above, the present invention is achieved through the following technical solutions：
Epitaxial wafer, including substrate and the first epitaxial layer, it is characterised in that the first described epilayer resistance rate is in concentric circles
Shape is distributed.
Preferably, the resistivity heterogeneity at the first epitaxial layer same radius is no more than 5%.
Preferably, resistivity heterogeneity of first epitaxial layer from the center of circle radially in every 30 mm in width endless belt be not
More than 5%.
Preferably, the first epitaxial layer is radially uniform from the center of circle is divided into three regions, and three region radial widths are identical,
Resistivity heterogeneity in each region is no more than 5%.
Preferably, it is provided with monocrystalline silicon layer between the substrate and the first epitaxial layer.
Preferably, described monocrystalline silicon layer thickness is 2~5 μm.
Preferably, described monocrystalline silicon layer is that trichlorosilane reacts generation with hydrogen at 1040 DEG C~1100 DEG C.
Preferably, described substrate is N-type.
Preferably, at least one element during described N-type substrate is doped with arsenic, phosphorus and antimony.
Preferably, the first described epitaxial layer is N-type.
Preferably, at least one element during the first described epitaxial layer is doped with arsenic, phosphorus and antimony.
Preferably, described substrate is p-type.
Preferably, described P type substrate is doped with boron.
Preferably, the first described epitaxial layer is p-type.
Preferably, the first described epitaxial layer is doped with boron.
Preferably, the first described epilayer resistance rate is radially enlarged from the center of circle or reduces or alternately increase reduction
Or alternately reduce increase.
Preferably, the substrate back has an oxide layer, and the oxide layer edge radius 1-2 smaller than substrate radius is in the least
Rice.
The second object of the present invention is to overcome deficiency of the prior art, there is provided one kind is suitable for superjunction power device
The production method of the epitaxial wafer of part.
To realize object above, the present invention is achieved through the following technical solutions：
The production method of foregoing epitaxial wafer, it is characterised in that including step：
One substrate is provided；Substrate back is aoxidized to form an oxide layer；By 1-2 millimeters of the oxide layer edge etch；
Depositing monocrystalline silicon layer over the substrate；
The first epitaxial layer is deposited in the monocrystalline surface.
Preferably, described monocrystalline silicon layer is that trichlorosilane reacts generation with hydrogen at 1040 DEG C~1100 DEG C.
The third object of the present invention is to overcome deficiency of the prior art, there is provided a kind of breakdown voltage superjunction work(high
Rate device.
To realize object above, the present invention is achieved through the following technical solutions：
Super junction power device, it is characterised in that including foregoing epitaxial wafer.
Preferably, including described epitaxial wafer, the epitaxial layer of the epitaxial wafer is provided around the groove in the center of circle；The ditch
It is filled with groove and is covered in first epitaxial layer and the insertion groove with the second epitaxial layer, second epitaxial layer；It is described
First epitaxial layer is different from the second epitaxial film materials.
Preferably, the substrate is N-type, and the first epitaxial layer is N-type；Second epitaxial layer is p-type；Or the lining
Bottom is p-type, and the first epitaxial layer is p-type；Second epitaxial layer is N-type.
Epilayer resistance rate in the present invention refers to that the epitaxial layer at the same distance of the center of circle is electric in concentric circles distribution
Resistance rate is identical or difference of maxima and minima is a selected scope.Epilayer resistance rate in the present invention is in concentric circles
Distribution, can also be that the difference between the resistivity maxima and minima in the endless belt of every 30 mm wide from the center of circle is
Selected scope.From the center of circle to epitaxial wafer edge radially, resistivity both can gradually increase；Can also be gradually reduced；Also
First can gradually increase and be gradually reduced again；Or be first gradually reduced and gradually increase again；In addition, resistivity gradually increases and gradually subtracts
Small being alternately distributed can also.
Heterogeneity=(maximum-minimum value) × 100%/(maximum+minimum value) in the present invention.
Epitaxial wafer in the present invention, the first epilayer resistance rate is distributed in concentric circles.In trench etch and fill extension
After material, distribution of charges is uniform, will not produce the problem of electrical property failure.Using the epitaxial wafer in the present invention, superjunction can be improved
The breakdown voltage of power device.Using the epitaxial wafer in the present invention, the breakdown voltage of super junction power device can be improved 50 volts
More than.The breakdown voltage of the super junction power device that the epitaxial wafer for using non-concentric round shape to be distributed is produced is 580 volts；Using this hair
The super junction power device breakdown voltage of the epitaxial wafer production in bright rises to 630 volts.Needing collapsing for super junction power device
Routed voltage is 600 volts of field, and the super junction power device produced using existing epitaxial wafer is unable to reach use requirement, using this
Epitaxial wafer production super junction power device in invention can meet use requirement.
Brief description of the drawings
Fig. 1 is the epitaxial slice structure schematic diagram that a kind of super junction power device is used.
Fig. 2 is a kind of resistivity distribution schematic diagram of epitaxial wafer.
Fig. 3 is the super junction power device testing electrical property figure produced using the epitaxial wafer shown in Fig. 2.
Fig. 4 is the epitaxial slice structure schematic cross-sectional view in the present invention.
Fig. 5 is the electrical resistivity distribution map in embodiment 1.
Fig. 6 is view when epitaxial wafer in the present invention is used to produce super junction power device.
View when Fig. 7 is the epitaxial wafer production super junction power device in the present invention.
Fig. 8 is the super junction power device testing electrical property figure produced using the epitaxial wafer in embodiment 1.
Fig. 9 is the electrical resistivity distribution map in embodiment 2.
Figure 10 is the super junction power device testing electrical property figure produced using the epitaxial wafer in embodiment 2.
Figure 11 is the electrical resistivity distribution map in embodiment 3.
Figure 12 is the super junction power device testing electrical property figure produced using the epitaxial wafer in embodiment 3.
Figure 13 is the electrical resistivity distribution map in embodiment 4.
Figure 14 is the super junction power device testing electrical property figure produced using the epitaxial wafer in embodiment 4.
Figure 15 is the electrical resistivity distribution map in embodiment 5.
Figure 16 is the super junction power device testing electrical property figure produced using the epitaxial wafer in embodiment 5.
Figure 17 is the electrical resistivity distribution map in embodiment 6.
Figure 18 is the super junction power device testing electrical property figure produced using the epitaxial wafer in embodiment 6.
Specific embodiment
Fig. 2 is a kind of electrical resistivity distribution schematic diagram.Inventor pass through experimental studies have found that, when using have Fig. 2
Shown characteristic epitaxial wafer production super junction power device when, due to its resistivity from epitaxial wafer edge genesis analysis, circumferentially
There is difference in the resistivity in direction.When groove is along the circumferential direction opened up, the resistivity at the different position of groove is different.And
The resistivity of filling epitaxial material along the circumferential direction all same in described groove.In a circumferential direction, so may result in groove
There is difference with the difference of the epilayer resistance rate of epitaxial wafer in interior filling epitaxial material resistivity.Therefore, using this epitaxial wafer
The super junction power device distribution of charges of production is uneven, haves the shortcomings that electrical property failure.Fig. 3 show the epitaxial wafer shown in Fig. 2
Electrical analysis figure.Black round dot in figure represents electrical property failure position.Due to its resistivity skewness, cause to be made a circle outside it
Electrical property failure position is very more.Have a strong impact on the super junction power device performance of manufacture.
The present invention is described in detail with reference to embodiment and accompanying drawing：
Embodiment 1
Epitaxial wafer, it is shaped as circle.Through-thickness cutting, its sectional view are as shown in figure 4, including N-type substrate 1 and N
The first epitaxial layer of type 2.Monocrystalline silicon layer 5 is provided between N-type substrate 1 and the first epitaxial layer of N-type 2.
Its production stage includes：As shown in Figure 4, there is provided a N-type substrate 1；The backside oxide of N-type substrate 1 is formed into one to aoxidize
Layer 7；It it is 2 millimeters by the edge etch width L of the oxide layer 7.The depositing monocrystalline silicon layer 5 in the N-type substrate 1；N-type substrate 1
Monocrystalline silicon layer 5 is provided between N-type epitaxy layer 2.The thickness of monocrystalline silicon layer 5 is 4 μm.Monocrystalline silicon layer 5 is trichlorosilane and hydrogen
Reaction is generated and is deposited on the surface of substrate 1 at 1040 DEG C.The first epitaxial layer 2 is deposited on the surface of the monocrystalline silicon layer 5.Produce
Epitaxial wafer shown in Fig. 5.
It is illustrated in figure 5 the epilayer resistance rate distribution map of the epitaxial wafer of the present embodiment production.As can be seen from Figure 5, first
The resistivity of epitaxial layer is distributed in concentric circles.From the center of circle, the resistivity heterogeneity of first 30mm endless belt is
1.0%.Second resistivity heterogeneity of 30mm endless belts is 1.1%.The resistivity of the 3rd 30mm endless belt is non-homogeneous
Property is 4%.
As shown in fig. 6, when the epitaxial wafer in the present invention is used to produce super power device, the first epitaxial layer of N-type 2 is etched
Four road grooves, i.e. first groove 61, second groove 62, the 3rd groove 63 and the 4th groove 64.The wherein width of first groove 61 is big
In other three road groove.As shown in fig. 7, the first epitaxial layer 2 is covered with the second epitaxial layer 4, the second epitaxial layer 4 is embedded in four road grooves
It is interior.Second epitaxial layer 4 is p-type.
Fig. 8 show the super junction power device testing electrical property figure produced using the epitaxial wafer in embodiment 1, the black in figure
Black circle represents electrical property failure position.From figure 8, it is seen that the position of its electrical property failure is considerably less, therefore, distribution of charges is equal
It is even, with breakdown voltage higher.Meet the use requirement of super junction power device.
Embodiment 2
Its production method difference from Example 1 is that monocrystalline silicon layer 5 is trichlorosilane anti-at 1045 DEG C with hydrogen
Should generate and be deposited on the surface of substrate 1.Remaining structure and production method are same as Example 1.
It is illustrated in figure 9 the epilayer resistance rate distribution map of the epitaxial wafer of the present embodiment production.It can be seen in fig. 9 that first
The resistivity of epitaxial layer 2 is distributed in concentric circles.From the center of circle, the resistivity heterogeneity of first 30mm endless belt is
1.1%.Second resistivity heterogeneity of 30mm endless belts is 1.2%.The 3rd resistivity heterogeneity of 30mm endless belts
It is 3.8%.
Figure 10 show the super junction power device testing electrical property figure produced using the epitaxial wafer in embodiment 2, black in figure
Color black circle represents electrical property failure position.From fig. 10 it can be seen that the position of its electrical property failure is considerably less, therefore, electric charge point
Cloth is uniform, with breakdown voltage higher.Meet the use requirement of super junction power device.
Embodiment 3
Its production method difference from Example 1 is that monocrystalline silicon layer 5 is trichlorosilane anti-at 1050 DEG C with hydrogen
Should generate and be deposited on the surface of substrate 1.Remaining structure and production method are same as Example 1.
The epilayer resistance rate distribution map of the epitaxial wafer for being produced for the present embodiment as shown in figure 11.As can be seen from Figure 11,
The resistivity of one epitaxial layer 2 is distributed in concentric circles.From the center of circle, the resistivity heterogeneity of first 30mm endless belt is
1.0%.Second resistivity heterogeneity of 30mm endless belts is 1.2%.The 3rd resistivity heterogeneity of 30mm endless belts
It is 3.7%.
Figure 12 show the super junction power device testing electrical property figure produced using the epitaxial wafer in embodiment 3, black in figure
Color black circle represents electrical property failure position.It can be recognized from fig. 12 that the position of its electrical property failure is considerably less, therefore, electric charge point
Cloth is uniform, with breakdown voltage higher.Meet the use requirement of super junction power device.
Embodiment 4
Its production method difference from Example 1 is that oxide layer 7 and the edge etch width L of diaphragm 8 are 1 millimeter.
Monocrystalline silicon layer 5 is not provided between N-type substrate 1 and N-type epitaxy layer 2.Remaining structure and production method are same as Example 1.
The epilayer resistance rate distribution map of the epitaxial wafer for being produced for the present embodiment as shown in figure 13.As can be seen from Figure 13,
The resistivity of one epitaxial layer is distributed in concentric circles.From the center of circle, the resistivity heterogeneity of first 30mm endless belt is
1.2%.Second resistivity heterogeneity of 30mm endless belts is 1.1%.The 3rd resistivity heterogeneity of 30mm endless belts
It is 4.2%.
Figure 14 show the super junction power device testing electrical property figure produced using the epitaxial wafer in embodiment 4, black in figure
Color black circle represents electrical property failure position.It is seen from figure 14 that the position of its electrical property failure is considerably less, therefore, electric charge point
Cloth is uniform, with breakdown voltage higher.Meet the use requirement of super junction power device.
Embodiment 5
Its production method difference from Example 1 is that oxide layer 7 and the edge etch width L of diaphragm 8 are 1 millimeter.
Monocrystalline silicon layer 5 is provided between N-type substrate 1 and N-type epitaxy layer 2.The thickness of monocrystalline silicon layer 5 is 4 μm.Monocrystalline silicon layer 5 is trichlorine silicon
Alkane reacts at 1090 DEG C with hydrogen and generates and be deposited on the surface of substrate 1.Remaining structure and production method are same as Example 1.
The epilayer resistance rate distribution map of the epitaxial wafer for being produced for the present embodiment as shown in figure 15.As can be seen from Figure 15,
The resistivity of one epitaxial layer 2 is distributed in concentric circles.From the center of circle, the resistivity heterogeneity of first 30mm endless belt is
1.0%.Second resistivity heterogeneity of 30mm endless belts is 1.2%.The 3rd resistivity heterogeneity of 30mm endless belts
It is 3.5%.
Figure 16 show the super junction power device testing electrical property figure produced using the epitaxial wafer in embodiment 5, black in figure
Color black circle represents electrical property failure position.As can be seen from Figure 16, the position of its electrical property failure is considerably less, therefore, electric charge point
Cloth is uniform, with breakdown voltage higher.Meet the use requirement of super junction power device.
Embodiment 6
Its production method difference from Example 1 is that oxide layer 7 and the edge etch width L of diaphragm 8 are 1 millimeter.
Monocrystalline silicon layer 5 is provided between N-type substrate 1 and N-type epitaxy layer 2.The thickness of monocrystalline silicon layer 5 is 4 μm.Monocrystalline silicon layer 5 is trichlorine silicon
Alkane reacts at 1100 DEG C with hydrogen and generates and be deposited on the surface of substrate 1.Remaining structure and production method are same as Example 1.
The epilayer resistance rate distribution map of the epitaxial wafer for being produced for the present embodiment as shown in figure 17.As can be seen from Figure 17,
The resistivity of one epitaxial layer 2 is distributed in concentric circles.From the center of circle, the resistivity heterogeneity of first 30mm endless belt is
1.2%.Second resistivity heterogeneity of 30mm endless belts is 1.2%.The 3rd resistivity heterogeneity of 30mm endless belts
It is 3.9%.
Figure 18 show the super junction power device testing electrical property figure produced using the epitaxial wafer in embodiment 6, black in figure
Color black circle represents electrical property failure position.As can be seen from Figure 18, the position of its electrical property failure is considerably less, therefore, electric charge point
Cloth is uniform, with breakdown voltage higher.Meet the use requirement of super junction power device.
The breakdown voltage for using the super junction power device that the epitaxial wafer shown in Fig. 2 produces is 580 volts；Using in the present invention
Epitaxial wafer production super junction power device breakdown voltage rise to 630 volts.Needing the collapse electricity of super junction power device
The field for 600 volts is pressed, the super junction power device produced using existing epitaxial wafer is unable to reach use requirement, uses the present invention
In epitaxial wafer production super junction power device can meet use requirement.Using the epitaxial wafer in the present invention, can be by superjunction power
The breakdown voltage of device improves more than 50 volts.
Embodiment in the present invention is only used for that the present invention will be described, does not constitute the limitation to right,
Other substantially equivalent replacements that those skilled in that art are contemplated that, all fall in the scope of protection of the present invention.
Claims (20)
1. epitaxial wafer, including substrate and the first epitaxial layer, it is characterised in that the first described epilayer resistance rate is in concentric circles
Distribution；Resistivity heterogeneity at the first epitaxial layer same radius is no more than 5%；The substrate and the first epitaxial layer it
Between be provided with monocrystalline silicon layer.
2. epitaxial wafer according to claim 1, it is characterised in that the first epitaxial layer radially every 30 mm in width from the center of circle
Resistivity heterogeneity in endless belt is no more than 5%.
3. epitaxial wafer according to claim 1, it is characterised in that the first epitaxial layer is radially uniform from the center of circle to be divided into three
Region, three region radial widths are identical, and the resistivity heterogeneity in each region is no more than 5%.
4. epitaxial wafer according to claim 1, it is characterised in that described monocrystalline silicon layer thickness is 2~5 μm.
5. the epitaxial wafer according to claim 1 or 4, it is characterised in that described monocrystalline silicon layer is trichlorosilane and hydrogen
Generation is reacted at 1040 DEG C~1100 DEG C.
6. epitaxial wafer according to claim 1, it is characterised in that described substrate is N-type.
7. epitaxial wafer according to claim 6, it is characterised in that described N-type substrate doped with arsenic, phosphorus and antimony extremely
A kind of few element.
8. the epitaxial wafer according to claim 6 or 7, it is characterised in that the first described epitaxial layer is N-type.
9. epitaxial wafer according to claim 8, it is characterised in that the first described epitaxial layer is doped with arsenic, phosphorus and antimony
At least one element.
10. epitaxial wafer according to claim 1, it is characterised in that described substrate is p-type.
11. epitaxial wafers according to claim 10, it is characterised in that described P type substrate is doped with boron.
12. epitaxial wafer according to claim 10 or 11, it is characterised in that the first described epitaxial layer is p-type.
13. epitaxial wafers according to claim 12, it is characterised in that the first described epitaxial layer is doped with boron.
14. epitaxial wafers according to claim 1, it is characterised in that first described epilayer resistance rate edge from the center of circle
Radially enlarged or reduction or alternately increase reduce or alternately reduction increase.
15. epitaxial wafers according to claim 1, it is characterised in that the substrate back has an oxide layer, the oxidation
Layer edge radius are smaller than substrate radius 1-2 millimeters.
The production method of the epitaxial wafer described in 16. claim 1-4,6-15 any claims, it is characterised in that including step
Suddenly：
One substrate is provided；Substrate back is aoxidized to form an oxide layer；By 1-2 millimeters of the oxide layer edge etch；
Depositing monocrystalline silicon layer over the substrate；
The first epitaxial layer is deposited in the monocrystalline surface.
The production method of 17. epitaxial wafers according to claim 16, it is characterised in that described monocrystalline silicon layer is trichlorine silicon
Alkane reacts generation with hydrogen at 1040 DEG C~1100 DEG C.
18. super junction power devices, it is characterised in that including the epitaxial wafer described in claim 1 to 15 any claim.
19. super junction power devices according to claim 18, it is characterised in that including described epitaxial wafer, the extension
The epitaxial layer of piece is provided around the groove in the center of circle；It is filled with the groove and the second epitaxial layer, the second epitaxial layer covering
In first epitaxial layer and the insertion groove；First epitaxial layer is different from the second epitaxial film materials.
20. super junction power devices according to claim 19, it is characterised in that the substrate is N-type, the first epitaxial layer is
N-type；Second epitaxial layer is p-type；Or the substrate is p-type, the first epitaxial layer is p-type；Second epitaxial layer is N
Type.
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