CN103632966A - Method for forming MOS transistor - Google Patents

Method for forming MOS transistor Download PDF

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Publication number
CN103632966A
CN103632966A CN201210299232.2A CN201210299232A CN103632966A CN 103632966 A CN103632966 A CN 103632966A CN 201210299232 A CN201210299232 A CN 201210299232A CN 103632966 A CN103632966 A CN 103632966A
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mos transistor
dielectric layer
layer
functional layer
gate dielectric
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CN103632966B (en
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张海洋
王新鹏
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity

Abstract

A method for forming an MOS transistor comprises providing a substrate; forming a back gate electrode, a back gate dielectric layer, a body region, a first functional layer and a front gate dielectric layer sequentially from the bottom surface of the substrate, the first functional layer being used for increasing the rate of migration of a carrier in a channel region; etching the front gate dielectric layer and the first functional layer and forming a first groove exposing a portion of the body region; conducting ion implantation on the first groove along the body region to form a heavily doped region; filling a metal layer in the first groove and forming a plug connected with the heavily doped region; and forming a second functional layer and a front gate on the surface of a front gate dielectric layer between the heavily doped regions sequentially from the bottom to the top, the second functional layer being used for reducing the leakage current of the channel region. The method for forming the MOS transistor can adjust the threshold voltage of the formed MOS transistor, improve the compatibility and matching rate of each MOS transistor in semiconductor devices and improve the performance of formed semiconductor devices.

Description

The formation method of MOS transistor
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of MOS transistor.
Background technology
Along with take the development of the Modern high-tech industry that electronic communication technology is representative, world's IC industry gross output value is every year with 30% speed development.Static random access memory is a kind of vitals in integrated circuit, and its size is little, density is high.In semiconductor storage unit, static random access memory devices (SRAM) is compared with dynamic random access memory (DRAM) device has advantages of lower power consumption and operating rate faster.Static RAM can carry out physical location location by bitmap testing equipment again at an easy rate, the actual effect pattern of research product.In addition, the yield of static RAM can be used as the important indicator of weighing the whole process rate of a kind of semiconductor, and the manufacture method of therefore studying static random access memory devices receives increasing concern.
The unit of static random access memory can be divided into ohmic load static random access memory cell and complementary metal oxide semiconductors (CMOS) (CMOS) static random access memory cell.Ohmic load static random access memory cell adopts the resistance of high resistance as load device, and CMOS static random-access memory unit adopts P-channel metal-oxide-semiconductor (PMOS) transistor as load device.
In CMOS static random asccess memory, comprise a plurality of nmos pass transistors and PMOS transistor, difference due to manufacturing process, cause the transistorized threshold voltage of manufacturing different, thereby cause static random access memory internal components static random access memory and other device in circuit incompatible or manufacturing incompatible.Transistorized threshold voltage is mainly relevant with the factor such as the kind of the structure of transistor pellicular cascade in manufacture process and formation method, transistor each several part critical dimension, Implantation and condition.In prior art, mainly by changing the method for the thickness of sidewall, improve the incompatibility problem between manufacturing static random access memory internal transistor.
In the Chinese patent application that is CN101640187A at publication number, can also find more about prior art compatible between transistor in improving static random access memory.
Yet, along with the continuous minimizing of transistor feature size, by changing the method for the thickness of sidewall, can increase undoubtedly the shared volume of MOS transistor, and then be unfavorable for reducing of transistor feature size.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of MOS transistor, to form the adjustable MOS transistor of threshold voltage, improves the compatibility of the MOS transistor that forms.
For addressing the above problem, the invention provides a kind of formation method of MOS transistor, comprising: substrate is provided; At described substrate surface, form successively from the bottom to top back grid, back of the body gate dielectric layer, body region, the first functional layer and front gate dielectric layer, described the first functional layer is for improving the migration rate of channel region charge carrier; Gate dielectric layer and the first functional layer before described in etching, form the first groove that exposes part body region; Along described the first groove, described body region is carried out to Implantation, form heavily doped region; In described the first groove, fill metal level, form the connector being connected with heavily doped region; Front gate dielectric layer surface between heavily doped region forms the second functional layer and normal-gate from the bottom to top successively, and described the second functional layer is for reducing the leakage current of channel region.
Optionally, the material of described the first functional layer is topological insulating material, and described topological insulating material is Bi 2te 3, Bi 2se 3or Sb 2te 3.
Optionally, the material of described the second functional layer is silicon nitride or silicon oxynitride.
Compared with prior art, technical solution of the present invention has the following advantages:
The first functional layer (topological insulating material) that allows electric charge to move by form built-in electrical insulation, interface below front gate dielectric layer, improve the migration rate of charge carrier in MOS transistor channel region, and then the threshold voltage of adjusting MOS transistor, improve the matching degree that is arranged in the dissimilar MOS transistor of same device (PMOS transistor AND gate nmos pass transistor).
In addition, by form the leakage current that the second functional layer reduces MOS transistor channel region on front gate dielectric layer, reducing the minimum of MOS transistor can operating voltage (minimum operating voltage), improve adjustable extent and the stability of MOS transistor threshold voltage, and then improve the electric property of the MOS transistor that forms.
Accompanying drawing explanation
Fig. 1 to Figure 11 is the generalized section that embodiment of formation method of MOS transistor of the present invention forms each stage of MOS transistor.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here, implement, so the present invention has not been subject to the restriction of following public specific embodiment.
Just as described in the background section, in existing semiconductor device, comprise a plurality of nmos pass transistors and PMOS transistor, difference due to manufacturing process, cause the transistorized threshold voltage of manufacturing nmos pass transistor and PMOS not identical, and then cause each device semiconductor device and other device in circuit incompatible or manufacturing of semiconductor device inside incompatible.
For above-mentioned defect, the invention provides a kind of formation method of MOS transistor, by forming the first functional layer between MOS transistor back of the body gate dielectric layer and front gate dielectric layer, form the threshold voltage that the second functional layer regulates formed MOS transistor above front gate dielectric layer, and then MOS transistor dissimilar in same semiconductor device (PMOS transistor and nmos pass transistor) is mated mutually, each device that improves semiconductor device inside is compatible.
Below in conjunction with accompanying drawing, be elaborated.
Fig. 1～Figure 11 shows the cross-sectional view in each stage of MOS transistor that forms in embodiment of formation method of MOS transistor of the present invention, with reference to figure 1～Figure 11, by specific embodiment, the formation method of MOS transistor of the present invention is described further.
With reference to figure 1, provide substrate 201.
In the present embodiment, the material of described substrate 201 is silicon, germanium or silicon-on-insulator (Silicon-On-Insulator, SOI), or well known to a person skilled in the art other semiconductive material substrate, and the present invention does not limit this.
Continuation, with reference to figure 1, forms back grid 203, back of the body gate dielectric layer 205, body region 206, the first functional layer 207a, front gate dielectric layer 209a and patterned photoresist layer 213 from the bottom to top successively on described substrate 201 surfaces.
Wherein, described patterned photoresist layer 213 exposes the front gate dielectric layer 209a corresponding with heavily doped region.
The material of described back grid 203 is semi-conducting material or the polysilicon of doping; The material of described back of the body gate dielectric layer 205 is one or more in oxide, nitride, nitrogen oxide.In the present embodiment, the material of described back of the body gate dielectric layer 205 is silicon nitride.
The material of described body region 206 is silicon, germanium silicon or polysilicon.
Described the first functional layer 207a is for improving the migration rate of channel region charge carrier, and its material can be topological insulating material.Topology insulating material is the material that a kind of built-in electrical insulation, interface allow electric charge to move, and the body electronic state of topological insulating material is the insulator that has energy gap, and its surface is the metallic state without energy gap.Described topological insulating material can be Bi 2te 3, Bi 2se 3or Sb 2te 3.The method that forms described the first functional layer 207a is molecular beam epitaxial growth technique, and the thickness range of described the first functional layer 207a is 10 dust～500 dusts.In the present embodiment, the material of described the first functional layer 207a is Bi 2te 3.
The material of described front gate dielectric layer 209a is high k material, as hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, one or more of lead oxide scandium tantalum or lead niobate zinc, or above-mentioned high k material and silica, the composition of silicon nitride and/or silicon oxynitride, described front gate dielectric layer 209a can pass through ald (Atom Layer Deposition, ALD), chemical vapour deposition (CVD) (Chemical Vapor Deposition, CVD) or physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) form.In the present embodiment, the material of described front gate dielectric layer 209a is aluminium oxide (Al 2o 3), the formation method of described front gate dielectric layer 209a is ald.
With reference to figure 2, the described patterned photoresist layer 213 of take is mask, and front gate dielectric layer 209a and the first functional layer 207a described in etching Fig. 1, to form the first groove 215 that exposes part body region 206.Described the first groove 215 runs through described front gate dielectric layer 209b and the first functional layer 207b.
In the present embodiment, described in etching before the method for gate dielectric layer 209a and the first functional layer 207a be dry etching, its concrete etching technics, as those skilled in the art's known technology, does not describe in detail at this.
In other embodiments, also can form the first groove 215 by well known to a person skilled in the art that other techniques carry out etching to described front gate dielectric layer 209a and the first functional layer 207a, it does not limit the scope of the invention.
Continuation, with reference to figure 2, is carried out Implantation along the body region 206 of 215 pairs of the first groove 215 bottoms of the first groove, forms heavily doped region (not shown), and the body region 206 between heavily doped region is as the channel region of MOS transistor.
In the present embodiment, the doping ion of described Implantation is by the type decided of formed MOS transistor.For example, the MOS transistor that forms is PMOS transistor, and described doping ion is boron ion or boron nitride ion; The MOS transistor that forms is nmos pass transistor, and described doping ion is arsenic ion, phosphonium ion or antimony ion.
With reference to figure 3, deposit metallic material 217a in described the first groove 215 and on the photoresist layer 213 of the first groove 215 opening both sides.
In the present embodiment, the material of described metal material 217a is copper, tungsten or copper-tungsten, and the method for deposit metallic material 217a is physical gas-phase deposition or chemical vapor deposition method.
With reference to figure 4, metal material 217a described in planarization Fig. 3 and photoresist layer 213, to exposing front gate dielectric layer 209b, form the connector 217b be connected with heavily doped region, described connector 217b is used for making realizing and being electrically connected between body region 206 heavily doped regions and external power source.
In the present embodiment, the method for metal material 217a and photoresist layer 213 is chemical mechanical milling tech described in planarization, and its concrete technology step is thought conventionally known to one of skill in the art, at this, does not repeat.
In other embodiments, after in Fig. 2, heavily doped region forms, can also first remove described photoresist layer 213, deposit metallic material in the first groove 215 and on the front gate dielectric layer 209b of the first groove 215 opening both sides again, described in planarization, metal material, to exposing front gate dielectric layer 209b, forms the connector 217b being connected with heavily doped region in body region 206 in Fig. 4 again.
With reference to figure 5, remove connector 217b in Fig. 4 and, away from front gate dielectric layer 209b and the first functional layer 207b of channel region one side, retain front gate dielectric layer 209b and the first functional layer 207b of channel region top.
In the present embodiment, removal connector 217b comprises the steps: away from front gate dielectric layer 209b and the first functional layer 207b of channel region one side
Front gate dielectric layer 209b surface above described channel region forms mask layer (not shown);
The mask layer on gate dielectric layer 209b surface was mask in the past, and etching connector 217b is away from front gate dielectric layer 209b and the first functional layer 207b of channel region one side, to exposing part body region 206;
The mask layer on gate dielectric layer 209b surface before removing.
In other embodiments, can also not remove connector 217b away from front gate dielectric layer 209b and the first functional layer 207b of channel region one side, its performance impact to formed MOS transistor is little.
With reference to figure 6, form the sacrifice layer 219a of part body region 206, front gate dielectric layer 209b and connector 217b in coverage diagram 5.
Concrete, the material of described sacrifice layer 219a can be one of polysilicon, amorphous silicon, monocrystalline silicon, polycrystalline germanium, amorphous germanium, monocrystalline germanium, SiGe.
In the present embodiment, the material of described sacrifice layer 219a is polysilicon, and the method that forms described sacrifice layer 219a is ald.
Continuation, with reference to figure 6, forms photoresist layer on described sacrifice layer 219a, and graphical described photoresist layer, retains the photoresist layer 221 corresponding with alternative normal-gate region.
In the present embodiment, described photoresist layer 211 is positioned at directly over channel region and (that is, substitutes normal-gate region corresponding part channel region), and its shape, size are corresponding with shape, the size of the second functional layer below follow-up normal-gate to be formed and normal-gate.Graphical described photoresist layer can adopt existing any photoetching process to carry out, and at this, does not repeat.
In the present embodiment, using photoresist layer 211 as barrier layer, and take described photoresist layer 211 and carry out follow-up etching as mask; In other embodiments, can also take photoresist layer 211 as mask, the other materials of usining carries out follow-up etching as barrier layer.
With reference to figure 7, the photoresist layer 221 in Fig. 6 of take is mask, and sacrifice layer 219a described in etching, to exposing part normal-gate dielectric layer 209b, connector 217b and part body region 206, forms and substitute normal-gate 219b.
In the present embodiment, the method for sacrifice layer 219a is dry etching described in etching, and its concrete technology parameter, as those skilled in the art's known technology, does not repeat at this.
Continuation, with reference to figure 7, is removed photoresist layer 221.
In the present embodiment, the method for removing photoresist layer 221 is cineration technics, but the invention is not restricted to this.
With reference to figure 8, in Fig. 7, part body region 206, the front gate dielectric layer 209b of part and connector 217b surface form interlayer dielectric layer 223, the upper surface flush of the upper surface of described interlayer dielectric layer 223 and alternative normal-gate 217b.
In the present embodiment, the material of described interlayer dielectric layer 223 is low-k materials or super low-k materials, and the method that forms described interlayer dielectric layer 223 is chemical vapor deposition method, but the invention is not restricted to this.
With reference to figure 9, remove described in Fig. 8 and substitute normal-gate 219b, forming bottom is that front gate dielectric layer 209c, sidewall are the second groove 225 of interlayer dielectric layer 223.
In the present embodiment, the removal technique of described alternative normal-gate 219b is identical with the etching technics of sacrifice layer 219a in Fig. 6, at this, does not repeat.
With reference to Figure 10, in the interior formation of the second groove 225 described in Fig. 9 the second functional layer 227 be positioned at the normal-gate 229 in described the second functional layer 227, the upper surface flush of the upper surface of described normal-gate 229 and interlayer dielectric layer 223.
In the present embodiment, the material of described the second functional layer 227 is silicon nitride or silicon oxynitride, and it is chemical vapour deposition (CVD) or ald that described the second functional layer 227 forms technique, and the thickness of described the second functional layer 227 is 10 dust～200 dusts.Described the second functional layer 227 can avoid the channel region of formed MOS transistor to produce leakage current, reducing the minimum of MOS transistor can operating voltage, improve the adjustable extent of the threshold voltage of the MOS transistor that forms, and then improved the stability of the MOS transistor that forms.
The material of described normal-gate 229 is metal (as: tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminium, lead, platinum, tin, silver or gold), conducing composite material (as tantalum nitride, titanium nitride, tungsten silicide, tungsten nitride, ruthenium-oxide, nickle silicide etc.), carbon nano-tube or conductive carbon.
With reference to Figure 11, remove interlayer dielectric layer 223 described in Figure 10.
In the present embodiment, the method for the described interlayer dielectric layer 223 of described removal is dry etching, but the invention is not restricted to this.
In above embodiment, by being formed for improving the first functional layer of charge carrier migration rate on channel region below front gate dielectric layer, above front gate dielectric layer, be formed for reducing the threshold voltage that the second functional layer of leakage current on channel region regulates formed MOS transistor, improve the matching degree that is arranged in the dissimilar MOS transistor of same semiconductor device (PMOS transistor AND gate nmos pass transistor), and then improved the electric property of the semiconductor device that forms.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.

Claims (12)

1. a formation method for MOS transistor, is characterized in that, comprising:
Substrate is provided;
At described substrate surface, form successively from the bottom to top back grid, back of the body gate dielectric layer, body region, the first functional layer and front gate dielectric layer, described the first functional layer is for improving the migration rate of channel region charge carrier;
Gate dielectric layer and the first functional layer before described in etching, form the first groove that exposes part body region;
Along described the first groove, described body region is carried out to Implantation, form heavily doped region;
In described the first groove, fill metal level, form the connector being connected with heavily doped region;
Front gate dielectric layer surface between heavily doped region forms the second functional layer and normal-gate from the bottom to top successively, and described the second functional layer is for reducing the leakage current of channel region.
2. the formation method of MOS transistor as claimed in claim 1, is characterized in that, the material of described the first functional layer is topological insulating material.
3. the formation method of MOS transistor as claimed in claim 2, is characterized in that, described topological insulating material is Bi 2te 3, Bi 2se 3or Sb 2te 3.
4. the formation method of MOS transistor as claimed in claim 2 or claim 3, is characterized in that, the method that forms the first functional layer is molecular beam epitaxial growth technique.
5. the formation method of MOS transistor as claimed in claim 1, is characterized in that, the thickness of described the first functional layer is 10 dust～500 dusts.
6. the formation method of MOS transistor as claimed in claim 1, is characterized in that, the material of described the second functional layer is silicon nitride or silicon oxynitride.
7. the formation method of MOS transistor as claimed in claim 6, is characterized in that, the method that forms described the second functional layer is chemical vapour deposition (CVD) or ald.
8. the formation method of MOS transistor as claimed in claim 1, is characterized in that, the thickness of described the second functional layer is 10 dust～200 dusts.
9. the formation method of MOS transistor as claimed in claim 1, is characterized in that, the material of described front gate dielectric layer is high k material.
10. the formation method of MOS transistor as claimed in claim 1, is characterized in that, the material of described back grid is polysilicon.
The formation method of 11. MOS transistor as claimed in claim 1, is characterized in that, the material of described back of the body gate dielectric layer is silica.
The formation method of 12. MOS transistor as claimed in claim 1, is characterized in that, the technique that forms the second functional layer and normal-gate comprises:
Form the sacrifice layer of cover part body region, front gate dielectric layer and connector;
On described sacrifice layer, form photoresist layer, and graphical described photoresist layer, the photoresist layer corresponding with alternative normal-gate retained;
Take that to retain the photoresist layer corresponding with alternative normal-gate be mask, sacrifice layer described in etching, to exposing part body region, normal-gate dielectric layer and connector, forms alternative normal-gate;
On the body region of described alternative normal-gate both sides, front gate dielectric layer and connector, form interlayer dielectric layer, the upper surface of described interlayer dielectric layer and the upper surface flush of alternative normal-gate;
Remove described alternative normal-gate, form the second groove that bottom is interlayer dielectric layer for front gate dielectric layer, sidewall;
In described the second groove, form successively from the bottom to top the second functional layer and normal-gate;
Remove described interlayer dielectric layer.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105514163A (en) * 2014-09-26 2016-04-20 中芯国际集成电路制造(上海)有限公司 Fin field effect transistor and forming method thereof
CN105514162A (en) * 2014-09-26 2016-04-20 中芯国际集成电路制造(上海)有限公司 Fin field effect transistor and forming method thereof
CN114561623A (en) * 2021-11-05 2022-05-31 杭州大和热磁电子有限公司 Surface treatment method for bismuth telluride material

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1656596A (en) * 2002-05-20 2005-08-17 先进微装置公司 Gate oxide process methods for high performance mos transistors by reducing remote scattering
CN1815755A (en) * 2004-12-22 2006-08-09 台湾积体电路制造股份有限公司 Semiconductor device and method for manufacturing it
JP2006344837A (en) * 2005-06-09 2006-12-21 Matsushita Electric Ind Co Ltd Semiconductor apparatus and manufacturing method thereof
US20090020802A1 (en) * 2007-07-16 2009-01-22 Yi Ma Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices
CN101369607A (en) * 2007-08-17 2009-02-18 中芯国际集成电路制造(上海)有限公司 Flash memory unit structure and preparation thereof
US20120138115A1 (en) * 2010-12-06 2012-06-07 Purdue Research Foundation Surface excitonic thermoelectric devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1656596A (en) * 2002-05-20 2005-08-17 先进微装置公司 Gate oxide process methods for high performance mos transistors by reducing remote scattering
CN1815755A (en) * 2004-12-22 2006-08-09 台湾积体电路制造股份有限公司 Semiconductor device and method for manufacturing it
JP2006344837A (en) * 2005-06-09 2006-12-21 Matsushita Electric Ind Co Ltd Semiconductor apparatus and manufacturing method thereof
US20090020802A1 (en) * 2007-07-16 2009-01-22 Yi Ma Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices
CN101369607A (en) * 2007-08-17 2009-02-18 中芯国际集成电路制造(上海)有限公司 Flash memory unit structure and preparation thereof
US20120138115A1 (en) * 2010-12-06 2012-06-07 Purdue Research Foundation Surface excitonic thermoelectric devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HAN LIU,PEIDE D.YE: "Atomic-layer-deposited Al2O3 on Bi2Te3 for topological insulator field-effect transistors", 《APPLIED PHYSICS LETTERS》 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105514163A (en) * 2014-09-26 2016-04-20 中芯国际集成电路制造(上海)有限公司 Fin field effect transistor and forming method thereof
CN105514162A (en) * 2014-09-26 2016-04-20 中芯国际集成电路制造(上海)有限公司 Fin field effect transistor and forming method thereof
CN105514162B (en) * 2014-09-26 2018-08-10 中芯国际集成电路制造(上海)有限公司 Fin formula field effect transistor and forming method thereof
CN105514163B (en) * 2014-09-26 2018-09-07 中芯国际集成电路制造(上海)有限公司 Fin formula field effect transistor and forming method thereof
CN114561623A (en) * 2021-11-05 2022-05-31 杭州大和热磁电子有限公司 Surface treatment method for bismuth telluride material

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