CN105514162B - Fin formula field effect transistor and forming method thereof - Google Patents

Fin formula field effect transistor and forming method thereof Download PDF

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Publication number
CN105514162B
CN105514162B CN201410505413.5A CN201410505413A CN105514162B CN 105514162 B CN105514162 B CN 105514162B CN 201410505413 A CN201410505413 A CN 201410505413A CN 105514162 B CN105514162 B CN 105514162B
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fin
layer
surface
material
field effect
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CN201410505413.5A
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CN105514162A (en
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张海洋
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中芯国际集成电路制造(上海)有限公司
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Abstract

A kind of fin formula field effect transistor and forming method thereof, the forming method of the fin formula field effect transistor includes:Substrate is provided, the substrate surface has fin, and the material of the fin portion surface is crystalline material;Separation layer is formed in the substrate surface, the surface of the separation layer is less than fin top, and the side wall of the separation layer covering part fin, the separation layer are amorphous material;Channel layer is formed in the side wall and top surface of the insulation surface and fin, the material of the channel layer is topological insulating materials;Gate dielectric layer is formed in the channel layer surface;It is developed across the grid layer of the fin on the gate dielectric layer surface.It can prevent from being formed by fin formula field effect transistor generation short-channel effect and leakage current, improve the performance of fin formula field effect transistor.

Description

Fin formula field effect transistor and forming method thereof

Technical field

The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of fin formula field effect transistor and its formation sides Method.

Background technology

With the rapid development of semiconductor fabrication, semiconductor devices is towards higher component density and higher The direction of integrated level is developed.Transistor is just being widely used at present as most basic semiconductor devices, therefore with semiconductor The raising of the component density and integrated level of device, the grid size of planar transistor is also shorter and shorter, traditional planar transistor It dies down to the control ability of channel current, generates short-channel effect, generate leakage current, the final electrical property for influencing semiconductor devices Energy.

In order to overcome the short-channel effect of transistor, leakage current, the prior art is inhibited to propose fin formula field effect transistor (Fin FET).Fin formula field effect transistor is a kind of common multi-gate device.

As shown in Figure 1, be a kind of dimensional structure diagram of fin formula field effect transistor, including:Semiconductor substrate 100; Fin 101 positioned at 100 surface of semiconductor substrate;Dielectric layer 102 positioned at 100 surface of semiconductor substrate, the dielectric layer 102 The side wall of fin 101 described in covering part, and 102 surface of dielectric layer is less than 101 top of fin;Positioned at 102 surface of dielectric layer, with And the top of fin 101 and the gate structure 103 of sidewall surfaces;Source in the fin 101 of 103 both sides of the gate structure Area 104a and drain region 104b.

However, with the diminution of dimensions of semiconductor devices, the degradation of fin formula field effect transistor needs to seek into one The method that step improves fin formula field effect transistor performance.

Invention content

Problems solved by the invention is to prevent fin formula field effect transistor from generating short-channel effect and leakage current, is improved The performance of fin formula field effect transistor.

To solve the above problems, the present invention provides a kind of forming method of fin formula field effect transistor, including:Lining is provided Bottom, the substrate surface have fin, and the material of the fin portion surface is crystalline material;It is formed and is isolated in the substrate surface The surface of layer, the separation layer is less than at the top of fin, and the side wall of the separation layer covering part fin, the material of the separation layer Material is amorphous material;Channel layer is formed in the side wall and top surface of the insulation surface and fin, the channel layer Material is topological insulating materials;Gate dielectric layer is formed in the channel layer surface;It is developed across institute on the gate dielectric layer surface State the grid layer of fin.

Optionally, the topological insulating materials is Bi2Te3、Bi2Se3Or Sb2Te3

Optionally, the formation process of the channel layer includes epitaxy technique twice.

Optionally, the epitaxial deposition process twice is molecular beam epitaxial process.

Optionally, the epitaxy technique twice includes:First time epitaxy technique, the first time epitaxy technique have first Technological temperature;After the first time epitaxy technique, second of epitaxy technique is carried out, second of epitaxy technique has the Two technological temperatures, and second technological temperature is higher than first technological temperature.

Optionally, the material of the fin portion surface is aluminium oxide, silicon or silica.

Optionally, the material of the fin portion surface is aluminium oxide, and the aluminium oxide of the fin top surface has (0001) Crystal face.

Optionally, the material of the gate dielectric layer includes high K dielectric material.

Optionally, the high K dielectric material includes:Aluminium oxide, hafnium oxide, hafnium silicon oxide, nitrogen oxidation hafnium silicon, lanthana, Lanthana aluminium, zirconium oxide, zirconium silicon oxide, nitrogen oxidation zirconium silicon, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia One or more combinations in titanium, yttrium oxide, lead oxide scandium tantalum, lead niobate zinc.

Optionally, the material of the gate dielectric layer further includes one or more in silica, silicon nitride, silicon oxynitride.

Optionally, the material of the grid layer is polysilicon.

Optionally, further include:Dielectric layer, the surface of the dielectric layer and the grid are formed on the gate dielectric layer surface The surface of layer flushes;The grid layer is removed, forms opening in the dielectric layer;Grid is formed in the opening.

Optionally, the material of the grid includes metal, the metal be tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminium, lead, It is one or more in platinum, tin, silver, gold.

Optionally, the material of the grid further includes metallic compound, the metallic compound be titanium nitride, tantalum nitride, It is one or more in tungsten silicide, tungsten nitride, ruthenium-oxide, cobalt silicide, nickle silicide.

Optionally, the material of the grid is carbon nano-tube material or conductive carbon material.

Optionally, there are Doped ions in the grid.

Optionally, the formation process of the fin includes:Substrate is provided;Mask layer is formed in the substrate surface, it is described Mask layer covers the corresponding region for needing to form fin;Using the mask layer as mask, the substrate is etched, in the substrate Groove is formed, the substrate between adjacent trenches forms fin, and the substrate for being located at the fin bottom forms substrate;Described in etching After substrate, the mask layer is removed.

Optionally, the material of the separation layer is silica;The formation process of the separation layer includes:In the substrate and Fin portion surface forms isolation film;The isolation film is planarized, until exposing the top surface of fin;In flatening process Later, it is etched back to the isolation film, and exposes the partial sidewall surface of the fin, forms separation layer.

Optionally, further include:After forming the grid layer, the fin portion surface in the grid layer both sides forms source region The drain region and.

Correspondingly, being formed by fin formula field effect transistor using any of the above-described method the present invention also provides a kind of, wrap It includes:Substrate, the substrate surface have fin, and the material of the fin portion surface is crystalline material;Positioned at the substrate surface The surface of separation layer, the separation layer is less than at the top of fin, and the side wall of the separation layer covering part fin, the separation layer For amorphous material;Positioned at the channel layer of the side wall and top surface of the insulation surface and fin, the material of the channel layer Material is topological insulating materials;Positioned at the gate dielectric layer of the channel layer surface;Grid layer positioned at the gate dielectric layer surface, institute Grid layer is stated across the fin.

Compared with prior art, technical scheme of the present invention has the following advantages:

In the forming method of the present invention, channel layer is formed in separation layer and fin portion surface, and the channel layer is used to form The channel region of fin formula field effect transistor.The material of the channel layer is topological insulating materials, the table of the topology insulating materials Face is the metallic state of no band gap, can be conductive, and the inside of the topological insulating materials is the insulator for having band gap, Therefore, when forming channel layer with the topological insulating materials, can be made with the surface that the channel layer is in contact with gate dielectric layer To allow the transistor channel of carrier mobility, moreover, because the topology insulating materials only allows carrier in surface migration, Therefore, the thickness of the transistor channel is very thin, the generation that can be effectively inhibited short-channel effect, prevent leakage current, ensures The performance for being formed by fin formula field effect transistor is more stable.Moreover, the conductive capability on the topology insulating materials surface It is not influenced by surface concrete structure pattern, also not by impurity effect, therefore, the conductive capability of the channel layer is stablized, favorably Stablize in making the property retention for being formed by fin formula field effect transistor.

Further, since the material of the fin portion surface is crystalline material, therefore in the side wall and top surface of the fin The channel layer of formation can also have good crystalline structure so that it is in good metallic state to be formed by channel layer surface, then Stablize positioned at the side wall of fin and the channel layer surface conductive capability of top surface.Since the separation layer is amorphous material, So that the crystal lattice state for being formed in the channel layer of the insulation surface is mixed and disorderly, that causes insulation surface channel layer surface can not Good metallic state is formed, then the channel layer conductive capability of insulation surface is poor.Since the channel layer of the fin portion surface is used In the channel region for forming transistor, and the channel layer of insulation surface is needed with the ability being electrically isolated, therefore in the isolation Layer and fin portion surface form channel layer, can either ensure the performance for being formed by channel region, and can ensure between adjacent fin Channel layer can be electrically isolated.It leaks electricity between fin formula field effect transistor therefore, it is possible to avoid being formed by, ensures institute's shape At fin formula field effect transistor performance stablize.

Further, the formation process of the channel layer includes epitaxy technique twice.In the epitaxy technique twice, first Secondary epitaxy technique has the first technological temperature, and first technological temperature is relatively low, can form gradient coating performance and preferably open up Flutter insulating materials so that the channel layer is evenly covered on the side wall and top surface of insulation surface and fin, and It can closely be contacted with the surface of separation layer and fin.After the first time epitaxy technique, second of extension is carried out Technique, second of epitaxy technique has the second technological temperature, and second technological temperature is higher than first process warm Degree, therefore, second of epitaxy technique can form the neat topology of lattice structure absolutely in the side wall and top surface of fin Edge material, the topological insulating materials dense uniform for making fin side wall and top surface be formed, have good surface conductance ability, And built-in electrical insulation ability, it can make to be formed by the channel region performance of transistor more preferably.

Further, the material of the fin portion surface is aluminium oxide, and the aluminium oxide of the fin top surface has (0001) crystal face.The topology insulation with good gradient coating performance can be formed on the alumina material surface of the crystalline state Material so as to form channel layer in homogeneous thickness in the side wall of fin and top surface, and is formed by channel layer and fin Portion's intimate surface contact effectively inhibits leakage current so as to make the performance for being formed by fin formula field effect transistor stablize Generation.Moreover, can make to be formed by channel layer with good lattice structure, channel layer table is formed by ensure that Face is in the good metallic state of conductive capability, makes to be formed by transistor performance stabilization.

In the structure of the present invention, the side wall and top surface of the substrate surface and fin have channel layer, the isolation Layer is located at the channel layer surface on substrate, and grid layer is located at the separation layer and gate dielectric layer surface, and is developed across the fin The grid layer in portion.The channel layer is used to form the raceway groove of fin formula field effect transistor, and the material of the channel layer is that topology is exhausted The surface of edge material, the topology insulating materials is the metallic state of no band gap, can be conductive, and the topological insulating materials Inside be the insulator for having band gap, therefore, it is possible to using the surface that the channel layer is in contact with gate dielectric layer as permit Perhaps the transistor channel of carrier mobility makes institute moreover, because the topology insulating materials only allows carrier in surface migration The thickness for stating transistor channel is very thin, so as to the generation for effectively inhibiting short-channel effect, preventing leakage current, ensure that institute The performance of the fin formula field effect transistor of formation is more stable.Moreover, the conductive capability on the topology insulating materials surface not by The influence of surface concrete structure pattern, also not by impurity effect, therefore, the conductive capability of the channel layer is stablized, and is conducive to make The property retention for being formed by fin formula field effect transistor is stablized.

Description of the drawings

Fig. 1 is a kind of dimensional structure diagram of fin formula field effect transistor;

Fig. 2 is cross-sectional views of the Fig. 1 along the directions AA ';

Fig. 3 to Fig. 9 is the cross-sectional view of the forming process of the fin formula field effect transistor of the embodiment of the present invention.

Specific implementation mode

As stated in the background art, with the diminution of dimensions of semiconductor devices, the degradation of fin formula field effect transistor.

By the study found that referring to FIG. 2, Fig. 2 is cross-sectional views of the Fig. 1 along the directions AA ', in the fin field When effect transistor works, the subregion transoid that the fin 101 is in contact with gate structure 103 forms channel region 105. With the diminution of dimensions of semiconductor devices, the width of the fin 101 is caused to reduce, in the fin 101, carrier is not only It gathers, can also be gathered in the region of 101 side wall of fin, so as to cause being produced in the region close to 101 top of fin The distance at raw 105 bottom of channel region to 101 top of fin is excessive, that is, the thickness for being formed by channel region 105 is blocked up, causes institute The fin formula field effect transistor of formation easy tos produce short-channel effect, generates leakage current, the property of the fin formula field effect transistor It can be deteriorated.

To solve the above-mentioned problems, a kind of fin formula field effect transistor of present invention proposition and forming method thereof.In formation side In method, channel layer is formed in separation layer and fin portion surface, and the channel layer is used to form the raceway groove of fin formula field effect transistor Area.The material of the channel layer is topological insulating materials, and the surface of the topology insulating materials is the metallic state of no band gap, Can be conductive, and the inside of the topological insulating materials is the insulator for having band gap, therefore, with the topological insulating materials It, can be using the surface that the channel layer is in contact with gate dielectric layer as the transistor for allowing carrier mobility when forming channel layer Raceway groove, moreover, because the topology insulating materials only allows carrier in surface migration, therefore, the thickness of the transistor channel The generation very thin, short-channel effect can be effectively inhibited, prevent leakage current is spent, ensure that and be formed by fin field effect crystal The performance of pipe is more stable.Moreover, the conductive capability on the topology insulating materials surface is not by the shadow of surface concrete structure pattern It rings, also not by impurity effect, therefore, the conductive capability of the channel layer is stablized, and is conducive to make to be formed by fin field effect crystalline substance The property retention of body pipe is stablized.

To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.

Fig. 3 to Fig. 9 is the cross-sectional view of the forming process of the fin formula field effect transistor of the embodiment of the present invention.

Referring to FIG. 3, providing substrate 200,200 surface of the substrate has fin 201, the material on 201 surface of the fin Material is crystalline material.

Due to subsequently needing side wall and top surface in the fin 201 to form topological insulating materials as channel layer, And the topological insulating materials is crystalline material, and need to be formed with epitaxy technique, the side wall and top surface of the fin 201 Material need for crystalline material, so as to form the topological insulating materials in crystalline structure with epitaxy technique.The fin The material on 201 surfaces is aluminium oxide, silicon or silica;In the present embodiment, the material on 201 surface of the fin is the oxidation of crystalline state Aluminium.

In the present embodiment, the fin 201 is etched by the substrate provided and is formed;The formation process packet of the fin 201 It includes:Substrate is provided;Mask layer is formed in the substrate surface, the mask layer covering needs to form the corresponding region of fin 201; Using the mask layer as mask, the substrate is etched, forms groove in the substrate, the substrate between adjacent trenches forms fin Portion 201, the substrate for being located at 201 bottom of the fin form substrate 200;After etching the substrate, the mask layer is removed.

The substrate includes semiconductor layer and the alumina layer positioned at semiconductor layer surface, and the mask layer is formed Fin is formed in the alumina layer surface, and by etching the alumina layer.The semiconductor layer is monocrystalline silicon layer, monocrystalline Germanium layer, germanium-silicon layer, silicon carbide layer, silicon on insulator layer or germanium on insulator layer;The semiconductor layer is used to form follow-up institute's shape At fin formula field effect transistor bottom grid, the bottom grid is provided commonly for the grid for being subsequently formed in fin portion surface The channel layer being subsequently formed is controlled to be turned on and off.The material of the alumina layer is crystalline state aluminium oxide, is single in the present embodiment Crystalline state aluminium oxide or sapphire (Sapphire) material;The alumina layer is formed in the semiconductor layer by epitaxy technique Surface, the epitaxy technique in the present embodiment are that molecular beam epitaxy (Molecular Beam Epitaxy, abbreviation MBE) deposits work Skill, pulse laser technique or metal organic chemical vapor deposition (MOCVD), and the crystal face for being formed by alumina layer surface refers to Number is (0001), then can ensure to be subsequently formed good in the raceway groove layer lattice structure on 201 surface of fin;The alumina layer Thickness is greater than or equal to the height of the fin 201 of required formation so that is formed by 201 side wall of fin and top surface material is equal For aluminium oxide.

The material of the mask layer is silica, silicon nitride, silicon oxynitride, one or more in amorphous carbon, described The formation process of mask layer includes:In substrate surface deposition of mask material film, the present embodiment, the mask material film is formed in Alumina layer surface;Patterned photoresist layer is formed in the mask material film surface using photoetching process, with the figure The photoresist layer of change is mask, etches the mask material film until exposing substrate surface, forms mask layer.It is being formed After fin 201, the technique for removing mask layer is wet-etching technology or cineration technics.

The technique of the etching substrate is anisotropic dry etch process, and being formed by 201 side wall of fin can hang down Directly tilted in 200 surface of substrate or relative to 200 surface of substrate.In the present embodiment, the side wall of the fin 201 is opposite It is tilted in 200 surface of substrate, the top dimension for being formed by fin 201 is less than bottom size, 201 inclined side wall of the fin Be conducive to when being subsequently formed grid layer, the gate layer material of 201 sidewall surfaces of fin is performed etching, can ensure to be formed Grid layer pattern is good, accurate size, so that the performance for being formed by fin formula field effect transistor is stablized.

In the present embodiment, the groove that formation is etched in substrate is located in alumina layer, and the bottom of the groove is The alumina layer not being etched so that it is aluminium oxide to be formed by 200 surfacing of substrate.In another embodiment, institute is etched Alumina layer is stated, until exposing semiconductor layer surface, then the material for being formed by fin 201 is aluminium oxide, and is located at fin 200 material of substrate of 201 bottoms is semi-conducting material.

In another embodiment, the formation process of the fin 201 includes:Substrate is provided;It is formed in the substrate surface Mask layer, the mask layer covering need to form the corresponding region of fin 201;Using the mask layer as mask, the base is etched Bottom forms groove in the substrate;After etching the substrate, the mask layer is removed;Remove the mask layer it Afterwards, alumina layer, the substrate between adjacent trenches and oxygen are formed in the side wall and bottom surface of the substrate surface and groove Change aluminium layer and form fin 201, the substrate and alumina layer for being located at 201 bottom of the fin form substrate 200.

The substrate be monocrystalline substrate, single-crystal germanium substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator substrate or Germanium substrate on insulator.

Referring to FIG. 4, forming separation layer 202 on 200 surface of the substrate, the surface of the separation layer 202 is less than fin The material at 201 tops, and the side wall of 202 covering part fin 201 of the separation layer, the separation layer 202 is amorphous material.

The separation layer 202 is used for as the isolation structure between adjacent fin 201, and the grid layer being subsequently formed is located at institute State 202 surface of separation layer.

The material of the separation layer 202 is silica, silicon oxynitride, low-K dielectric material or ultralow K dielectric materials.It is described The formation process of separation layer 202 includes:Isolation film is formed in the substrate 200 and 201 surface of fin;Planarize the isolation Film, until the top surface for exposing fin 201;After flatening process, it is etched back to the isolation film, and expose The partial sidewall surface of the fin 201 forms separation layer 202.

The formation process of the isolation film is chemical vapor deposition method or physical gas-phase deposition;It is described planarization every Technique from film is CMP process;The technique for being etched back to isolation film is anisotropic dry etch process.

Be formed by separation layer 202 be amorphous state insulating materials, when subsequently with epitaxy technique in the separation layer 202 and fin 201 surface of portion formed channel layer when, due to 202 surface of the separation layer do not have neat lattice structure, be formed in every The lattice structure of the channel layer on 202 surface of absciss layer is mixed and disorderly;Since the material of the channel layer is topological insulating materials, when the ditch When the lattice structure of channel layer is mixed and disorderly, the metallic state of the channel layer surface is unstable, then is formed by the conduction of channel layer surface Ability is poor, to enable the channel layer for being formed in 202 surface of separation layer to be electrically isolated, makes between adjacent fin 201 It is electrically connected between channel layer, to inhibit the channel layer between adjacent fin 201 to generate leakage current, makes to be formed by fin field The performance of effect transistor is more stable.

Referring to FIG. 5, channel layer 203 is formed in the side wall and top surface of 202 surface of the separation layer and fin 201, The material of the channel layer 203 is topological insulating materials.

The topology insulating materials is the material that a kind of built-in electrical insulation, surface allow charge to move.Specifically, described to open up The electronic state flutterred inside insulating materials is the insulator for having energy gap, and the surface of the topological insulating materials is the gold of no energy gap Belong to state.Moreover, because the surface state of topological insulating materials is determined by the topological structure of the electronic state of material internal, it is exhausted with topology The concrete structure of edge material surface is unrelated, and therefore, the metallic state on the topology insulating materials surface is highly stable, not by impurity or The influence of surface texture variation.In addition, on the surface of topological insulating materials, the electronics moved toward one another is transported at different paths respectively It moves, interfere with each other, therefore energy consumption can be reduced.

In the present embodiment, the channel layer 203 is formed with the topological insulating materials, the gate dielectric layer being subsequently formed and Grid layer is located at the channel layer surface so that positioned at 201 surface of fin and positioned at the raceway groove for the grid layer bottom being subsequently formed Layer 203 can become the raceway groove of fin formula field effect transistor.Since the only surface of the channel layer 203 allows charge to move, and institute The built-in electrical insulation of channel layer 203 is stated, therefore, in the raceway groove formed by the channel layer 203, carrier only can be in channel layer 203 surface movement, so as to effectively inhibit the generation of short-channel effect, and can prevent the generation of leakage current, make The performance for being formed by fin formula field effect transistor improves.

The topology insulating materials includes Bi2Te3、Bi2Se3Or Sb2Te3;In the present embodiment, the topological insulating materials For Bi2Se3;The topology insulating materials is formed with epitaxy technique so that it is in crystalline state, with whole to be formed by topological insulating materials Neat lattice structure so that the surface for being formed by topological insulating materials is in good metallic state, inside in good insulation state.

In the present embodiment, the thickness of the channel layer 203 is 5 nanometers~50 nanometers;The formation work of the channel layer 203 Skill includes epitaxy technique twice, and the epitaxial deposition process twice is molecular beam epitaxial process.The epitaxy technique twice Including:First time epitaxy technique, the first time epitaxy technique have the first technological temperature;The first time epitaxy technique it Afterwards, second of epitaxy technique is carried out, second of epitaxy technique has the second technological temperature, and second technological temperature is high In first technological temperature.

In the epitaxy technique twice, first time epitaxy technique has the first technological temperature, and first process warm Spend relatively low, the first time epitaxy technique can be formed in the side wall and top surface on 202 surface of separation layer and fin 201 The topological insulating materials molecule of even distribution is as nucleating layer, and the nucleating layer has good gradient coating performance, therefore, It can make to be formed by nucleating layer and the close contact of the side wall and top surface of 202 surface of separation layer and fin 201, and It is flat to be formed by nucleation layer surface, be conducive to make subsequently to be formed by 203 surface of channel layer it is flat and with 201 surface of fin It is tightly combined.

There is second of epitaxy technique the second technological temperature, second technological temperature to be higher than the first technological temperature, Therefore the extension rate of second of epitaxy technique is very fast.In second of epitaxy technique, pass through intermolecular model moral Magnificent (Van der waals) power makes the molecule that molecular beam is provided be bonded with the molecule as core, to constitute The molecule for stating nucleating layer is core, is epitaxially-formed channel layer 203, and it is topological insulation material to be formed by 203 material of channel layer Material, and the topological insulating materials is crystalline material.Second of epitaxy technique can form the higher topology insulation of quality Material so that the lattice structure marshalling of topological insulating materials is formed by, to make to be formed by the surface of channel layer 203 Can be in good metallic state, and internal is in good insulation state, can make to be formed by 203 performance of channel layer more preferably.

In the present embodiment, the fin 201 etches to be formed by the alumina layer to crystalline state, and the alumina layer table Face is (0001) crystal face, therefore the oxidation aluminium surface of 201 top surface of the fin has (0001) crystal face, in the crystalline state Alumina material surface forms topological insulating materials by molecular beam epitaxial process, can make to be formed by topological insulating materials With good gradient coating performance, and be conducive to make to be formed by topological insulating materials internal crystal framework marshalling, density It is uniform with thickness, to enable the side wall for being formed by channel layer 203 and fin 201 and top surface to combine closely, and The channel layer 203 on 201 surface of be formed in fin has stable metallic state surface and the inside for the state that insulate.To be formed Channel layer 203 formed raceway groove when, leakage current can be effectively inhibited, the generation of short-channel effect, raising is prevented to be formed by The performance of fin formula field effect transistor.

In the present embodiment, the technological parameter of the first time epitaxy technique includes:Temperature is taken the photograph for 100 degrees Celsius~150 Family name's degree, air pressure are 1E-10 millibars;The technological parameter of second of epitaxy technique includes:Temperature is taken the photograph for 250 degrees Celsius~400 Family name's degree, air pressure are 1E-10 millibars.

The channel layer 203 is formed using epitaxy technique, and the epitaxy technique is in the material of the surface formation in crystalline state Lattice structure is more neat, and more mixed and disorderly in the material lattice structure that amorphous surface is formed.Due to 203 shape of the channel layer It is amorphous state material at the material in the side wall and top surface on 202 surface of separation layer and fin 201, the separation layer 202 Material, therefore, 203 lattice structure of channel layer for being formed in 202 surface of separation layer is mixed and disorderly, 203 table of channel layer on 202 surface of separation layer The metallic state in face is poor, and therefore, the 203 surface conductance ability of channel layer being formed on separation layer 202 is poor;And the fin The material on 201 surfaces is crystalline material, and therefore, 203 lattice structure of channel layer for being formed in 201 side wall of fin and top surface is whole Together, make 203 surface of channel layer of 201 side wall of fin and top surface that there is good metallic state, the channel layer on fin 201 203 surfaces have good conductive capability.Channel layer 203 due to being formed in 201 surface of fin is used to form fin field effect The raceway groove of transistor, therefore, the good conductive ability of the channel layer 203 on fin 201 can make the raceway groove of the transistor It can be more stable;And the channel layer 203 on 202 surface of separation layer makes the transistor formed on adjacent fin 201 without being electrically connected Between independently of each other, therefore, when the conductive capability on 203 surface of channel layer on separation layer 202 is poor, adjacent fin can be prevented It leaks electricity between channel layer 203 between 201.Therefore, it is possible to make to be formed by the performance of fin formula field effect transistor more Stablize.

Referring to FIG. 6, forming gate dielectric layer 204 on 203 surface of the channel layer.

The gate dielectric layer 204 is used for as the gate medium for being formed by fin formula field effect transistor.In the present embodiment, The material of the gate dielectric layer 204 includes high K dielectric material, and it is high-K metal gate (High-k to be formed by transistor grid structure Metal Gate, abbreviation HKMG) structure, the technique for forming the gate structure is rear grid (Gate Last) technique.

The high K dielectric material includes:Aluminium oxide, hafnium oxide, hafnium silicon oxide, nitrogen oxidation hafnium silicon, lanthana, lanthana Aluminium, zirconium oxide, zirconium silicon oxide, nitrogen oxidation zirconium silicon, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, oxidation One or more combinations in yttrium, lead oxide scandium tantalum, lead niobate zinc.

The material of the gate dielectric layer 204 is aluminium oxide, and the thickness of the gate dielectric layer 204 is 5 nanometers~50 nanometers, grid The formation process of dielectric layer 204 is atomic layer deposition (Atom Layer Deposition, abbreviation ALD), forms the gate medium Layer 204 technological parameter include:Temperature is 150 degrees Celsius~250 degrees Celsius, and presoma includes trimethyl aluminium (TMA), Yi Jishui (H2) or ozone (O O3), the burst length of the trimethyl aluminium is 0.5 second~1 second, and the burst length of water is 1 second~1.5 seconds, smelly The burst length of oxygen is 0.8 second~1.2 seconds;In addition, further including being purged using purge gas in technique, it is passed through each time After presoma, the time that purge gas is passed through is 5 to 10 seconds.

In one embodiment, the thickness of the gate dielectric layer 204 is 10 nanometers, and the atom layer deposition process includes:Temperature Degree is 200 degrees Celsius, and presoma is trimethyl aluminium (TMA) and water (H2) or trimethyl aluminium and ozone (O O3);Precursor is three When aluminium methyl and water, the burst length of the trimethyl aluminium is 0.8 second, and the burst length of water is 1.2 seconds;Precursor is front three When base aluminium and ozone, the burst length of the trimethyl aluminium is 1 second, and the burst length of ozone is 1 second;Purge gas is nitrogen, After being passed through presoma each time, the time of nitrogen being passed through is 6 seconds.

Density and alumina layer in homogeneous thickness can be formed on topological insulating materials surface using atom layer deposition process, Keep the quality for being formed by gate dielectric layer 204 good.Moreover, being formed on topological insulating materials surface using atom layer deposition process Alumina layer can make to be formed by alumina layer with good gradient coating performance, be situated between so as to make to be formed by grid Be well combined between matter layer 204 and the surface of channel layer 203, can be effectively prevented gate dielectric layer 204 and channel layer 203 it Between leakage current is generated because of defect, the performance for making to be formed by fin formula field effect transistor is stablized.

In one embodiment, the material of the gate dielectric layer 204 further includes one in silica, silicon nitride, silicon oxynitride Kind is a variety of.When one or more in the silica, silicon nitride, silicon oxynitride are formed in gate dielectric layer 204 and channel layer When between 203, the binding ability between high K dielectric material and channel layer 203 can be enhanced.

In another embodiment, the material of the gate medium 204 be silica, silicon nitride, one kind in silicon oxynitride or A variety of, then what is be subsequently formed can be as the grid of transistor by the grid layer of material of polysilicon.

Fig. 7 and Fig. 8 are please referred to, Fig. 8 is cross-sectional views of the Fig. 7 along the directions BB ', in 204 table of the gate dielectric layer Face is developed across the grid layer 205 of the fin 201.

In the present embodiment, the material of the grid layer 205 is polysilicon, and it is high K to be formed by transistor grid structure Metal-gate structures, therefore the grid layer 205 is dummy gate layer, the grid to be subsequently formed takes up space position, subsequently with gold The grid for belonging to material substitutes the grid layer 205, to form gate structure.

In another embodiment, the material of the gate dielectric layer 204 is one kind in silica, silicon nitride, silicon oxynitride Or it is a variety of, the material of the grid layer 205 is polysilicon, and the grid layer 205 is the required fin formula field effect transistor formed Grid.

The formation process of the grid layer 205 includes:Gate electrode film is formed in separation layer 202 and 204 surface of gate dielectric layer; The grid film surface forms mask layer, and the figure of the mask layer runs through the fin 201;Using the mask layer as mask, The gate electrode film is etched, until exposing 204 surface of 202 surface of separation layer and gate dielectric layer, forms grid layer 205; After etching the gate electrode film, the mask layer is removed.

The material of the mask layer can be photoresist, silicon nitride, silicon oxynitride or amorphous carbon;Etch the gate electrode film Technique be anisotropic dry etch process;The technique for removing the mask layer is wet-etching technology or cineration technics.

Referring to FIG. 9, after forming the grid layer 205, the 201 surface shape of fin in 205 both sides of the grid layer At source region 206a and drain region 206b.

It should be noted that the direction of described Fig. 9 is consistent with profile direction shown in Fig. 8.

In the present embodiment, before forming the source region 206a and drain region 206b, further include:In 205 liang of the grid layer 204 surface of gate dielectric layer of side and 202 surface of separation layer form side wall 207.The side wall 207 is for reducing source region 206a and leakage Overlapping area between area 206b and grid layer 205 reduces parasitic capacitance with this.

The material of the side wall 207 is one or more combinations in silica, silicon nitride, silicon oxynitride;The side wall 207 formation process includes:Side wall film is formed in the grid layer 205 and 204 surface of gate dielectric layer;The side wall film is carried out It is etched back to, until exposing 204 surface of gate dielectric layer.The formation process of the side wall film is chemical vapor deposition method or physics Gas-phase deposition;The technique that is etched back to is anisotropic dry etch process.

The formation process of the source region 206a and drain region 206b includes:After forming the side wall 207, in the grid Groove is formed in layer 205 and the gate dielectric layer 204 and channel layer 203 of 207 both sides of side wall, the groove exposes part fin 201 top and sidewall surfaces, and the groove extends to 202 surface of the separation layer;Source and drain is formed in the groove The material of layer, the source-drain layer is semi-conducting material.

The formation process of the groove includes:Mask layer, the mask layer exposure are formed on 204 surface of the gate dielectric layer Go out 204 surface of part gate dielectric layer of the grid layer 205, side wall 207 and grid layer 205 and 207 both sides of side wall, it is described The gate dielectric layer 204 exposed is located higher than 201 side wall of fin and top surface of separation layer 202;It is to cover with the mask layer Film etches the gate dielectric layer 204 and channel layer 202 using isotropic etching technics, until exposing the side of fin 201 Until wall and top surface, groove is formed.

The material of the source-drain layer is semi-conducting material, and formation process is selective epitaxial depositing operation.In the present embodiment In, the material of the source-drain layer is silicon, due to the alumina material that the material of the fin 201 is crystalline state, the fin 201 The lattice structure of side wall and bottom surface is neat, therefore, it is possible to 201 surface of fin exposed in the bottom portion of groove, with choosing Selecting property epitaxial deposition process forms silicon materials;Moreover, because 204 surface of gate dielectric layer of the groove vicinity is covered by mask layer Lid, therefore, the selective epitaxial depositing operation will not form source-drain layer in the mask layer surface, so as to only described The source-drain layer is formed in groove.

After forming the source-drain layer, with ion implantation technology in the source-drain layer doped N-type ion or p-type from Son, to form source region 206a and drain region 206b;After forming the source region 206a and drain region 206b, the mask is removed Layer.In the present embodiment, doped N-type ion in source region 206a and drain region 206b, then be formed by fin formula field effect transistor Carrier is electronics, can improve the working efficiency for being formed by transistor.

In another embodiment, additionally it is possible in the selective epitaxial depositing operation for forming source-drain layer, using doping in situ Technique doped N-type ion or p-type ion, to form source region 206a and drain region 206b.

In the present embodiment, after forming the source region 206a and drain region 206b, further include:In the gate dielectric layer 204 surfaces form dielectric layer, and the surface of the dielectric layer is flushed with the surface of the grid layer 205;Remove the grid layer 205, opening is formed in the dielectric layer;Grid is formed in the opening.

The material of the grid includes metal, the metal be tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminium, lead, platinum, tin, silver, It is one or more in gold;In the metal material of the grid, additionally it is possible to the Doped ions with other metals, for adjusting Threshold voltage.Moreover, the material of the grid further includes metallic compound, the metallic compound is titanium nitride, tantalum nitride, silicon It is one or more in change tungsten, tungsten nitride, ruthenium-oxide, cobalt silicide, nickle silicide, for adjusting the threshold value electricity for being formed by transistor Pressure.In addition, the material of the grid is carbon nano-tube material or conductive carbon material.

When the present embodiment is formed by fin formula field effect transistor work, the semiconductor layer of alumina layer bottom is made to connect Ground, the bottom grid as transistor;Apply source bias V in the source region 206aS;It is inclined to apply drain electrode in the drain region 206b Press VD;Apply grid bias V in the gridG, the top grid as transistor.By controlling the grid bias VG, can Control electronics from gate bottom, 203 surface of channel layer that is in contact with gate dielectric layer 204 pass through, to make positioned at the grid Pole bottom, 203 surface of channel layer that is in contact with gate dielectric layer 204 become the raceway groove of transistor;And by controlling the source Pole bias VSWith drain bias VDBetween difference, flowing of the electronics on 203 surface of channel layer can be controlled, to drive crystal Pipe works.Since the only surface of the channel layer 203 is in metallic state, and it is internal in insulation state so that and electronics is all in channel layer 203 Surface is moved, and to restrained effectively the generation of short-channel effect and leakage current, improves the performance of transistor.

In the present embodiment, channel layer is formed in separation layer and fin portion surface, and the channel layer is used to form fin field effect Answer the channel region of transistor.The material of the channel layer is topological insulating materials, and the surface of the topology insulating materials is incompetent The metallic state of band gap, can be conductive, and the inside of the topological insulating materials is the insulator for having band gap, therefore, with It, can be using the surface that the channel layer is in contact with gate dielectric layer as allowing to carry when the topology insulating materials forms channel layer The transistor channel of stream migration, moreover, because the topology insulating materials only allows carrier in surface migration, therefore, institute The thickness for stating transistor channel is very thin, and the generation that can be effectively inhibited short-channel effect, prevent leakage current ensure that be formed Fin formula field effect transistor performance it is more stable.Moreover, the conductive capability on the topology insulating materials surface is not by surface The influence of concrete structure pattern, also not by impurity effect, therefore, the conductive capability of the channel layer is stablized, and is conducive to make institute's shape At fin formula field effect transistor property retention stablize.

Further, since the material of the fin portion surface is crystalline material, therefore in the side wall and top surface of the fin The channel layer of formation can also have good crystalline structure so that it is in good metallic state to be formed by channel layer surface, then Stablize positioned at the side wall of fin and the channel layer surface conductive capability of top surface.Since the separation layer is amorphous material, So that the crystal lattice state for being formed in the channel layer of the insulation surface is mixed and disorderly, that causes insulation surface channel layer surface can not Good metallic state is formed, then the channel layer conductive capability of insulation surface is poor.Since the channel layer of the fin portion surface is used In the channel region for forming transistor, and the channel layer of insulation surface is needed with the ability being electrically isolated, therefore in the isolation Layer and fin portion surface form channel layer, can ensure the performance for being formed by channel region, and can ensure between adjacent fin Channel layer can be electrically isolated.It leaks electricity between fin formula field effect transistor therefore, it is possible to avoid being formed by, ensures institute's shape At fin formula field effect transistor performance stablize.

Correspondingly, the embodiment of the present invention also provides a kind of fin formula field effect transistor formed using the above method, please after Continuous reference chart 7 and Fig. 9, including:Substrate 200,200 surface of the substrate have fin 201, the material on 201 surface of the fin For crystalline material;The surface of separation layer 202 positioned at 200 surface of the substrate, the separation layer 202 is less than 201 top of fin, And the side wall of the 202 covering part fin 201 of separation layer, the separation layer 202 are amorphous material;Positioned at the separation layer The material of the channel layer 203 of the side wall and top surface of 202 surfaces and fin 201, the channel layer 203 is topological insulation material Material;Gate dielectric layer 204 positioned at 203 surface of the channel layer;Grid layer 205 positioned at 204 surface of the gate dielectric layer, it is described Grid layer 205 is across the fin 201.

The topology insulating materials is Bi2Te3、Bi2Se3Or Sb2Te3, the thickness of the channel layer 203 is 5 nanometers~50 Nanometer.

The material on 201 surface of the fin is aluminium oxide, silicon or silica.In the present embodiment, the substrate 200 and fin The material on 201 surface of portion is aluminium oxide, and the aluminium oxide of 201 top surface of the fin has (0001) crystal face.

The material of the gate dielectric layer 204 includes high K dielectric material;The high K dielectric material includes:Aluminium oxide, oxidation Hafnium, hafnium silicon oxide, nitrogen oxidation hafnium silicon, lanthana, lanthana aluminium, zirconium oxide, zirconium silicon oxide, nitrogen oxidation zirconium silicon, tantalum oxide, oxidation One or more combinations in titanium, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yttrium oxide, lead oxide scandium tantalum, lead niobate zinc. In one embodiment, the material of the gate dielectric layer 204 further includes one or more in silica, silicon nitride, silicon oxynitride. In another embodiment, the material of the gate dielectric layer 204 is one or more in silica, silicon nitride, silicon oxynitride.

The grid layer 205 is the grid of the transistor.In the present embodiment, the material of the grid layer 205 is gold Belong to.In another embodiment, the material of the grid layer 205 is polysilicon.In addition, the material of the grid layer 205 can also For carbon nano-tube material or conductive carbon material.

In the present embodiment, the fin formula field effect transistor further includes:Medium positioned at 204 surface of the gate dielectric layer Layer (not shown), the surface of the dielectric layer is flushed with the surface of the grid layer 205.

In the present embodiment, the material of the grid layer 205 includes metal, the metal be tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, It is one or more in copper, aluminium, lead, platinum, tin, silver, gold;It can also be with the Doped ions of other metals in the metal;And And when the material of the grid layer 205 includes metal, the material of the grid layer 205 can also include metallic compound, institute It is one or more in titanium nitride, tantalum nitride, tungsten silicide, tungsten nitride, ruthenium-oxide, cobalt silicide, nickle silicide to state metallic compound.

In the present embodiment, the fin formula field effect transistor further includes the gate dielectric layer positioned at 205 both sides of the grid layer The side wall 207 on 202 surface of 204 surfaces and separation layer;The material of the side wall 207 is in silica, silicon nitride, silicon oxynitride One or more combinations.

In the present embodiment, the fin formula field effect transistor further includes the fin positioned at 207 both sides of the grid layer and side wall The source region 206a and drain region 206b on 201 surface of portion.

In the present embodiment, the side wall and top surface of the substrate surface and fin have channel layer, the separation layer position In the channel layer surface on substrate, grid layer is located at the separation layer and gate dielectric layer surface, and is developed across the fin Grid layer.The channel layer is used to form the raceway groove of fin formula field effect transistor, and the material of the channel layer is topological insulation material The surface of material, the topology insulating materials is the metallic state of no band gap, can be conductive, and the topological insulating materials is interior Portion is the insulator for having band gap, therefore, it is possible to using the surface that the channel layer is in contact with gate dielectric layer as allowing to carry The transistor channel of stream migration makes the crystalline substance moreover, because the topology insulating materials only allows carrier in surface migration The thickness in body pipe trench road is very thin, so as to the generation for effectively inhibiting short-channel effect, preventing leakage current, ensure that be formed Fin formula field effect transistor performance it is more stable.Moreover, the conductive capability on the topology insulating materials surface is not by surface The influence of concrete structure pattern, also not by impurity effect, therefore, the conductive capability of the channel layer is stablized, and is conducive to make institute's shape At fin formula field effect transistor property retention stablize.

Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims (20)

1. a kind of forming method of fin formula field effect transistor, which is characterized in that
Substrate is provided, the substrate surface has fin, and the material of the fin portion surface is crystalline material;
Separation layer is formed in the substrate surface, the surface of the separation layer is less than at the top of fin, and the separation layer covering part Divide the side wall of fin, the material of the separation layer is amorphous material;
Channel layer is formed in the side wall and top surface of the insulation surface and fin, the material of the channel layer is that topology is exhausted Edge material;
Gate dielectric layer is formed in the channel layer surface;
It is developed across the grid layer of the fin on the gate dielectric layer surface.
2. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that the topology insulating materials For Bi2Te3、Bi2Se3Or Sb2Te3
3. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that the formation of the channel layer Technique includes epitaxy technique twice.
4. the forming method of fin formula field effect transistor as claimed in claim 3, which is characterized in that the epitaxy technique twice It is molecular beam epitaxial process.
5. the forming method of fin formula field effect transistor as claimed in claim 3, which is characterized in that the epitaxy technique twice Including:First time epitaxy technique, the first time epitaxy technique have the first technological temperature;The first time epitaxy technique it Afterwards, second of epitaxy technique is carried out, second of epitaxy technique has the second technological temperature, and second technological temperature is high In first technological temperature.
6. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that the material of the fin portion surface Material is aluminium oxide, silicon or silica.
7. the forming method of fin formula field effect transistor as claimed in claim 6, which is characterized in that the material of the fin portion surface Material is aluminium oxide, and the aluminium oxide of the fin top surface has (0001) crystal face.
8. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that the material of the gate dielectric layer Material includes high K dielectric material.
9. the forming method of fin formula field effect transistor as claimed in claim 8, which is characterized in that the high K dielectric material Including:Aluminium oxide, hafnium oxide, hafnium silicon oxide, nitrogen oxidation hafnium silicon, lanthana, lanthana aluminium, zirconium oxide, zirconium silicon oxide, nitrogen oxidation In zirconium silicon, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yttrium oxide, lead oxide scandium tantalum, lead niobate zinc One or more combinations.
10. the forming method of fin formula field effect transistor as claimed in claim 8, which is characterized in that the gate dielectric layer Material further includes one or more in silica, silicon nitride, silicon oxynitride.
11. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that the material of the grid layer Material is polysilicon.
12. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that further include:In the grid Dielectric layer surface forms dielectric layer, and the surface of the dielectric layer is flushed with the surface of the grid layer;The grid layer is removed, Opening is formed in the dielectric layer;Grid is formed in the opening.
13. the forming method of fin formula field effect transistor as claimed in claim 12, which is characterized in that the material of the grid Including metal, the metal is one or more in tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminium, lead, platinum, tin, silver, gold.
14. the forming method of fin formula field effect transistor as claimed in claim 13, which is characterized in that the material of the grid Further include metallic compound, the metallic compound is titanium nitride, tantalum nitride, tungsten silicide, tungsten nitride, ruthenium-oxide, cobalt silicide, silicon Change one or more in nickel.
15. the forming method of fin formula field effect transistor as claimed in claim 12, which is characterized in that the material of the grid For carbon nano-tube material or conductive carbon material.
16. the forming method of fin formula field effect transistor as claimed in claim 12, which is characterized in that have in the grid Doped ions.
17. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that the formation of the fin Technique includes:Substrate is provided;Mask layer is formed in the substrate surface, the mask layer covering needs to form the correspondence area of fin Domain;Using the mask layer as mask, the substrate is etched, forms groove in the substrate, the substrate shape between adjacent trenches At fin, the substrate for being located at the fin bottom forms substrate;After etching the substrate, the mask layer is removed.
18. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that the material of the separation layer Material is silica;The formation process of the separation layer includes:Isolation film is formed in the substrate and fin portion surface;Described in planarization Isolation film, until exposing the top surface of fin;After flatening process, it is etched back to the isolation film, and exposure Go out the partial sidewall surface of the fin, forms separation layer.
19. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that further include:Forming institute After stating grid layer, the fin portion surface in the grid layer both sides forms source region and drain region.
20. a kind of being formed by fin formula field effect transistor using such as any one of claim 1 to 19 method, which is characterized in that Including:
Substrate, the substrate surface have fin, and the material of the fin portion surface is crystalline material;
Positioned at the separation layer of the substrate surface, the surface of the separation layer is less than at the top of fin, and the separation layer covering part It is amorphous material to divide the side wall of fin, the separation layer;
Positioned at the channel layer of the side wall and top surface of the insulation surface and fin, the material of the channel layer is that topology is exhausted Edge material;
Positioned at the gate dielectric layer of the channel layer surface;
Grid layer positioned at the gate dielectric layer surface, the grid layer is across the fin.
CN201410505413.5A 2014-09-26 2014-09-26 Fin formula field effect transistor and forming method thereof CN105514162B (en)

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CN103227200A (en) * 2012-01-31 2013-07-31 台湾积体电路制造股份有限公司 Finfet and method of fabricating the same
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