CN103617948A - Doping method of MOS device - Google Patents
Doping method of MOS device Download PDFInfo
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- CN103617948A CN103617948A CN201310500173.5A CN201310500173A CN103617948A CN 103617948 A CN103617948 A CN 103617948A CN 201310500173 A CN201310500173 A CN 201310500173A CN 103617948 A CN103617948 A CN 103617948A
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- diffusion
- silicon chip
- oxide layer
- mixed liquor
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000009792 diffusion process Methods 0.000 claims abstract description 102
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 70
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 70
- 239000010703 silicon Substances 0.000 claims abstract description 70
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 16
- 239000001301 oxygen Substances 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- 229910052796 boron Inorganic materials 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 19
- 239000004816 latex Substances 0.000 claims description 17
- 229920000126 latex Polymers 0.000 claims description 17
- 238000003756 stirring Methods 0.000 claims description 10
- 238000001816 cooling Methods 0.000 claims description 5
- 239000000428 dust Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000003960 organic solvent Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
The invention discloses a doping method of an MOS device. The method comprises the following steps: step one, a silicon wafer is placed in a diffusion furnace for first heat diffusion; step two, oxygen is injected into the diffusion furnace, so as to form a thin oxide layer on the surface of the silicon wafer; and step three, the surface of the thin oxide layer of the silicon wafer is coated by mixed liquor, and then second heat diffusion doping is carried out.
Description
Technical field
The present invention relates to technical field of semiconductors, especially relate to a kind of doping method of MOS device.
Background technology
The doping process of the impurity of existing MOS device is height and the inhomogeneity key technology that determines the parameter of device.Doping method to MOS device mainly contains: boron or phosphorus plasma method for implanting and the method for utilizing latex source or gaseous source in High temperature diffusion.For ion injection method, its speed that adulterates, precision is controlled good, but implantation membership causes lattice defect, thus affect the performance of MOS device.For direct by latex source or gaseous source when the method for High temperature diffusion is mixed impurity at the high boron square resistance of needs, dense due to impurity source, thus precision is very poor.So the semiconductor device parameter consistency of making is very poor: as conducting resistance, puncture voltage, multiplication factor etc.
Along with constantly reducing of MOS device feature size (gate length), for suppressing short-channel effect, the doping content of tagma (channel region) must improve constantly.But improving constantly of doping content can cause carrier mobility reduction, subthreshold characteristic variation and threshold voltage to be difficult to the problems such as reduction.Oxide layer in traditional MOS device manufacturing processes is used for isolating the impurity such as boron, phosphorus and enters.This requires the thickness of oxide layer enough thick.If the thickness low LCL of oxide layer, the impurity such as boron, phosphorus will diffuse into so.Therefore, for MOS device, in the urgent need to a kind of technology of mixing concentration that can accurately control impurity.
Summary of the invention
The doping method that the object of this invention is to provide a kind of MOS device.To solve the existing problem of prior art.
For solving the problems of the technologies described above, when adulterate in the doped region of the MOS device that the present invention proposes, in turn include the following steps:
Step 1, inserts silicon chip in diffusion furnace, to carry out thermal diffusion for the first time;
Step 2 passes into oxygen in above-mentioned diffusion furnace, thereby forms thin oxide layer at silicon chip surface;
Step 3, at the thin oxide layer surface-coated mixed liquor of silicon chip, then carries out the doping of thermal diffusion for the second time.
Wherein, in step 1, first adopt photoresist on silicon chip, to define non-doped region, thereby the surface of exposing non-doped region then forms silicon nitride layer on the surface of non-doped region, the Main Function of described silicon nitride layer is as impurity barrier layer, therefore its thickness is enough thick, to prevent that impurity from entering non-doped region, in the present invention, the thickness of silicon nitride layer is about 100-200 micron.Then silicon chip is inserted in diffusion furnace, carry out thermal diffusion for the first time after the oxygen in emptying diffusion furnace, diffusion concentration is about 5 * 10
-14cm
-3to 1 * 10
-15cm
-3, diffusion temperature is about 1100-1200 degree Celsius, is about 2-3 hour diffusion time;
Wherein, in step 2, in the diffusion furnace of completing steps one, pass into oxygen, thereby form oxide layer on the doped region surface of silicon chip, diffusion furnace temperature is about 700-800 degree Celsius, and the thickness that forms oxide layer is about 100-150 dust;
Wherein, in step 3, will form the silicon chip extracting of oxide layer, form the surface-coated mixed liquor of oxide layer at silicon chip, described mixed liquor adds photoresist to form in boron latex source, and the ratio of boron latex source and photoresist is about (weight ratio): 10:3~6 gram; The concrete mixed process of mixed liquor is: boron latex source and photoresist are mixed, then put into stirring vessel and stir fully, mixing time is about 2.5~3.5 hours.After this mixed liquor obtaining is coated on the oxide layer surface of silicon chip to form mixed liquor coat, coat thickness is about 300-400 micron; The silicon chip that applies mixed liquor is toasted, and baking temperature is about 140-160 degree Celsius, and baking time is about 20~25 minutes, and the main purpose of baking is that the organic solvent in described coat is brought into play completely; By the silicon chip extracting after baking, again put into the thermal diffusion for the second time that diffusion furnace carries out impurity, diffusion temperature is controlled at and is about 1150-1250 degree Celsius, is controlled at diffusion time and is about 2.5~3.5 hours, and diffusion concentration is about 5 * 10
-15cm
-3to 5 * 10
-16cm
-3; After diffusion, then by diffusion furnace cooling, until while reaching room temperature by silicon chip extracting, through removing after the silicon nitride layer of silicon chip surface, the doping that completes MOS device doped region is made.
The present invention is by diffuseing to form for the first time light doping section at silicon chip, and then the doped region surface oxidation on silicon chip generates silicon dioxide oxide layer, by silicon dioxide layer, control the concentration of diffusion impurity, thereby can accurately control the needed doping content in MOS device doped region.
Embodiment
Embodiment 1
When adulterate in the doped region of the MOS device that the present invention proposes, in turn include the following steps:
Step 1, inserts silicon chip in diffusion furnace, to carry out thermal diffusion for the first time;
Step 2 passes into oxygen in above-mentioned diffusion furnace, thereby forms thin oxide layer at silicon chip surface;
Step 3, at the thin oxide layer surface-coated mixed liquor of silicon chip, then carries out the doping of thermal diffusion for the second time.
Wherein, in step 1, first adopt photoresist on silicon chip, to define non-doped region, thereby the surface of exposing non-doped region then forms silicon nitride layer on the surface of non-doped region, the Main Function of described silicon nitride layer is as impurity barrier layer, therefore its thickness is enough thick, to prevent that impurity from entering non-doped region, in the present invention, the thickness of silicon nitride layer is about 100 microns.Then silicon chip is inserted in diffusion furnace, carry out thermal diffusion for the first time after the oxygen in emptying diffusion furnace, diffusion concentration is about 5 * 10
-14cm
-3, diffusion temperature is about 1100 degrees Celsius, is about 2 hours diffusion time;
Wherein, in step 2, in the diffusion furnace of completing steps one, pass into oxygen, thereby form oxide layer on the doped region surface of silicon chip, diffusion furnace temperature is about 700 degrees Celsius, and the thickness that forms oxide layer is about 100 dusts;
Wherein, in step 3, will form the silicon chip extracting of oxide layer, form the surface-coated mixed liquor of oxide layer at silicon chip, described mixed liquor adds photoresist to form in boron latex source, and the ratio of boron latex source and photoresist is about (weight ratio): 10:3 gram; The concrete mixed process of mixed liquor is: boron latex source and photoresist are mixed, then put into stirring vessel and stir fully, mixing time is about 3 hours.After this mixed liquor obtaining is coated on the oxide layer surface of silicon chip to form mixed liquor coat, coat thickness is about 300 microns; The silicon chip that applies mixed liquor is toasted, and baking temperature is about 140 degrees Celsius, and baking time is about 20 minutes, and the main purpose of baking is that the organic solvent in described coat is brought into play completely; By the silicon chip extracting after baking, again put into the thermal diffusion for the second time that diffusion furnace carries out impurity, diffusion temperature is controlled at and is about 1150 degrees Celsius, is controlled at diffusion time and is about 3 hours, and diffusion concentration is about 5 * 10
-15cm
-3; After diffusion, then by diffusion furnace cooling, until while reaching room temperature by silicon chip extracting, through removing after the silicon nitride layer of silicon chip surface, the doping that completes MOS device doped region is made.
Embodiment 2
When adulterate in the doped region of the MOS device that the present invention proposes, in turn include the following steps:
Step 1, inserts silicon chip in diffusion furnace, to carry out thermal diffusion for the first time;
Step 2 passes into oxygen in above-mentioned diffusion furnace, thereby forms thin oxide layer at silicon chip surface;
Step 3, at the thin oxide layer surface-coated mixed liquor of silicon chip, then carries out the doping of thermal diffusion for the second time.
Wherein, in step 1, first adopt photoresist on silicon chip, to define non-doped region, thereby the surface of exposing non-doped region then forms silicon nitride layer on the surface of non-doped region, the Main Function of described silicon nitride layer is as impurity barrier layer, therefore its thickness is enough thick, to prevent that impurity from entering non-doped region, in the present invention, the thickness of silicon nitride layer is about 200 microns.Then silicon chip is inserted in diffusion furnace, carry out thermal diffusion for the first time after the oxygen in emptying diffusion furnace, diffusion concentration is about 1 * 10
-15cm
-3, diffusion temperature is about 1200 degrees Celsius, is about 3 hours diffusion time;
Wherein, in step 2, in the diffusion furnace of completing steps one, pass into oxygen, thereby form oxide layer on the doped region surface of silicon chip, diffusion furnace temperature is about 800 degrees Celsius, and the thickness that forms oxide layer is about 150 dusts;
Wherein, in step 3, will form the silicon chip extracting of oxide layer, form the surface-coated mixed liquor of oxide layer at silicon chip, described mixed liquor adds photoresist to form in boron latex source, and the ratio of boron latex source and photoresist is about (weight ratio): 10:6 gram; The concrete mixed process of mixed liquor is: boron latex source and photoresist are mixed, then put into stirring vessel and stir fully, mixing time is about 3.5 hours.After this mixed liquor obtaining is coated on the oxide layer surface of silicon chip to form mixed liquor coat, coat thickness is about 400 microns; The silicon chip that applies mixed liquor is toasted, and baking temperature is about 160 degrees Celsius, and baking time is about 25 minutes, and the main purpose of baking is that the organic solvent in described coat is brought into play completely; By the silicon chip extracting after baking, again put into the thermal diffusion for the second time that diffusion furnace carries out impurity, diffusion temperature is controlled at and is about 1250 degrees Celsius, is controlled at diffusion time and is about 3.5 hours, and diffusion concentration is about 5 * 10
-16cm
-3; After diffusion, then by diffusion furnace cooling, until while reaching room temperature by silicon chip extracting, through removing after the silicon nitride layer of silicon chip surface, the doping that completes MOS device doped region is made.
Embodiment 3
When adulterate in the doped region of the MOS device that the present invention proposes, in turn include the following steps:
Step 1, inserts silicon chip in diffusion furnace, to carry out thermal diffusion for the first time;
Step 2 passes into oxygen in above-mentioned diffusion furnace, thereby forms thin oxide layer at silicon chip surface;
Step 3, at the thin oxide layer surface-coated mixed liquor of silicon chip, then carries out the doping of thermal diffusion for the second time.
Wherein, in step 1, first adopt photoresist on silicon chip, to define non-doped region, thereby the surface of exposing non-doped region then forms silicon nitride layer on the surface of non-doped region, the Main Function of described silicon nitride layer is as impurity barrier layer, therefore its thickness is enough thick, to prevent that impurity from entering non-doped region, in the present invention, the thickness of silicon nitride layer is about 160 microns.Then silicon chip is inserted in diffusion furnace, carry out thermal diffusion for the first time after the oxygen in emptying diffusion furnace, diffusion concentration is about 8 * 10
-15cm
-3, diffusion temperature is about 1150 degrees Celsius, is about 2.5 hours diffusion time;
Wherein, in step 2, in the diffusion furnace of completing steps one, pass into oxygen, thereby form oxide layer on the doped region surface of silicon chip, diffusion furnace temperature is about 750 degrees Celsius, and the thickness that forms oxide layer is about 130 dusts;
Wherein, in step 3, will form the silicon chip extracting of oxide layer, form the surface-coated mixed liquor of oxide layer at silicon chip, described mixed liquor adds photoresist to form in boron latex source, and the ratio of boron latex source and photoresist is about (weight ratio): 10:5 gram; The concrete mixed process of mixed liquor is: boron latex source and photoresist are mixed, then put into stirring vessel and stir fully, mixing time is about 3 hours.After this mixed liquor obtaining is coated on the oxide layer surface of silicon chip to form mixed liquor coat, coat thickness is about 360 microns; The silicon chip that applies mixed liquor is toasted, and baking temperature is about 150 degrees Celsius, and baking time is about 25 minutes, and the main purpose of baking is that the organic solvent in described coat is brought into play completely; By the silicon chip extracting after baking, again put into the thermal diffusion for the second time that diffusion furnace carries out impurity, diffusion temperature is controlled at and is about 1200 degrees Celsius, is controlled at diffusion time and is about 3 hours, and diffusion concentration is about 1 * 10
-16cm
-3; After diffusion, then by diffusion furnace cooling, until while reaching room temperature by silicon chip extracting, through removing after the silicon nitride layer of silicon chip surface, the doping that completes MOS device doped region is made.
So far the present invention has been done to detailed explanation, but the embodiment of description above the preferred embodiments of the present invention just only, it is not intended to limit the present invention.Those skilled in the art can make any modification to the present invention, and protection scope of the present invention is limited to the appended claims.
Claims (2)
1. a doping method for MOS device, described method in turn includes the following steps:
Step 1, inserts silicon chip in diffusion furnace, to carry out thermal diffusion for the first time;
Step 2 passes into oxygen in above-mentioned diffusion furnace, thereby forms thin oxide layer at silicon chip surface;
Step 3, at the thin oxide layer surface-coated mixed liquor of silicon chip, then carries out the doping of thermal diffusion for the second time.
2. the method for claim 1, is characterized in that:
Wherein, in step 1, first adopt photoresist on silicon chip, to define non-doped region, thereby expose the surface of non-doped region, then on the surface of non-doped region, form silicon nitride layer, the thickness of silicon nitride layer is about 100-200 micron; Then silicon chip is inserted in diffusion furnace, carry out thermal diffusion for the first time after the oxygen in emptying diffusion furnace, diffusion concentration is about 5 * 10
-14cm
-3to 1 * 10
-15cm
-3, diffusion temperature is about 1100-1200 degree Celsius, is about 2-3 hour diffusion time;
Wherein, in step 2, in the diffusion furnace of completing steps one, pass into oxygen, thereby form oxide layer on the doped region surface of silicon chip, diffusion furnace temperature is about 700-800 degree Celsius, and the thickness that forms oxide layer is about 100-150 dust;
Wherein, in step 3, will form the silicon chip extracting of oxide layer, form the surface-coated mixed liquor of oxide layer at silicon chip, described mixed liquor adds photoresist to form in boron latex source, and the ratio of boron latex source and photoresist is about (weight ratio): 10:3~6 gram; The concrete mixed process of mixed liquor is: boron latex source and photoresist are mixed, then put into stirring vessel and stir fully, mixing time is about 2.5~3.5 hours; After this mixed liquor obtaining is coated on the oxide layer surface of silicon chip to form mixed liquor coat, coat thickness is about 300-400 micron; The silicon chip that applies mixed liquor is toasted, and baking temperature is about 140-160 degree Celsius, and baking time is about 20~25 minutes; By the silicon chip extracting after baking, again put into the thermal diffusion for the second time that diffusion furnace carries out impurity, diffusion temperature is controlled at and is about 1150-1250 degree Celsius, is controlled at diffusion time and is about 2.5~3.5 hours, and diffusion concentration is about 5 * 10
-15cm
-3to 5 * 10
-16cm
-3; After diffusion, then by diffusion furnace cooling, until while reaching room temperature by silicon chip extracting, through removing after the silicon nitride layer of silicon chip surface, the doping that completes MOS device doped region is made.
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04129215A (en) * | 1990-09-20 | 1992-04-30 | Nec Corp | Manufacture of semiconductor device |
US20060183307A1 (en) * | 2004-12-20 | 2006-08-17 | Ajeet Rohatgi | Boron diffusion in silicon devices |
CN1933110A (en) * | 2006-10-13 | 2007-03-21 | 鞍山市华辰电力器件有限公司 | Method for III family elements two-time spreading and raising large power transistor blocking current-voltage characteristics |
CN102254801A (en) * | 2011-08-06 | 2011-11-23 | 深圳市稳先微电子有限公司 | Method for controlling doping density of doped region of semiconductor device accurately |
-
2013
- 2013-10-22 CN CN201310500173.5A patent/CN103617948B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04129215A (en) * | 1990-09-20 | 1992-04-30 | Nec Corp | Manufacture of semiconductor device |
US20060183307A1 (en) * | 2004-12-20 | 2006-08-17 | Ajeet Rohatgi | Boron diffusion in silicon devices |
CN1933110A (en) * | 2006-10-13 | 2007-03-21 | 鞍山市华辰电力器件有限公司 | Method for III family elements two-time spreading and raising large power transistor blocking current-voltage characteristics |
CN102254801A (en) * | 2011-08-06 | 2011-11-23 | 深圳市稳先微电子有限公司 | Method for controlling doping density of doped region of semiconductor device accurately |
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Effective date of registration: 20170726 Address after: Licheng Town East Street Liyang city 213300 Jiangsu city of Changzhou province No. 182 Patentee after: Liyang Technology Development Center Address before: Li Town of Liyang City, Jiangsu province 213300 Changzhou City Dongmen Street No. 67 Patentee before: LIYANG DONGDA TECHNOLOGY TRANSFER CENTER CO., LTD. |