CN103943479A - Preparation method for gate oxide - Google Patents
Preparation method for gate oxide Download PDFInfo
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- CN103943479A CN103943479A CN201410162741.XA CN201410162741A CN103943479A CN 103943479 A CN103943479 A CN 103943479A CN 201410162741 A CN201410162741 A CN 201410162741A CN 103943479 A CN103943479 A CN 103943479A
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- gate oxide
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- nitrogen
- temperature
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
Abstract
The invention provides a preparation method for gate oxide. Nitrogen is used for attenuating hydrogen in reaction gas to reduce the number of Si-H bonds and S-O-H bonds generated on an Si-SiO2 interface, high-temperature treatment is performed on a substrate after an oxidation film is formed to accelerate stress releasing of the inside structure of the oxidation film so that the possibility of generating an interface state because of rupture bonds generated nearby the interface can be reduced. By the adoption of the method, total charge of the interface state of the gate oxide can be effectively reduced by at least one order of magnitude, and because the gate oxide has stable nitrogen content, service life of components can be prolonged, and performance of the components can be improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of preparation method of gate oxide.
Background technology
Along with dwindling of the size of semiconductor device, the gate oxide thickness that is applied to programmable logic device requires to be less than 2nm, and this has caused a series of problems such as interface trapped charge, gate medium tunnelling leakage current and reliability.These problems be considered to a certain extent with film in Si atom or and the Si-SiO of the not complete oxidation that exists
2the interfacial state that interface exists is relevant.
Generation about interfacial state mainly contains following two kinds of reasons:
1. the mechanism based on hydrogen bond model.This mechanism is thought Si-SiO
2the hydrogen bonds structure of near interface, owing to catching the kinetic energy of incident charge carrier and occur the disengaging of hydrogen atom, makes original Si-H and Si-O-H bond fission, causes the generation of dangling bonds, and has caused thus the generation of interfacial state.
2. the mechanism based on internal stress.This mechanism is thought Si-SiO
2the Si-Si key of near interface and the impact that exists the Si-O key of internal stress to be subject to external charge carrier due to irregular structure are ruptured, thereby cause interfacial state to produce.
In existing technique, mainly by high annealing, repair oxidation growth SiO
2the Si-H key producing in the process of dielectric layer and S-O-H key and Si-SiO
2the breaking bonds that near interface occurs, to improve interfacial state.But since semiconductor technology enters 45 nanometer era, traditional method of improving gate oxidation films interfacial state has run into unprecedented challenge, the thermal oxidation technique after film forming cannot be improved interfacial state timely and effectively.
Summary of the invention
For improving in less semiconductor device, improve interfacial state, the invention provides a kind of preparation method of gate oxide, comprise following steps:
S1 a: substrate is carried out to oxidation technology to form gate oxide, comprise nitrogen at the reacting gas of described oxidation technology;
S2: in nitrogen environment, described substrate is carried out to high-temperature process;
S3: described gate oxide is carried out to nitrogen doping;
S4: the nitrogen that adopts high-temperature annealing process to stablize described gate oxide adulterates and repairs its plasma damage.Optionally, in step S1, oxidation technology adopts ISSG technique.
Optionally, the reacting gas of described ISSG technique is N
2o and H
2.
Optionally, the reacting gas of described ISSG technique is O
2and H
2.
Optionally, in described reacting gas, the flow of nitrogen is 5slm-50slm, and the amount of substance of described nitrogen is that half of remaining reaction gas is to 3 times.
Optionally, the temperature range that described high-temperature ammonolysis is processed is 1000 degrees Celsius to 1100 degrees Celsius, and the processing time is 5 seconds to 120 seconds.
Optionally, the doping of the nitrogen in step S3 using plasma Nitriding Technology.
Optionally, described pecvd nitride technology is decoupled plasma nitridation or remote plasma nitridation.
Optionally, the temperature range of the high-temperature annealing process in step S4 is 1000 degrees Celsius to 1100 degrees Celsius, and the time is 5 seconds to 120 seconds.
Optionally, the gas of the high-temperature annealing process in step S4 comprises N
2or O
2or N
2with O
2mist.
Than prior art, the present invention, by adopting nitrogen to carry out the content of hydrogen in diluting reaction gas, reduces Si-SiO
2the quantity of generation of interfaces Si-H key and S-O-H key, and substrate real time high temperature is processed to accelerate the Stress Release of oxide-film internal structure after forming oxide-film, to reduce near interface generation breaking bonds, produce the possible of interfacial state.Adopt method provided by the present invention can effectively reduce at least one order of magnitude of interfacial state total electrical charge of gate oxidation films, and gate oxide has stable nitrogen content, can improve life-span and the performance of device.
Accompanying drawing explanation
Fig. 1 is the flow chart of the preparation method of gate oxide described in one embodiment of the invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
As shown in Figure 1, the preparation method of gate oxide provided by the invention comprises following steps:
S1 a: substrate is carried out to oxidation technology to form gate oxide, comprise nitrogen at described oxidation technology reacting gas.
Wherein, described oxidation technology is that insitu moisture generates (ISSG), ISSG is a kind of New Low Voltage Quick Oxidation thermal annealing technology, is mainly used at present the preparation of ultra-thin oxide film growth, shallow-trench isolation rounded at the edge (STI corner rounding) and nitrogen oxygen film.It adopts hydrogen (H
2) and oxygen (O
2) as reacting gas, at high temperature hydrogen can produce the chemical reaction that is similar to burning with oxygen, generates a large amount of gas-phase activity free radical (being mainly wherein elemental oxygen).Meanwhile, in reaction cavity, by the radiant type technology of being rapidly heated, make silicon chip be warming up to 800 ℃-1100 ℃, under this high temperature atmosphere, silicon chip surface can be similar to the chemical reaction of detonation.Because elemental oxygen has extremely strong oxidizability, in the oxidation film body that makes finally to obtain, defect reduces, Si-SiO
2interface is fully oxidized, thereby can effectively improve the electrology characteristic of film.The reacting gas of ISSG technique is except being above-mentioned H
2and O
2outside, can be also N
2o and H
2.
In order better to improve gate oxide interfacial state, in above-mentioned reacting gas hydrogen and oxygen, mix nitrogen, can reach H in diluting reaction gas
2the object of content.Thus, reduced Si-SiO
2the quantity of the hydrogen bonds (as Si-H and Si-O-H) that near interface produces, prevents because the disengaging of hydrogen atom causes the generation of dangling bonds in hydrogen bonds, and then causes the generation of interfacial state trap.Concrete, the flow of above-mentioned nitrogen is 5slm-50slm, and the amount of substance of nitrogen is that half of remaining reaction gas is to 3 times.Those skilled in the art can also change according to actual device requirement flow and the ratio of above-mentioned nitrogen.
S2: in nitrogen environment, described substrate is carried out to high-temperature process.
After ISSG operation forms the process of gate oxide, in nitrogen environment, described substrate is carried out to high-temperature process, so can accelerate the Stress Release of oxide-film internal structure, to reduce the possibility of near interface generation breaking bonds.Therefore, oxidation and high-temperature process are carried out simultaneously, can realize the real-time improvement to gate oxidation films interfacial state, obtain better effect.Concrete, the temperature range of above-mentioned high-temperature process is 1000 degrees Celsius to 1100 degrees Celsius, the processing time is 5 seconds to 120 seconds.
S3: described gate oxide is carried out to nitrogen doping.
Described nitrogen doping using plasma Nitriding Technology, be specially decoupled plasma nitridation DPN (Decoupled Plasma Nitridation), the NO of remote plasma nitridation RPN (Remote Plasma Nitridation) or vertical proliferation equipment, N
2o or NH
3deng nitrogenation treatment technology.Nitrogen doping can improve the dielectric coefficient of gate oxide, improves the performance of gate oxide.
S4: the nitrogen that adopts high-temperature annealing process to stablize described gate oxide adulterates and repairs its plasma damage.
Wherein, the temperature range of described high-temperature annealing process is 1000 degrees Celsius to 1100 degrees Celsius, and the time is 5 seconds to 120 seconds.The gas of high-temperature annealing process comprises N
2or O
2or N
2with O
2mist.Concrete, annealing process comprises two steps, first in nitrogen environment, carries out, in order to promote the bonding of doping nitrogen with stable; Second step carries out in pure oxygen or the oxygen containing environment of part, and the defect at gate oxide and channel interface place can be effectively repaired in the introducing of oxygen, thereby further improves the electric property of device.
To sum up, the present invention is by adopting nitrogen to come the content of hydrogen in diluting reaction gas to reduce Si-SiO
2the quantity of generation of interfaces Si-H key and Si-O-H key, and substrate real time high temperature is processed to accelerate the Stress Release of oxide-film internal structure after forming oxide-film, to reduce near interface generation breaking bonds, produce the possible of interfacial state.Adopt method provided by the present invention can effectively reduce at least one order of magnitude of interfacial state total electrical charge of gate oxidation films, and gate oxide has stable nitrogen content, can improve life-span and the performance of device.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these change and modification.
Claims (10)
1. a preparation method for gate oxide, is characterized in that, comprises
S1 a: substrate is carried out to oxidation technology to form gate oxide, comprise nitrogen in the reacting gas of described oxidation technology;
S2: in nitrogen environment, described substrate is carried out to high-temperature process;
S3: described gate oxide is carried out to nitrogen doping;
S4: the nitrogen that adopts high-temperature annealing process to stablize described gate oxide adulterates and repairs its plasma damage.
2. the preparation method of gate oxide as claimed in claim 1, is characterized in that, in step S1, oxidation technology adopts ISSG technique.
3. the preparation method of gate oxide as claimed in claim 2, is characterized in that, the reacting gas of described ISSG technique is N
2o and H
2.
4. the preparation method of gate oxide as claimed in claim 2, is characterized in that, the reacting gas of described ISSG technique is O
2and H
2.
5. the preparation method of gate oxide as claimed in claim 1, is characterized in that: in described reacting gas, the flow of nitrogen is 5slm-50slm, and the amount of substance of described nitrogen is that half of remaining reaction gas is to 3 times.
6. the preparation method of gate oxide as claimed in claim 1, is characterized in that: the temperature range that described high-temperature ammonolysis is processed is 1000 degrees Celsius to 1100 degrees Celsius, and the processing time is 5 seconds to 120 seconds.
7. the preparation method of gate oxide as claimed in claim 1, is characterized in that: the nitrogen doping using plasma Nitriding Technology in step S3.
8. the preparation method of gate oxide as claimed in claim 7, is characterized in that: described pecvd nitride technology is decoupled plasma nitridation or remote plasma nitridation.
9. the preparation method of gate oxide as claimed in claim 1, is characterized in that: the temperature range of the high-temperature annealing process in step S4 is 1000 degrees Celsius to 1100 degrees Celsius, and the time is 5 seconds to 120 seconds.
10. the preparation method of gate oxide as claimed in claim 1, is characterized in that: the gas of the high-temperature annealing process in step S4 comprises N
2or O
2or N
2with O
2mist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410162741.XA CN103943479A (en) | 2014-04-22 | 2014-04-22 | Preparation method for gate oxide |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410162741.XA CN103943479A (en) | 2014-04-22 | 2014-04-22 | Preparation method for gate oxide |
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|---|---|
| CN103943479A true CN103943479A (en) | 2014-07-23 |
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| CN201410162741.XA Pending CN103943479A (en) | 2014-04-22 | 2014-04-22 | Preparation method for gate oxide |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104713588A (en) * | 2015-03-20 | 2015-06-17 | 上海华力微电子有限公司 | Method for monitoring cleanliness of vacuum cavity of electron microscope |
| CN105185700A (en) * | 2015-08-11 | 2015-12-23 | 上海华力微电子有限公司 | Preparation method of ultra-thin gate oxygen |
| CN108807165A (en) * | 2018-06-14 | 2018-11-13 | 上海华力集成电路制造有限公司 | The manufacturing method of oxide layer |
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| US20090280654A1 (en) * | 2008-05-09 | 2009-11-12 | Promos Technologies, Inc. | Method of forming a silicon nitride layer on a gate oxide film of a semiconductor device and annealing the nitride layer |
| CN103346077A (en) * | 2013-07-09 | 2013-10-09 | 上海华力微电子有限公司 | Preparation method of gate oxide |
| CN103441064A (en) * | 2013-06-24 | 2013-12-11 | 上海华力微电子有限公司 | Method for improving gate oxide surface uniformity |
| CN103489770A (en) * | 2013-09-22 | 2014-01-01 | 上海华力微电子有限公司 | Grid oxide layer growth method and CMOS tube manufacturing method |
-
2014
- 2014-04-22 CN CN201410162741.XA patent/CN103943479A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101290886A (en) * | 2007-04-20 | 2008-10-22 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of grid dielectric layer and grid |
| US20090280654A1 (en) * | 2008-05-09 | 2009-11-12 | Promos Technologies, Inc. | Method of forming a silicon nitride layer on a gate oxide film of a semiconductor device and annealing the nitride layer |
| CN103441064A (en) * | 2013-06-24 | 2013-12-11 | 上海华力微电子有限公司 | Method for improving gate oxide surface uniformity |
| CN103346077A (en) * | 2013-07-09 | 2013-10-09 | 上海华力微电子有限公司 | Preparation method of gate oxide |
| CN103489770A (en) * | 2013-09-22 | 2014-01-01 | 上海华力微电子有限公司 | Grid oxide layer growth method and CMOS tube manufacturing method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104713588A (en) * | 2015-03-20 | 2015-06-17 | 上海华力微电子有限公司 | Method for monitoring cleanliness of vacuum cavity of electron microscope |
| CN104713588B (en) * | 2015-03-20 | 2017-03-29 | 上海华力微电子有限公司 | A kind of method of monitoring ultramicroscope vacuum cavity cleanliness factor |
| CN105185700A (en) * | 2015-08-11 | 2015-12-23 | 上海华力微电子有限公司 | Preparation method of ultra-thin gate oxygen |
| CN108807165A (en) * | 2018-06-14 | 2018-11-13 | 上海华力集成电路制造有限公司 | The manufacturing method of oxide layer |
| CN108807165B (en) * | 2018-06-14 | 2021-04-13 | 上海华力集成电路制造有限公司 | Method for producing oxide layer |
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Application publication date: 20140723 |