CN103617321B - Reduce the method for different end angles lower bumper chain time delay change - Google Patents
Reduce the method for different end angles lower bumper chain time delay change Download PDFInfo
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- CN103617321B CN103617321B CN201310615670.XA CN201310615670A CN103617321B CN 103617321 B CN103617321 B CN 103617321B CN 201310615670 A CN201310615670 A CN 201310615670A CN 103617321 B CN103617321 B CN 103617321B
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Abstract
The present invention discloses a kind of method reducing the lower bumper chain time delay change of different end angles, and the method, using the fault path of hold-time in chip design as research object, extracts the sequential allowance under optimum, worst end angle, input bound-time and load electric capacity; The minimum time delay of buffer chain under traveling through all snubbers and calculating optimum end angle; If time delay meets target delay requirement, continue to calculate the buffer chain maximum delay under worst end angle; Computation delay velocity of variation, selects to export the buffer chain A more minimum than time delay velocity of variation, if there is no the buffer chain of time delay velocity of variation in stated limit, and output buffer chain A, otherwise contrast exports the minimum buffer chain of area. The present invention can reduce the lower bumper chain time delay change of different end angles, reduces the iteration number of times between different end angle to a great extent, greatly shorten design cycle, speed-up chip sequential.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, it is specifically related to a kind of method reducing the lower bumper chain time delay change of different end angles.
Background technology
Growing along with integrated circuit technology, the size of transistor constantly reduces, and current transistor size has been reduced to 28nm. Transistor size reduce requirement manufacturing process accurately, and the subtle change of manufacturing process can bring significant processing parameter deviation. Technique contracting is put and is required that with circuit layout voltage of supply is put by corresponding proportion contracting simultaneously, and power electric compression is put the high-speed turnover with unicircuit node and also can be brought voltage deviation. The switch reactivity of standard cell and the diversity of kind cause the high power consumption of the local appearance in chip local, thus causing uneven supply voltage distribution and temperature focus, Chip Packaging and circuit long-time running also can cause each node temperature of unicircuit to change. The function of unicircuit, performance and stability can be had an impact by the deviation of technique, voltage of supply and temperature, can estimate, along with reducing further of transistor size, PVT deviation will be more obvious on the impact of unicircuit, the impact that especially unit time delay is changed by PVT deviation.
In the physical Design of current chip, snubber is as the elementary cell of timing optimization, and its time delay, power consumption and driving force are more and more subject to the attention of slip-stick artist. Along with the reduction of cell process size, the needs of chip high-performance designs, the application at multi-mode multiterminal angle in timing optimization, on setting up, the reparation that the time breaks rules and the hold-time breaks rules produces increasing impact in the time delay change of snubber. Under normal circumstances, placement-and-routing's instrument, automatically having repaired the timing closure under certain end angle in the process broken rules, there will be again bigger sequential and breaks rules, so often needing a large amount of manual operation under other end angles, iterate between different end angle, it is ensured that the timing closure in fault path.Therefore, the convergence that sequential is accelerated in the time delay change how reducing different end angles lower bumper in timing optimization process becomes more and more urgent.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of can reduce the lower bumper chain time delay change of different end angles, reduce the iteration number of times between different end angle to a great extent, the method for the reduction different end angles lower bumper chain time delay change of the convergence of greatly shortening design cycle, speed-up chip sequential.
In order to solve the problems of the technologies described above, the technical solution used in the present invention is:
Reducing a method for different end angles lower bumper chain time delay change, implementation step is as follows:
1) the buffer data end sequential allowance under optimum end angle and worst end angle, input bound-time and load electric capacity respectively is extracted by placement-and-routing's instrument, using the sequential allowance under described optimum end angle as target time delay;
2) under optimum end angle, travel through the snubber of buffer chain, calculate the area of optimum end angle lower bumper chain, and according to the time delay of the input bound-time under optimum end angle and the single snubber of load capacitance calculation, and using the time delay of minimum single snubber as the minimum time delay of buffer chain;
3) judging whether to have buffer chain time delay to meet the buffer chain of described target time delay, if not having buffer chain time delay to meet the buffer chain of target time delay, then increasing described target time delay and redirect execution step 2); Otherwise under worst end angle, according to the time delay of the input bound-time under worst end angle and the single snubber of load capacitance calculation, and the time delay summation combination of single snubber is obtained buffer chain maximum delay, and redirect performs step 4);
4) the buffer chain maximum delay that each meets target time delay buffer chain respectively obtains the time delay velocity of variation of buffer chain divided by the minimum time delay of buffer chain, and the buffer chain selecting the time delay velocity of variation of a buffer chain minimum is as target buffer chain;
5) the time delay velocity of variation of all buffer chain meeting target time delay and the time delay velocity of variation of target buffer chain being compared, if not finding the buffer chain of time delay velocity of variation in stated limit, then directly exporting target buffer chain; If finding the buffer chain of time delay velocity of variation in stated limit, then comparing all buffer chain of time delay velocity of variation in stated limit, from all buffer chain, searching the minimum buffer chain of area export.
The further improvements in methods of different end angles lower bumper chain time delay change are reduced as the present invention:
Described step 2) in when traveling through the snubber of buffer chain under optimum end angle, specifically refer to all snubbers of traversal first-level buffer device chain, level 2 buffering device chain, three grades of buffer chain.
Described step 2) in when traveling through the snubber of buffer chain under optimum end angle, if the minimum time delay of snubber in timing unit storehouse is greater than target time delay, then directly ignores this snubber and start to process next snubber.
Described step 2) in as follows according to the detailed step of the input bound-time under optimum end angle and the time delay of the single snubber of load capacitance calculation: search timing sequence library file list according to the input bound-time under optimum end angle and load electric capacity, judge whether hit delay value, if hit delay value, directly export the delay value of hit; Otherwise, given delay value in four tables adjacent with hit point in acquisition timing sequence library file list, calculates the delay value of hit point according to given delay value employing linear interpolation method in four tables that described hit point is adjacent and exports.
Described step 3) in as follows according to the detailed step of the input bound-time under worst end angle and the time delay of the single snubber of load capacitance calculation: search timing sequence library file list according to the input bound-time under worst end angle and load electric capacity, judge whether hit delay value, if hit delay value, directly export the delay value of hit;Otherwise, given delay value in four tables adjacent with hit point in acquisition timing sequence library file list, calculates the delay value of hit point according to given delay value employing linear interpolation method in four tables that described hit point is adjacent and exports.
Described step 3) in increase described target time delay and specifically refer to described target time delay is increased by 0.1 times.
Described step 5) in 1��1.1 times of time delay velocity of variation of stated limit specifically target buffer chain.
The method that the present invention reduces the lower bumper chain time delay change of different end angles has following advantage: after placement-and-routing's instrument repairs automatically, it is still necessary to a large amount of manual operation, iterates between different end angle, just can guarantee all paths timing closure. In order to the iteration number of times reduced between different end angle, shorten the cycle of design, the timing closure of speed-up chip, the present embodiment is using the fault path of hold-time in chip design as research object, the known worst end angle setting up time time series analysis is WC, the worst end angle of hold-time time series analysis is BC, extracts the sequential allowance under WC and optimum end angle, input bound-time and load electric capacity; Travel through all snubbers and calculate the time delay of optimum end angle lower bumper chain; Its time delay meets the time delay that target delay requirement then continues to calculate worst end angle lower bumper chain; The buffer chain maximum delay that each meets target time delay buffer chain respectively obtains the time delay velocity of variation of buffer chain divided by the minimum time delay of buffer chain, the buffer chain selecting the time delay velocity of variation of a buffer chain minimum is as target buffer chain, the time delay velocity of variation of the time delay velocity of variation of all buffer chain meeting target time delay and target buffer chain is compared, if not finding the buffer chain of time delay velocity of variation in stated limit, then directly export target buffer chain; If finding the buffer chain of time delay velocity of variation in stated limit, then compare all buffer chain of time delay velocity of variation in stated limit, from all buffer chain, search the minimum buffer chain of area export the advantage with the following aspects: 1, accelerate timing closure. Buffer chain time delay velocity of variation under different end angles is little, while ensure that hold-time fault is repaired fast, can not cause and break rules for two times of the time of foundation. 2, the design cycle is short. Needing manually to iterate under different end angle in timing optimization process, ensure the timing closure at each end angle, the present invention is realized by script language completely, complete the automatization of design, reduce the number of times of iteration, shorten the cycle of design greatly, it is to increase the efficiency of design. 3, cell density is reduced. All buffer chain meeting target time delay have been analyzed by the present invention, have selected the reparation of the minimum buffer chain of area for the path that breaks rules, reduce the cell density in chip design, for physical space is vacated in newly-increased unit and wiring.
Accompanying drawing explanation
Fig. 1 is the basic procedure schematic diagram of embodiment of the present invention method.
Fig. 2 is the structural representation of buffer chain in the embodiment of the present invention.
The time delay that Fig. 3 is different end angles lower bumper chain in the embodiment of the present invention calculates principle schematic.
Fig. 4 is the principle schematic of the linear interpolation method in the embodiment of the present invention.
Embodiment
As shown in Figure 1, the implementation step of the method that the present embodiment reduces the lower bumper chain time delay change of different end angles is as follows:
The first step, the buffer data end sequential allowance under optimum (BestCase) holds angle and worst (WorstCase) to hold angle, input bound-time and load electric capacity respectively is extracted, using the sequential allowance under described optimum end angle as target time delay by placement-and-routing's instrument.Sequential allowance under optimum end angle and worst end angle, input bound-time and load electric capacity will be used for calculating the time delay of buffer chain to buffer data end respectively.
2nd step, the snubber of buffer chain is traveled through under optimum end angle, calculate the area of optimum end angle lower bumper chain, and according to the time delay of the input bound-time under optimum end angle and the single snubber of load capacitance calculation, and using the time delay of minimum single snubber as the minimum time delay Tmin of buffer chain.
As shown in Figure 2, in buffer chain, each snubber adopts the mode of " end to end " near connecting, and this kind of mode of connection reduces the impact that snubber is inputted bound-time and load electric capacity by interconnection line, ensure that the acquisition of a more accurate delay value.
When the present embodiment travels through the snubber of buffer chain under optimum end angle, specifically refer to all snubbers of traversal first-level buffer device chain, level 2 buffering device chain, three grades of buffer chain. The present embodiment has only used one-level, two grades and three grades of buffer chain, and its reason is that the time delay velocity of variation of buffer chain is included among first three level after three grades, it is not necessary to the extra traversal burden increasing snubber; And progression is more many, the input bound-time of buffer chain and load electric capacity will become uncontrollable, cause the delay value that in delay value that buffer chain calculates and practice, placement-and-routing's instrument calculates not identical.
When the present embodiment travels through the snubber of buffer chain under optimum end angle, if the minimum time delay of snubber in timing unit storehouse is greater than target time delay, then directly ignores this snubber and start to process next snubber. The time delay of snubber is judged by this step, if the minimum time delay of certain snubber in timing unit storehouse is greater than target time delay, so using the unit of this snubber as traversal, the traversal time of snubber can not be greatly reduced like this in the deterministic process of buffer chain.
It should be noted that, unit time delay is the function of input bound-time and load electric capacity, and placement-and-routing's instrument only needs acquiring unit input bound-time and load electric capacity, so that it may to obtain definite delayed data in timing sequence library file. As using the input bound-time of the input bound-time of the buffer data end in step 1 as first step snubber in buffer chain, the input end capacitor of second stage snubber is as the load electric capacity of first step snubber, so that it may to calculate the cell delay of first step snubber. With reason, using the input bound-time of the output bound-time of first step snubber as the snubber second season, using the load electric capacity of the input capacitance of third stage snubber as second stage snubber, so that it may to calculate the cell delay of second stage snubber. And for third stage snubber, then the electric capacity of the snubber input terminus in step 1 is as its load capacitance calculation cell delay. When in 7 �� 7 tables inputting bound-time and load electric capacity and not appearing at timing sequence library file, it is necessary to find out the interval range that they drop in table, then calculated the time delay of needs by linear interpolation method according to the value of these border scopes.
Therefore, the present embodiment step 2) in as follows according to the detailed step of the input bound-time under optimum end angle and the time delay of the single snubber of load capacitance calculation: search timing sequence library file list according to the input bound-time under optimum end angle and load electric capacity, judge whether hit delay value, if hit delay value, directly export the delay value of hit; Otherwise, given delay value in four tables adjacent with hit point in acquisition timing sequence library file list, calculates the delay value of hit point according to given delay value employing linear interpolation method in four tables that described hit point is adjacent and exports.
The principle of linear interpolation method is see Fig. 4, assume that M point (x, y) is for delay value to be asked, with hit point M point (x in timing sequence library file list, y) in four adjacent tables, set point is respectively Q11, Q12, Q22, Q21, respectively coordinate (the x in corresponding diagram 41,y1)��(x1,y2)��(x2,y2)��(x2,y1), and the delay value of its correspondence is respectively f (Q11)��f(Q12)��f(Q22)��f(Q21).When utilizing linear interpolation method to seek M point (x, y) delay value, formula (1) is first utilized to calculate the value of R1, R2; Then utilizing formula (2) to calculate f (M), f (M) is exactly the delay value of single snubber.
2.2) utilizing formula (2) to calculate M value, M value is exactly the delay value of single snubber.
3rd step, judges whether have buffer chain time delay to meet the buffer chain of described target time delay, if not having buffer chain time delay to meet the buffer chain of target time delay, then increases described target time delay and redirect execution step 2); Otherwise under worst end angle, according to the time delay of the input bound-time under worst end angle and the single snubber of load capacitance calculation, and the time delay summation combination of single snubber is obtained buffer chain maximum delay Tmax, and redirect performs step 4);
As shown in Figure 3, the present embodiment first must by being greater than in snubber set to travel through the area calculating all buffer chain meeting target delay be switched to worst end angle with postponing again on the basis of Tmin at optimum end angle, split under worst end angle and calculate, obtain the delay under worst end angle of each snubber in buffer chain, and the delay under being added the worst end angle obtaining buffer chain, complete the combination calculation under worst end angle, obtain buffer chain maximum delay Tmax. In the present embodiment, increase described target time delay and specifically refer to described target time delay is increased by 0.1 times to have the selection of more buffer chain like this when error is less.
In the present embodiment, step 3) in as follows according to the detailed step of the input bound-time under worst end angle and the time delay of the single snubber of load capacitance calculation: search timing sequence library file list according to the input bound-time under worst end angle and load electric capacity, judge whether hit delay value, if hit delay value, directly export the delay value of hit; Otherwise, given delay value in four tables adjacent with hit point in acquisition timing sequence library file list, calculates the delay value of hit point according to given delay value employing linear interpolation method in four tables that described hit point is adjacent and exports. Wherein, detail and the step 2 of linear interpolation method) in the linear interpolation method that uses identical, do not repeat them here.
4th step, the buffer chain maximum delay Tmax that each meets target time delay buffer chain respectively obtains the time delay velocity of variation (P=Tmax/Tmin) of buffer chain divided by the minimum time delay Tmin of buffer chain, and the buffer chain A selecting the time delay velocity of variation P of a buffer chain minimum is as target buffer chain.
5th step, by the time delay velocity of variation P of the time delay velocity of variation P of all buffer chain meeting target time delay and target buffer chain AAComparing, if not finding the buffer chain of time delay velocity of variation P in stated limit, then directly exporting target buffer chain A; If finding the buffer chain of time delay velocity of variation in stated limit, then comparing all buffer chain of time delay velocity of variation in stated limit, from all buffer chain, searching the minimum buffer chain B of area export.
In the present embodiment, step 5) in 1��1.1 times of time delay velocity of variation of stated limit specifically target buffer chain, namely P value is at PA��(PA+ 10%PA) buffer chain in scope is the buffer chain of time delay velocity of variation P in stated limit, compare the area of all buffer chain within the scope of this, and export the buffer chain B that area is minimum. The main purpose of this step is the cell density reduced in chip design, thus vacates physical space for increasing unit and wiring newly.
After placement-and-routing's instrument repairs automatically, it is still necessary to a large amount of manual operation, iterate between different end angle, just can guarantee all paths timing closure.In order to the iteration number of times reduced between different end angle, shorten the cycle of design, the timing closure of speed-up chip, the present embodiment is using the fault path of hold-time in chip design as research object, the known worst end angle setting up time time series analysis is WC (WorstCase), the optimum end angle of hold-time time series analysis is BC (BestCase), extracts the sequential allowance under worst end angle and optimum end angle, input bound-time and load electric capacity; Travel through all snubbers and calculate the time delay Tmin of optimum end angle lower bumper chain; Its time delay meets the time delay Tmax that target delay requirement then continues to calculate worst end angle lower bumper chain; The size (definition time delay velocity of variation P=Tmax/Tmin) of contrast buffer chain Tmax/Tmin, exports the buffer chain A that P value is minimum; If there is the P value of some buffer chain and the substantially equal (P of P value size of buffer chain AA��(PA+ 10%PA) in scope), then contrast exports the minimum buffer chain of area. The present embodiment has the advantage of the following aspects in the utilization that the hold-time breaks rules in reparation: 1, accelerate timing closure. Buffer chain time delay velocity of variation under different end angles is little, while ensure that hold-time fault is repaired fast, can not cause and break rules for two times of the time of foundation. 2, the design cycle is short. Timing optimization process needs manually iterate under different end angle, ensure the timing closure at each end angle, the present embodiment is realized by script language completely, complete the automatization of design, reduce the number of times of iteration, shorten the cycle of design greatly, it is to increase the efficiency of design. 3, cell density is reduced. All buffer chain meeting target time delay have been analyzed by the present embodiment various countries, have selected the reparation of the minimum buffer chain of area for the path that breaks rules, reduce the cell density in chip design such that it is able to for physical space is vacated in newly-increased unit and wiring.
The above is only the preferred embodiment of the present invention, and protection scope of the present invention is also not only confined to above-described embodiment, and all technical schemes belonged under thinking of the present invention all belong to protection scope of the present invention. It is noted that for those skilled in the art, some improvements and modifications without departing from the principles of the present invention, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (7)
1. one kind is reduced the method for different end angles lower bumper chain time delay change, it is characterised in that implementation step is as follows:
1) the buffer data end sequential allowance under optimum end angle and worst end angle, input bound-time and load electric capacity respectively is extracted by placement-and-routing's instrument, using the sequential allowance under described optimum end angle as target time delay;
2) under optimum end angle, travel through the snubber of buffer chain, calculate the area of optimum end angle lower bumper chain, and according to the time delay of the input bound-time under optimum end angle and the single snubber of load capacitance calculation, and using the time delay of minimum single snubber as the minimum time delay of buffer chain;
3) judging whether to have buffer chain time delay to meet the buffer chain of described target time delay, if not having buffer chain time delay to meet the buffer chain of target time delay, then increasing described target time delay and redirect execution step 2); Otherwise under worst end angle, according to the time delay of the input bound-time under worst end angle and the single snubber of load capacitance calculation, and the time delay summation combination of single snubber is obtained buffer chain maximum delay, and redirect performs step 4);
4) the buffer chain maximum delay that each meets target time delay buffer chain respectively obtains the time delay velocity of variation of buffer chain divided by the minimum time delay of buffer chain, and the buffer chain selecting the time delay velocity of variation of a buffer chain minimum is as target buffer chain;
5) the time delay velocity of variation of all buffer chain meeting target time delay and the time delay velocity of variation of target buffer chain being compared, if not finding the buffer chain of time delay velocity of variation in stated limit, then directly exporting target buffer chain; If finding the buffer chain of time delay velocity of variation in stated limit, then comparing all buffer chain of time delay velocity of variation in stated limit, from all buffer chain, searching the minimum buffer chain of area export.
2. the method reducing the lower bumper chain time delay change of different end angles according to claim 1, it is characterized in that: described step 2) in when traveling through the snubber of buffer chain under optimum end angle, specifically refer to all snubbers of traversal first-level buffer device chain, level 2 buffering device chain, three grades of buffer chain.
3. the method reducing the lower bumper chain time delay change of different end angles according to claim 2, it is characterized in that: described step 2) in when traveling through the snubber of buffer chain under optimum end angle, if the minimum time delay of snubber in timing unit storehouse is greater than target time delay, then directly ignores this snubber and start to process next snubber.
4. the method reducing the lower bumper chain time delay change of different end angles according to claim 3, it is characterized in that: described step 2) in as follows according to the detailed step of the input bound-time under optimum end angle and the time delay of the single snubber of load capacitance calculation: search timing sequence library file list according to the input bound-time under optimum end angle and load electric capacity, judge whether hit delay value, if hit delay value, directly export the delay value of hit; Otherwise, given delay value in four tables adjacent with hit point in acquisition timing sequence library file list, calculates the delay value of hit point according to given delay value employing linear interpolation method in four tables that described hit point is adjacent and exports.
5. the method reducing the lower bumper chain time delay change of different end angles according to claim 4, it is characterized in that: described step 3) in as follows according to the detailed step of the input bound-time under worst end angle and the time delay of the single snubber of load capacitance calculation: search timing sequence library file list according to the input bound-time under worst end angle and load electric capacity, judge whether hit delay value, if hit delay value, directly export the delay value of hit; Otherwise, given delay value in four tables adjacent with hit point in acquisition timing sequence library file list, calculates the delay value of hit point according to given delay value employing linear interpolation method in four tables that described hit point is adjacent and exports.
6. according to the method for the different end angles of reduction described in any one in Claims 1 to 5 lower bumper chain time delay change, it is characterised in that: described step 3) in increase described target time delay and specifically refer to described target time delay is increased by 0.1 times.
7. the method reducing the lower bumper chain time delay change of different end angles according to claim 6, it is characterised in that: described step 5) in 1��1.1 times of time delay velocity of variation of stated limit specifically target buffer chain.
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| CN1250557A (en) * | 1997-03-24 | 2000-04-12 | 英特尔公司 | Method and apparatus for slew rate and impedance compensating buffer circuits |
| US6634014B1 (en) * | 2000-12-12 | 2003-10-14 | Lsi Logic Corporation | Delay/load estimation for use in integrated circuit design |
| CN1687934A (en) * | 2005-05-13 | 2005-10-26 | 清华大学 | Standard unit overall wiring method of multi-terminal network plug-in buffer optimizing delay |
| CN103197232A (en) * | 2009-03-26 | 2013-07-10 | 台湾积体电路制造股份有限公司 | Method and apparatus for diagnosing an integrated circuit |
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| US7191416B2 (en) * | 2003-01-27 | 2007-03-13 | Stmicroelectronics Limited | System and method for modifying integrated circuit hold times |
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|---|---|---|---|---|
| CN1250557A (en) * | 1997-03-24 | 2000-04-12 | 英特尔公司 | Method and apparatus for slew rate and impedance compensating buffer circuits |
| US6634014B1 (en) * | 2000-12-12 | 2003-10-14 | Lsi Logic Corporation | Delay/load estimation for use in integrated circuit design |
| CN1687934A (en) * | 2005-05-13 | 2005-10-26 | 清华大学 | Standard unit overall wiring method of multi-terminal network plug-in buffer optimizing delay |
| CN103197232A (en) * | 2009-03-26 | 2013-07-10 | 台湾积体电路制造股份有限公司 | Method and apparatus for diagnosing an integrated circuit |
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