CN103607193A - Interface circuit which provides voltage conversion for TTL and CMOS circuits - Google Patents
Interface circuit which provides voltage conversion for TTL and CMOS circuits Download PDFInfo
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- CN103607193A CN103607193A CN201310541698.3A CN201310541698A CN103607193A CN 103607193 A CN103607193 A CN 103607193A CN 201310541698 A CN201310541698 A CN 201310541698A CN 103607193 A CN103607193 A CN 103607193A
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Abstract
The invention provides an interface circuit which provides voltage conversion for TTL and CMOS circuits, and TTL output voltage can be effectively reduced to a CMOS input threshold range. The interface circuit comprises a field effect device which is connected to a bipolar unit which generates two times of the input voltage threshold of base emitter voltage drop. The interface circuit also comprises a switch circuit part which comprises a P channel MOS transistor and an N channel MOS transistor.
Description
Technical field
The present invention relates to a kind of interface circuit, in particular, relate to a kind of use at TTL circuit the interface circuit to cmos circuit.
Background technology
Complementary MOS (CMOS) is a kind of in IC field, and is that a kind of right logic of the ambipolar complementary transistor of PNP/NPN of the P of utilization raceway groove/N channel field-effect technology continues up-to-date complementary entrance.
Cmos circuit is so welcome in application is very low because of the required power of these circuit workings.
TTL circuit is usually operated at 5V or is less than 5V's
v cC under, or in the output voltage V of a logic level " 1 ", conventionally 2.4 to 3.5V.Complementary MOS circuit will be operated in 3 on the other hand under 15V, switching threshold, and, be about
v cC half.When two circuit
v cC while being all 5V, can directly with the output of TTL circuit, drive cmos circuit, but need pull-up resistor, and temperature upper limit has also promoted.Some serial cmos circuit can not directly be driven by the output of TTL circuit, even 5V's
v cC under, because cmos circuit
v cC higher than 5V.For needs
v cC at the cmos circuit of 10V or 15V, with regard to being not suitable for the output of TTL, drive CMOS input gate because for switch CMOS input gate required 2
v t voltage is (for 10V's
v cC 7.5V, for 15V's
v cC 10V) higher than the output V(high level of TTL).
Except the above-mentioned use of mentioning is normally used in
v cC and the pull-up resistor between TTL output/CMOS input line, in order to reduce the COMS design of logic threshold, be used, but it to be stood initial voltage tolerance and change with temperature.
Therefore, there is such demand, provide a kind of and can include a CMOS chip in and change the interface circuit that the logic output " 1 " or " 0 " of TTL circuit becomes the input that is applicable to " 1 " or " 0 " that cmos circuit receives.
Summary of the invention
Therefore, an object of the present invention is to provide an improved interface circuit in order to output to the Digital Logic conversion of CMOS door from TTL.
A further object of the present invention is to provide an improved interface circuit.Make with is connected CMOS device in, use bipolar transistor device to assemble, interface circuit is provided.An interface circuit that allows CMOS door switch to follow the tracks of the output of TTL is provided, and is also one object of the present invention.
Technical solution of the present invention is:
According to an example of the present invention, the interface circuit of the input that outputs to a MOS type circuit (CMOS) of ambipolar in order to be coupled (TTL) circuit has been disclosed.Interface circuit has comprised that an electric current regulates and bias voltage generation device, regulates electric current and produces a bias voltage source.Electric current regulates and bias voltage generation device comprises (a) bipolar transistor device, be used for stabling current and the output of bias voltage at certain level being provided and (b) being connected to the MOS transistor device of bipolar transistor device, for bipolar transistor device provides a current absorption end.Interface circuit comprises the voltage conversion device that is connected to electric current adjusting and bias voltage generation device equally, the voltage input that ambipolar (TTL) circuit is received converts the level voltage of an applicable driven MOS type circuit (CMOS) to, and corresponding with the input signal receiving from ambipolar (TTL) circuit.
Interface circuit comprises four NPN bipolar transistors, two P channel MOS transistors, five N-channel MOS transistors, one
resistance and the electric capacity of a 5pf.The collector electrode of four NPN transistor is connected to
v cC bus.Two P channel MOS transistors are all used as 50 times of micro-amplified current sources.Wherein three are used in the emitter follower configuration of Darlington for four NPN transistor.The 3rd NPN transistor in Darlington is by the grounding through resistance of 110 kilo-ohm.Other two emitters are all connected respectively to one of them lead-in wire of a drain electrode or two P channel MOS transistors, and one of them lead-in wire ground connection of source electrode or two P channel MOS transistors.The base stage of two NPN transistor links together, and by one
p channel MOS transistor current source.These base stages are connected to the transistorized drain electrode of N-channel MOS or lead-in wire equally, and the transistorized source lead ground connection of this N-channel MOS.The emitter of the 4th NPN transistor (connection of non-Darlington) is connected to the transistorized drain electrode of another N-channel MOS or lead-in wire, and its source electrode is ground connection also.Four transistorized grids of N-channel MOS are all connected to one end that 110K resistance does not have ground connection.
Virtual voltage transducer is to use the 2nd P raceway groove
the N-channel MOS transistor of current source mos transistor and a connection is realized.The source electrode of P channel MOS current source transistor is connected to
v cC bus, and drain electrode be connected to the transistorized drain electrode of N-channel MOS, the transistorized source electrode of this N-channel MOS is the input line of CMOS chip, and will be connected to the output of TTL.The 5th the transistorized grid of N-channel MOS is connected to a wire that connects the NPN transistor emitter of non-Darlington connection.This connection provides a source electrode that approaches stable 2.4V, as a 5th N channel gate bus, and the right grid of other voltage transitions that can be used for setovering.The cmos switch input that derives from drain electrode/drain electrode connection of complementary pair comprises P raceway groove
the N-channel MOS transistor of current source mos transistor and connection, its source electrode is connected to TTL output.
Above and other object of the present invention, characteristic and with the obvious advantage, will be from more specifically describing and embody invention below, as accompanying drawing.
The level shifter interface circuit 201120501463.8 of the TTL/CMOS RS 232 of contrast patent documentation: CN202353545U based on hot plug.
Accompanying drawing explanation:
Fig. 1 is an electrical schematic diagram of interface circuit of the present invention.
Embodiment:
According to unique figure,
v cC bus (being connected to one provides from 5 to 15V power supply, is generally 15V) is connected to NPN transistor Q3, Q4, the collector electrode of Q5 and Q6.Base stage or lead-in wire Q3 and Q6 link together by wire 2, and wire 2 has connected the drain lead of P channel MOS transistor Q1 equally.The source lead of MOS transistor Q1 is connected to
v cC bus 1.Q1 and Q2(electric pressure converter be the bottom at unique figure to one of them) be the P channel MOS transistor conduct of coupling
current source.MOS transistor Q1 forward bias NPN transistor Q3 and Q6 and contribute to the drain current of MOS N channel transistor Q9 to be used as a current sink.
NPN transistor Q3, Q4 and Q5 common collector link together, and by N-channel MOS transistor Q8 and Q7, the emitter of Darlington arrangement and Q3 and Q4 is connected respectively to earth potential, and this is the same as with Q9 current sink.The emitter of NPN transistor Q5 is connected to earth potential by the resistance R of a 110K.Unearthed one end of resistance R of 110K is connected to a public wire 3 to N-channel MOS transistor Q7, Q8, the grid of Q9 and Q10, and the whole ground connection of source electrode of N-channel MOS transistor Q10.
Therefore, 110K resistance R is connected to N-channel MOS transistor Q7, Q8, and the grid of Q9 and Q10, at lead-in wire, 3 places provide a common bias.Voltage at bias lead 3 places be 110K resistance two ends by from
v cC arrive the caused voltage drop of electric current of the collector and emitter that passes through NPN transistor Q5 of earth potential.At N-channel MOS device Q7, Q8, Q9 and Q10(
v tHN ) grid at the voltage threshold of bias lead 3 owing to passing through
110K ohmthe voltage drop of resistance R, forward bias N-channel MOS transistor Q7, Q8, Q9 and Q10.Leakage current by Q7 is from by Q4's
v cC , the leakage current by Q8 is from by Q3's
v cC , the leakage current by Q9 from
current source p channel transistor Q1, its drain electrode is connected to the base stage of Q3 and Q6 equally by wire 2.The stabilising condenser C of a 5pf is connected between earth potential and Q3 and the base stage of Q6 and the formed common point of lead-in wire of the drain electrode of Q1 and Q9.
The voltage that comes from the Q9 grid of common bias lead-in wire 3
v tHN maintain a leakage current by Q9(as a current sink)
most of electric current in electric current comes from current source Q1.Bias lead 3 be also connected to N channel transistor Q10 forward bias Q10 adjust from
v cC the electric current that passes through transistor Q6, thereby as the current offset of a NPN transistor Q6.Article one, gate bias bus or wire 4 are connected to the emitter from NPN transistor Q6, and it is connected to the drain lead of N-channel MOS transistor Q10.
Current regulator (Darlington) comprises Q3, and the function of Q4 and Q5 is to drive gate bias wire 3 to produce a level thereon, to allow Q9 delivery
(
time
v tHN ) 1V normally.The level of wire 4 normally twice base-emitter node (2) and, wherein
v bE be about 0.7V and add the gate bias in bias lead 3
v tHN be approximately 1V.Therefore, maintain the magnitude of voltage in gate bias bus or on wire 4, for all suitable
v cC value be about 2.4V.Electric current adjusting/gate bias generator in dotted line frame 7 described above can be as a circuit or as the part of a CMOS integrated circuit independently.Three ends (as shown in dotted line frame 7) of this part circuit will be
v cC , earth potential and gate bias wire 4.
Although only have a voltage transitions to be presented at circuit part dotted line frame 8, when the many CMOS door inputs of needs, other voltage conversion circuit part can be added to switch.Each voltage conversion circuit needs four ends,
v cC , earth potential, to the terminal 5 of TTL output with to the terminal 6 of CMOS input gate.
Electric pressure converter (dotted line frame 8) comprises
the current source of current source P channel MOS transistor Q2, its grounded-grid, also has a N-channel MOS transistor Q11, and its grid is connected to gate bias bus or wire 4.This makes Q11's
v tHN equal with reference to N-channel MOS Q9.This makes
v tHN offset, and make switching point in input point, node 5, becomes 2
v bE , be TTL logic threshold just, and there is identical temperature characterisitic.The source lead of Q2 is connected to
v cC , its drain electrode is connected to the drain electrode of Q11.The source electrode of Q11 is connected to terminal 5, and as the input that comes from a TTL output.Public drain line between Q2 and Q11 is connected to terminal 6, as CMOS door input lead.
Logical zero work: as mentioned above, Q2 and Q1 match, and are all the current sources being used as.The grid of N channel transistor Q11 remains on 2
v bE+ v tHN or about 2.4V.When terminal 5 is at output low level () (logical zero=0.2 is to 0.4V) from TTL output, because gate voltage is 2 to 2.2V, Q11 conducting.Therefore,, when Q11 opens or conducting, its current sink of conduct absorbs the electric current of all Q2.Voltage at terminal 6 places is CMOS input, equals now the leakage/source pressure drop by Q11, is low-voltage state (" 0 ") in other words conj.or perhaps for the logic on chip.
Logical one work: when the output of TTL circuit is high level, logical one (
v oH ),
v oH be provided to terminal 5, minimum is that 2.4V is to 3.4V.The effective voltage in the grid source of Q11 is from zero to-1 in this case.This closes Q11, and therefore the voltage at terminal 6 is the input of CMOS door, rises to very approaching
v cC , therefore brought up a reliable switch and guaranteed, far above cmos switch threshold value.
Those skilled in the art also will appreciate that, the present invention can be different from above-mentioned example, and described example only for illustrative purposes, rather than restrictive, and the present invention is only defined by the claims scope.
Claims (2)
1. one kind provides the interface circuit of voltage transitions for TTL and cmos circuit, it is characterized in that: interface circuit, the interface circuit of the input that outputs to a cmos circuit of a TTL circuit of being particularly used for being coupled comprises: electric current regulate with the device that produces bias voltage source, be connected to the bias voltage source of described electric current adjusting and bias voltage generation device, be used for any input voltage receiving from the output of a TTL circuit to be transformed into a level that is applicable to driving a cmos circuit, and the input voltage signal receiving with output from a TTL circuit is consistent, electric current regulates and produces the device of bias voltage source, comprise bipolar transistor device, it has a plurality of transistor electric coupling in each base stage, in order to regulate electric current and the bias voltage output in a definite value to be provided, and MOS transistor device has many MOS transistor that are connected to described many transistorized electrodes of bipolar transistor device, for described bipolar transistor device provides a current absorption end, bipolar transistor device comprises many NPN transistor devices, and the MOS transistor of each MOS transistor device is electrically coupled to the emitter of the bipolar transistor of a different bipolar transistor device, described many NPN transistor devices comprise four NPN transistor devices, and wherein three are connected as common collector, darlington transistor, and a base stage in Darlington NPN transistor is connected to the 4th NPN transistor device, wherein the collector electrode of four NPN transistor is connected to a voltage source
v cc , MOS transistor device comprises many N-channel MOS transistor units, interface circuit comprises a resistance that is connected to the grid of each N-channel MOS transistor unit, interface circuit comprises current source P channel MOS transistor device and an electric capacity that is connected to the drain electrode of current source P raceway groove, N channel transistor device also comprises four N-channel MOS transistor units, interface circuit also comprises a current source P channel MOS transistor device, and described current source P channel MOS transistor device is connected to one of them of N-channel MOS transistor unit, wherein current source P channel MOS transistor device is connected to the drain electrode of one of described N-channel MOS transistor unit, the source electrode of described current source P channel MOS transistor device be connected to a voltage source (
v cc ), wherein bipolar transistor device comprises many NPN transistor devices, wherein NPN transistor device comprises four N-channel MOS transistor units, and wherein three are connected as common collector, darlington transistor, and a base stage in Darlington NPN transistor is connected to the 4th NPN transistor device, wherein the collector electrode of four NPN transistor is connected to a voltage source
v cc , interface circuit comprises a resistance that is connected to the grid of each N-channel MOS transistor unit, interface circuit comprises current source P channel MOS transistor device and an electric capacity that is connected to the drain electrode of current source P raceway groove, wherein resistance is connected to one of them emitter of these NPN transistor devices, wherein resistance is connected between one of them emitter of NPN transistor device that earth potential and darlington transistor connect, interface circuit comprises that a current source P channel MOS transistor device is connected to one of them of those described N-channel MOS transistor units, current source P channel MOS transistor device has a gate electrode to be connected to earth potential, the source electrode of current source P channel MOS transistor device be connected to a voltage source (
v cc ), wherein the emitter of each NPN transistor device is connected to a drain electrode of N-channel MOS transistor unit, wherein the source electrode of each N-channel MOS transistor unit is connected to earth potential.
2. according to claim 1ly a kind ofly provide the interface circuit of voltage transitions for TTL and cmos circuit, it is characterized in that: an interface circuit, the interface circuit of the input that outputs to a cmos circuit of a TTL circuit of being particularly used for being coupled comprises: electric current regulate with the device that produces bias voltage source, be connected to the bias voltage source of described electric current adjusting and bias voltage generation device, be used for any input voltage receiving from the output of a TTL circuit to be transformed into a voltage levvl that is applicable to driving a cmos circuit, and the input voltage signal receiving with output from a TTL circuit is consistent, described voltage conversion device comprises a MOS transistor compensation device, one of them grid of MOS transistor compensation device is electrically coupled to the output that electric current regulated and produced the device of bias voltage source, one of them electrode of MOS transistor compensation device is electrically coupled to the electrode of corresponding another MOS transistor compensation device, one of them comprises a current source P channel MOS transistor device MOS transistor compensation device, and the MOS transistor compensation device described in another comprises a N-channel MOS transistor switch device, and it is connected in series to described current source P channel MOS transistor device, wherein the drain electrode of current source P channel MOS transistor device is connected to the drain electrode of described N-channel MOS switching transistor arrangement, wherein the grid of current source P channel MOS transistor device is connected to earth potential, the source electrode of current source P channel MOS transistor device be connected to a voltage source (
v cc ), wherein the source electrode of N-channel MOS switching transistor is connected to a TTL output, the drain electrode of N-channel MOS switching transistor is connected to a CMOS input equally, the transistorized grid of N-channel MOS is connected to bias voltage source and the bias voltage generator means of described current regulator, and bias voltage is greatly about 2.4 volts, wherein the device of electric current adjusting and generation bias voltage source comprises bipolar transistor device, it has a plurality of transistor electric coupling in each base stage, in order to regulate electric current and the bias voltage output in a definite value to be provided, and MOS transistor device has many MOS transistor that are connected to described many transistorized electrodes of bipolar transistor device, for described bipolar transistor device provides a current absorption end, shown in MOS transistor device comprise some N-channel MOS transistor units, wherein the device of electric current adjusting and generation bias voltage source comprises bipolar transistor device, it has a plurality of transistor electric coupling in each base stage, in order to regulate electric current and the bias voltage output in a definite value to be provided, and MOS transistor device has many MOS transistor that are connected to described many transistorized electrodes of bipolar transistor device, for described bipolar transistor device provides a current absorption end, wherein bipolar transistor device comprises some NPN transistor devices, these NPN transistor devices comprise four NPN transistor devices, wherein three are connected as common collector, darlington transistor, a base stage in Darlington NPN transistor is connected to the 4th NPN transistor device, and wherein the collector electrode of four NPN transistor is connected to a voltage source
v cc .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310541698.3A CN103607193A (en) | 2013-11-06 | 2013-11-06 | Interface circuit which provides voltage conversion for TTL and CMOS circuits |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310541698.3A CN103607193A (en) | 2013-11-06 | 2013-11-06 | Interface circuit which provides voltage conversion for TTL and CMOS circuits |
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| CN103607193A true CN103607193A (en) | 2014-02-26 |
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| CN201310541698.3A Pending CN103607193A (en) | 2013-11-06 | 2013-11-06 | Interface circuit which provides voltage conversion for TTL and CMOS circuits |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4128775A (en) * | 1977-06-22 | 1978-12-05 | National Semiconductor Corporation | Voltage translator for interfacing TTL and CMOS circuits |
| JPH05243955A (en) * | 1992-03-02 | 1993-09-21 | Fujitsu Ltd | Ecl input circuit |
| CN101256421A (en) * | 2007-12-27 | 2008-09-03 | 北京中星微电子有限公司 | Current limitation circuit as well as voltage regulator and DC-DC converter including the same |
| CN102467885A (en) * | 2010-11-11 | 2012-05-23 | 美信集成产品公司 | LED backlight driver |
| CN103134977A (en) * | 2011-11-28 | 2013-06-05 | 统达能源股份有限公司 | Large current detection device and large current detection method |
-
2013
- 2013-11-06 CN CN201310541698.3A patent/CN103607193A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4128775A (en) * | 1977-06-22 | 1978-12-05 | National Semiconductor Corporation | Voltage translator for interfacing TTL and CMOS circuits |
| JPH05243955A (en) * | 1992-03-02 | 1993-09-21 | Fujitsu Ltd | Ecl input circuit |
| CN101256421A (en) * | 2007-12-27 | 2008-09-03 | 北京中星微电子有限公司 | Current limitation circuit as well as voltage regulator and DC-DC converter including the same |
| CN102467885A (en) * | 2010-11-11 | 2012-05-23 | 美信集成产品公司 | LED backlight driver |
| CN103134977A (en) * | 2011-11-28 | 2013-06-05 | 统达能源股份有限公司 | Large current detection device and large current detection method |
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Application publication date: 20140226 |
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