CN103595407A - Fractional frequency division circuit and method based on programmable continuous mode changing frequency divider - Google Patents
Fractional frequency division circuit and method based on programmable continuous mode changing frequency divider Download PDFInfo
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- CN103595407A CN103595407A CN201310571682.7A CN201310571682A CN103595407A CN 103595407 A CN103595407 A CN 103595407A CN 201310571682 A CN201310571682 A CN 201310571682A CN 103595407 A CN103595407 A CN 103595407A
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- frequency divider
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Abstract
The invention discloses a fractional frequency division circuit based on a programmable continuous mode changing frequency divider. The fractional frequency division circuit comprises an FPGA circuit and the programmable continuous mode changing frequency divider. A sigma-delta modulator is arranged in the FPGA circuit to generate a modulation signal. The frequency dividing ratio is changed by controlling the programmable continuous mode changing frequency divider through a mode line; the programmable continuous mode changing frequency divider carries out frequency dividing on an input signal and the input signal is divided into two paths, wherein one path of signal serves as a fractional frequency divider output signal and the other path of signal serves a control clock of the sigma-delta modulator and is input into the FPGA circuit. According to the fractional frequency division circuit based on the programmable continuous mode changing frequency divider, fractional frequency division can be performed on the input signal of DC-14GHz with the fractional frequency division circuit and the frequency of the output signal can reach the maximum 270MHz. The ordinary FPGA circuit can be enough to carry out fractional frequency division and used in a fractional phase-locked loop, so that the phase demodulation frequency can be greatly improved, and therefore phase noise output by the fractional phase-locked loop is lowered.
Description
Technical field
The present invention relates to technical field of measurement and test, particularly a kind of fractional frequency division circuit, also relates to a kind of decimal frequency dividing method.
Background technology
Along with the development of microwave technology, more and more higher to the phase noise requirement of microwave test signal, in the urgent need to low noise frequency synthesis technique is studied, and phase-locked loop is one of major way of current frequency synthesis.An effective means improving phase-locked loop output phase noise is to improve phase demodulation frequency, improves phase demodulation frequency and means raising fractional frequency division circuit input signal frequency, requires fractional frequency division circuit to carry out fractional frequency division processing to high-frequency signal.
Figure 1 shows that existing fractional frequency division circuit theory diagrams, this fractional frequency division circuit adopts the preposition dual-mode frequency divider 11 of ÷ N/N+1 to realize fractional frequency division with the mode of FPGA circuit 12 cascades, and preposition dual-mode frequency divider 11 is first to input signal f
iNcarry out pre-frequency division and obtain f
pRE, then in FPGA circuit 12, pass through programmable frequency divider 13 and 14 couples of f of sigma-delta modulator
pREfurther frequency division obtains f
oUTthereby, realized fractional frequency division.For example, realize 160.1 frequency dividing ratios, need to carry out 160 frequency divisions 9 times, 1 161 frequency division, average divide is than being (160 * 9+161)/10=160.1, preposition dual-mode frequency divider 11 adopts ÷ 8/9 frequency divider, and 160 frequency divisions are realized by carrying out 20 8 frequency divisions, and 161 frequency divisions are realized by carrying out 19 8 frequency divisions and 19 frequency division.
The minimum frequency dividing ratio of existing fractional frequency division circuit is (N-1) * N, dual-mode frequency divider is ÷ 8/9 substantially in the market, ÷ 16/17, ÷ 32/33, ÷ 64/65, be used in high phase demodulation phase-locked loop, decimal frequency divider output may be up to 50MHz, and frequency input signal is generally several GHz, can only select like this ÷ 8/9 frequency divider, ÷ 8/9 output signal of frequency divider reaches hundreds of MHz and even surpasses 1GHz, high frequency like this is carried out back-end processing with FPGA circuit and is just become very difficult, can allow at present the FPGA circuit of high-frequency input signal so seldom, price is also very high.
Summary of the invention
The present invention proposes a kind of fractional frequency division circuit and method based on continuous change mould frequency divider able to programme, needs the problem of high speed FPGA circuit while having solved existing fractional frequency division circuit for high phase demodulation phase-locked loop.
Technical scheme of the present invention is achieved in that
A fractional frequency division circuit for continuous change mould frequency divider able to programme, comprising: FPGA circuit and continuous change mould frequency divider able to programme;
In described FPGA circuit, be provided with sigma-delta modulator, produce modulation signal, by mode line, control described continuous change mould frequency divider able to programme and change frequency dividing ratio;
Described continuous change mould frequency divider able to programme carries out frequency division to input signal, and output signal is divided into two-way ，Yi road and as the control clock of sigma-delta modulator, is input to FPGA circuit as decimal frequency divider output signal ，Yi road.
Alternatively, described sigma-delta modulator is 4 rank sigma-delta modulators.
Alternatively, the quantity of described mode line is 9.
Alternatively, the frequency dividing ratio of described continuous change mould frequency divider able to programme into/8 ,/9 ... / 511 continuous integral number.
Alternatively, the UXN14M9P chip that described continuous change mould frequency divider able to programme is CENTELLAX company.
Alternatively, the EP3C25E144C8 chip that described FPGA circuit is altera corp.
The present invention also provides a kind of decimal frequency dividing method based on continuous change mould frequency divider able to programme, comprises the following steps:
Step (a), produces modulation signal by the sigma-delta modulator in FPGA circuit, and described modulation signal is controlled continuous change mould frequency divider able to programme and constantly changed frequency dividing ratio, and input signal is carried out to frequency division;
Step (b), the output signal after frequency division is divided into two-way ，Yi road and as the control clock of sigma-delta modulator, enters FPGA circuit as output signal ，Yi road.
Alternatively, in described step (a), by 9 root mode lines, described modulation signal is transferred to described continuous change mould frequency divider able to programme.
Alternatively, the frequency dividing ratio of described continuous change mould frequency divider able to programme into/8 ,/9 ... / 511 continuous integral number.
The invention has the beneficial effects as follows:
(1) can carry out fractional frequency division to the input signal of DC-14GHz, the high energy of output signal frequency reaches 270MHz;
(2) adopt common FPGA circuit just can realize, for fractional phase lock loop, can improve greatly phase demodulation frequency, thereby improve the phase noise of fractional phase lock loop output.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the theory diagram of existing fractional frequency division circuit;
Fig. 2 is the control block diagram that the present invention is based on the fractional frequency division circuit of continuous change mould frequency divider able to programme;
Fig. 3 is the flow chart that the present invention is based on the decimal frequency dividing method of continuous change mould frequency divider able to programme.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
What existing fractional frequency division circuit adopted is that preposition multi-modulus frequency divider and the combination of FPGA circuit realize, and first by preposition multi-modulus frequency divider, input signal is carried out to pre-frequency division, then in FPGA circuit, further carries out fractional frequency division.Because preposition multi-modulus frequency divider frequency dividing ratio is comparatively single and ratio is less, if frequency input signal is higher, in FPGA circuit, need signal frequency to be processed corresponding higher, realize comparatively difficulty.
The present invention adopts continuous change mould frequency divider able to programme to realize fractional frequency division, the output that becomes continuously mould frequency divider be the output of decimal frequency divider, need in FPGA circuit, not do further frequency division processes, the signal frequency of processing in FPGA circuit is like this very low, general FPGA circuit just can be realized, and is applicable to the design of high phase demodulation fractional frequency-division phase-locked loop.
As shown in Figure 2, fractional frequency division circuit based on continuous change mould frequency divider able to programme of the present invention comprises FPGA circuit 21 and continuous change mould frequency divider 24 able to programme, in FPGA circuit 21, be provided with sigma-delta modulator 22, the exponent number of sigma-delta modulator 22 is 4 rank, produce modulation signal, by 9 root mode lines 23, control continuous change mould frequency divider 24 able to programme and constantly change frequency dividing ratio, to input signal f
iNcarry out frequency division, the frequency dividing ratio of continuous change mould frequency divider 24 able to programme into/8 ,/9 ... / 511 continuous integral number; The output signal f of continuous change mould frequency divider 24 able to programme
oUTbe divided into two-way ，Yi road and enter in FPGA circuit 21 as decimal frequency divider output signal ，Yi road, as the control clock of sigma-delta modulator 22.
Under instantaneous state, 24 couples of input signal f of continuous change mould frequency divider able to programme
iNwhat carry out is integral frequency divisioil, but the effect due to sigma-delta modulator 22, the frequency dividing ratio of continuous change mould frequency divider 24 able to programme is in continuous change, from long-time statistical analysis, what 24 pairs of input signals of continuous change mould frequency divider able to programme carried out is fractional frequency division, it is output as fractional frequency division signal, need in FPGA circuit 21, not make further frequency division and process.
Provide a specific embodiment according to the fractional frequency division circuit based on continuous change mould frequency divider able to programme of the present invention below, in the present embodiment, the EP3C25E144C8 chip of FPGA circuit 21Wei altera corp, the UXN14M9P chip of continuous change mould frequency divider 24Wei CENTELLAX able to programme company.For example 5GHz signal is carried out to 100.1 frequency divisions, adopt 4 rank sigma-delta modulators, the instantaneous frequency dividing ratio of continuous change mould frequency divider able to programme changes between 93-108.Due to input signal f
iNfor 5GHz microwave signal, its cycle is 0.2ns, supposes that first frequency dividing ratio that sigma-delta modulator produces is 95, after 95 input signal cycle, and the signal f of a complete cycle of continuous change mould frequency divider output able to programme
oUT, the cycle is 18ns, output signal f
oUTyou Yi road signal enters in FPGA circuit, complete a frequency division cycle after, output signal f
oUTtrigger sigma-delta modulator and enter next operating state, thereby change the frequency dividing ratio of continuous change mould frequency divider able to programme, further change output signal f
oUTthe instantaneous cycle.Under the continuous firing of sigma-delta modulator, output signal f
oUTthe instantaneous cycle can between 19.6ns-21.6ns, change, pass through so a plurality of all after dates, output signal f
oUTaverage period be 20.02ns, thereby realized input signal f
iN100.1 fractional frequency divisions.
The present invention also provides a kind of decimal frequency dividing method based on continuous change mould frequency divider able to programme, as shown in Figure 3, comprise the following steps: step (a), by the sigma-delta modulator in FPGA circuit, produce modulation signal, modulation signal is controlled continuous change mould frequency divider able to programme and is constantly changed frequency dividing ratio, and input signal is carried out to frequency division; Step (b), the output signal after frequency division is divided into two-way ，Yi road and as the control clock of sigma-delta modulator, enters FPGA circuit as output signal ，Yi road.
Preferably, in above-mentioned steps (a), by 9 root mode lines, modulation signal is transferred to continuous change mould frequency divider able to programme, modulation signal is controlled continuous change mould frequency divider able to programme and is constantly changed frequency dividing ratio, the frequency dividing ratio of continuous change mould frequency divider able to programme into/8 ,/9 ... / 511 continuous integral number.
Adopt fractional frequency division circuit and the method based on continuous change mould frequency divider able to programme of the present invention, can carry out fractional frequency division to the input signal of DC-14GHz, the high energy of output signal frequency reaches 270MHz, adopt common FPGA circuit just can realize, for fractional phase lock loop, can improve greatly phase demodulation frequency, thereby improve the phase noise of fractional phase lock loop output.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (9)
1. the fractional frequency division circuit based on continuous change mould frequency divider able to programme, is characterized in that, comprising: FPGA circuit and continuous change mould frequency divider able to programme;
In described FPGA circuit, be provided with sigma-delta modulator, produce modulation signal, by mode line, control described continuous change mould frequency divider able to programme and change frequency dividing ratio;
Described continuous change mould frequency divider able to programme carries out frequency division to input signal, and output signal is divided into two-way ，Yi road and as the control clock of sigma-delta modulator, is input to FPGA circuit as decimal frequency divider output signal ，Yi road.
2. the fractional frequency division circuit based on continuous change mould frequency divider able to programme as claimed in claim 1, is characterized in that, described sigma-delta modulator is 4 rank sigma-delta modulators.
3. the fractional frequency division circuit based on continuous change mould frequency divider able to programme as claimed in claim 1, is characterized in that, the quantity of described mode line is 9.
4. the fractional frequency division circuit based on continuous change mould frequency divider able to programme as claimed in claim 3, is characterized in that, the frequency dividing ratio of described continuous change mould frequency divider able to programme into/8 ,/9 ... / 511 continuous integral number.
5. the fractional frequency division circuit based on continuous change mould frequency divider able to programme as claimed in claim 4, is characterized in that, the UXN14M9P chip that described continuous change mould frequency divider able to programme is CENTELLAX company.
6. the fractional frequency division circuit based on continuous change mould frequency divider able to programme as claimed in claim 2, is characterized in that, the EP3C25E144C8 chip that described FPGA circuit is altera corp.
7. the decimal frequency dividing method based on continuous change mould frequency divider able to programme, is characterized in that, comprises the following steps:
Step (a), produces modulation signal by the sigma-delta modulator in FPGA circuit, and described modulation signal is controlled continuous change mould frequency divider able to programme and constantly changed frequency dividing ratio, and input signal is carried out to frequency division;
Step (b), the output signal after frequency division is divided into two-way ，Yi road and as the control clock of sigma-delta modulator, enters FPGA circuit as output signal ，Yi road.
8. a kind of decimal frequency dividing method based on continuous change mould frequency divider able to programme as claimed in claim 7, is characterized in that, in described step (a), by 9 root mode lines, described modulation signal is transferred to described continuous change mould frequency divider able to programme.
9. a kind of decimal frequency dividing method based on continuous change mould frequency divider able to programme as claimed in claim 8, is characterized in that, the frequency dividing ratio of described continuous change mould frequency divider able to programme into/8 ,/9 ... / 511 continuous integral number.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104038214A (en) * | 2014-06-05 | 2014-09-10 | 中国电子科技集团公司第四十一研究所 | Generation device and method of ultralow-phase noise phase discrimination reference signal |
| CN105634484A (en) * | 2015-12-24 | 2016-06-01 | 熊猫电子集团有限公司 | Frequency modulation continuous wave signal source based on external triggering |
| CN106374914A (en) * | 2015-07-23 | 2017-02-01 | 中国科学院电子学研究所 | Programmable frequency divider |
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| US6961400B1 (en) * | 2001-08-23 | 2005-11-01 | National Semiconductor Corporation | Automatic frequency correction apparatus and method of operation |
| CN102340308A (en) * | 2011-10-13 | 2012-02-01 | 电子科技大学 | Fractional-N frequency synthesizer |
| CN103001631A (en) * | 2011-09-16 | 2013-03-27 | 英飞凌科技奥地利有限公司 | Fractional-n phase locked loop |
| CN103178834A (en) * | 2013-03-07 | 2013-06-26 | 上海山景集成电路股份有限公司 | Fractional frequency division system |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6961400B1 (en) * | 2001-08-23 | 2005-11-01 | National Semiconductor Corporation | Automatic frequency correction apparatus and method of operation |
| CN103001631A (en) * | 2011-09-16 | 2013-03-27 | 英飞凌科技奥地利有限公司 | Fractional-n phase locked loop |
| CN102340308A (en) * | 2011-10-13 | 2012-02-01 | 电子科技大学 | Fractional-N frequency synthesizer |
| CN103178834A (en) * | 2013-03-07 | 2013-06-26 | 上海山景集成电路股份有限公司 | Fractional frequency division system |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104038214A (en) * | 2014-06-05 | 2014-09-10 | 中国电子科技集团公司第四十一研究所 | Generation device and method of ultralow-phase noise phase discrimination reference signal |
| CN104038214B (en) * | 2014-06-05 | 2018-03-13 | 中国电子科技集团公司第四十一研究所 | A kind of generating means and method of extremely low phase noise phase demodulation reference signal |
| CN106374914A (en) * | 2015-07-23 | 2017-02-01 | 中国科学院电子学研究所 | Programmable frequency divider |
| CN105634484A (en) * | 2015-12-24 | 2016-06-01 | 熊猫电子集团有限公司 | Frequency modulation continuous wave signal source based on external triggering |
| CN105634484B (en) * | 2015-12-24 | 2019-01-08 | 熊猫电子集团有限公司 | Frequency-modulated continuous-wave signals source based on external trigger |
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Effective date of registration: 20190308 Address after: 266000 No. 98 Xiangjiang Road, Huangdao District, Qingdao City, Shandong Province Patentee after: China Electronics Technology Instrument and Meter Co., Ltd. Address before: 266555 No. 98 Xiangjiang Road, Qingdao economic and Technological Development Zone, Shandong Patentee before: The 41st Institute of CETC |
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Address after: Huangdao Xiangjiang Road 266555 Shandong city of Qingdao Province, No. 98 Patentee after: CLP kesiyi Technology Co.,Ltd. Address before: 266000 No. 98 Xiangjiang Road, Huangdao District, Shandong, Qingdao Patentee before: CHINA ELECTRONIC TECHNOLOGY INSTRUMENTS Co.,Ltd. |