CN103594123B - Non-volatility memorizer and correcting and regulating method thereof - Google Patents
Non-volatility memorizer and correcting and regulating method thereof Download PDFInfo
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- CN103594123B CN103594123B CN201310625597.4A CN201310625597A CN103594123B CN 103594123 B CN103594123 B CN 103594123B CN 201310625597 A CN201310625597 A CN 201310625597A CN 103594123 B CN103594123 B CN 103594123B
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Abstract
The invention provides a kind of non-volatility memorizer and correcting and regulating method thereof, including: configuration information memory element, control logical block, test pattern control module and testing circuit, testing circuit is added in the circuit of traditional non-volatility memorizer, after non-volatility memorizer powers on, testing circuit is started working, detect the work state information of non-volatility memorizer in real time, and generate corresponding school tune information according to described work state information, then adjust information that non-volatility memorizer is carried out school tune further according to described school, owing to test circuit need not connect external equipment input external command, school can be generated in real time and adjust information, it is achieved thereby that the automatic school of non-volatility memorizer is adjusted, it is greatly saved the testing time, reduce testing cost.
Description
Technical field
The present invention relates to a kind of non-volatility memorizer and correcting and regulating method thereof, belong to field of semiconductor memory.
Background technology
Non-volatility memorizer owing to being affected by factors such as the variations in temperature of process corner and working environment, its
Performance can produce the voltage in a certain amount of skew, i.e. non-volatile memory circuit, electric current etc. and can occur
Change, accordingly, it would be desirable to non-volatility memorizer carries out school tune, just can make non-volatility memorizer reach
Initial designs index request.
Traditional non-volatile memory circuit structure is as it is shown in figure 1, specifically include that storage array (Cell
Array), configuration information memory element (NVR), row decoding circuit (X decoder), array decoding circuit
(Y decoder), control logic (Control Logic), inputoutput buffer (IO Buffer), spirit
Quick amplifier (SA), address buffer (Address Buffer), test pattern control module (Test Mode),
Voltage x current external interface (V/I Monitor) etc..
Traditional non-volatility memorizer is carrying out school timing, it is necessary to by with voltage x current external interface even
The external equipment input instruction connect, makes non-volatility memorizer enter test pattern and obtain school tune information,
Then information is adjusted to carry out school tune further according to the school obtained.This correcting and regulating method needs constantly to input from outside to refer to
Order, the testing time is long, and test equipment and cost of labor are of a relatively high.
Summary of the invention
For solving above-mentioned technical problem, the present invention provides a kind of non-volatility memorizer and correcting and regulating method thereof,
In the circuit of traditional non-volatility memorizer, add testing circuit, detected by testing circuit non-in real time
The work state information of volatile storage, and generate corresponding school tune letter according to described work state information
Breath, then adjusts information that non-volatility memorizer is carried out school tune further according to described school, waves it is achieved thereby that non-
The automatic school of the property sent out memorizer is adjusted, and technical scheme is as follows:
A kind of non-volatility memorizer, including: configuration information memory element, control logical block, test
Mode control module and testing circuit, wherein:
Described testing circuit is connected with described control logical block, detects non-volatility memorizer in real time
Work state information, generate corresponding school according to described work state information and adjust information, and by described school
Tune information exports to controlling logical block；
Described control logical block, for described school tune information is compared with standard reference information, when
When described school adjusts information and standard reference information inconsistent, adjust information to non-volatile holographic storage according to described school
Device carries out school tune, and wherein, described standard reference information is the original state letter of described non-volatility memorizer
Breath；
Test pattern control module, is used for controlling described control logical block and described school tune information is stored in
Described configuration information memory element.
Preferably, described work state information is process corner during non-volatility memorizer work and temperature shape
State information.
Preferably, described control logical block, it is further used for when described school adjusts information to believe with canonical reference
When ceasing inconsistent, producing control signal, described control signal is used for activating described test pattern control module.
Preferably, described school adjust information be the electric current in circuit whole to non-volatility memorizer, voltage,
Capacitor's capacity or metal-oxide-semiconductor quantity carry out the information of school tune.
Preferably, described test circuit includes: the first current source, the second current source, the first PMOS,
Info encoder is adjusted in first NMOS tube, voltage-current converter, current comparator, bank of latches and school,
Wherein:
The input of described first current source is connected with power supply, and the outfan of described first current source is with described
The source electrode of the first PMOS is connected, and the drain electrode of described first PMOS is connected with earth terminal, and described the
Grid and the drain electrode of one PMOS connect；
The input of described second current source is connected with power supply, and the outfan of described second current source is with described
The drain electrode of the first NMOS tube is connected, and the source electrode of described first NMOS tube is connected with earth terminal, and described the
The drain and gate of one NMOS tube connects；
The source electrode of described first PMOS is connected with the input of described voltage-current converter, and being used for will
The voltage of described first PMOS source electrode is converted to the first electric current；
The first input end of described current comparator is connected with the outfan of described voltage-current converter, institute
The grid of the second input and described first NMOS tube of stating current comparator is connected, and described current ratio is relatively
Device is used for described first current ratio mirror image obtains n the first image current, and by described first
The n that current ratio mirror image in NMOS tube obtains second image current, and by described n the first mirror
Image current compares with corresponding described n the second image current respectively, obtains n comparative result,
Wherein, n is the positive integer more than 2；
The input of described bank of latches is connected with n outfan of described current comparator, is used for latching
N comparative result of described current comparator output；
Described school adjusts the input of info encoder to be connected with the outfan of described bank of latches, and described school is adjusted
Info encoder generates numeral school tune information for described n comparative result carries out coding, and is supplied to
Described control logical block.
Preferably, described voltage-current converter includes: the second NMOS tube and the second PMOS,
Wherein:
The input that grid is described voltage-current converter of described second NMOS tube, described second
The source ground of NMOS tube, described second NMOS tube drain electrode and the drain electrode phase of described second PMOS
Even, the drain electrode of described second PMOS connects with grid, and the grid of described second PMOS is described
The outfan of voltage-current converter.
Preferably, described current comparator includes: n PMOS and n NMOS tube, and n is
Integer more than 2, wherein:
The source electrode of n PMOS is all connected with DC source, and the grid of n PMOS is connected conduct
The first input end of current comparator, the source electrode of n NMOS tube is all connected with earth terminal, n NMOS
Connected the second input as current comparator of the grid of pipe；
The drain electrode phase of the NMOS tube that the drain electrode of n PMOS is corresponding with n NMOS tube respectively
Continuous cropping is the outfan of described current comparator.
A kind of correcting and regulating method, is applied to non-volatility memorizer, including:
Detect the work state information of described non-volatility memorizer, and raw according to described work state information
Information is adjusted in the school becoming corresponding；
Information and standard reference information are adjusted in relatively described school, when described school adjusts information with standard reference information not
Time consistent, described school tune information is stored in configuration information memory element；
Adjust information that described non-volatility memorizer is carried out school tune according to described school.
Preferably, also include:
Read the school in described configuration information memory element and adjust information, adjust information to non-volatile according to described school
Property memorizer carries out school tune.
The technical scheme provided from the above present invention, the present invention provide non-volatility memorizer and
Correcting and regulating method, adds testing circuit in the circuit of traditional non-volatility memorizer, when non-volatile
After memorizer powers on, testing circuit is started working, in real time the duty letter of detection non-volatility memorizer
Breath, and generate corresponding school tune information according to described work state information, then adjust letter further according to described school
Breath carries out school tune to non-volatility memorizer, owing to test circuit need not connect external equipment input outside
Instruction, can generate school in real time and adjust information, it is achieved thereby that the automatic school of non-volatility memorizer is adjusted, greatly
Save the testing time greatly, reduced testing cost.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present application or technical scheme of the prior art, below will be to reality
Execute the required accompanying drawing used in example or description of the prior art to be briefly described, it should be apparent that below,
Accompanying drawing in description is only some embodiments described in the application, for those of ordinary skill in the art
From the point of view of, on the premise of not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the circuit structure diagram of traditional non-volatility memorizer；
Fig. 2 is the circuit structure diagram of non-volatility memorizer disclosed in the embodiment of the present invention；
Fig. 3 is the structure chart of testing circuit disclosed in the embodiment of the present invention；
Fig. 4 is the flow chart of correcting and regulating method disclosed in the embodiment of the present invention.
Detailed description of the invention
For the technical scheme making those skilled in the art be more fully understood that in the application, below in conjunction with
Accompanying drawing in the embodiment of the present application, clearly and completely retouches the technical scheme in the embodiment of the present application
State, it is clear that described embodiment is only some embodiments of the present application rather than whole enforcement
Example.Based on the embodiment in the application, those of ordinary skill in the art are not before making creative work
Put the every other embodiment obtained, all should belong to the scope of the application protection.
The embodiment of the invention discloses a kind of non-volatility memorizer, its circuit structure is as in figure 2 it is shown, wrap
Include: configuration information memory element 201, the logical block 202 that controls, test pattern control module 203 and survey
Examination circuit 204, compared with traditional non-volatility memorizer, it adds test circuit 204 in circuit,
And test circuit 204 and be connected with controlling logical block 202.
Described test circuit 204, is used for detecting in real time the work state information of non-volatility memorizer, according to
Described work state information generates corresponding school and adjusts information, and adjusts information to export to controlling logic in described school
Unit 202.
Wherein, work state information is process corner during non-volatility memorizer work and state of temperature information,
Information and process corner and the foundation of state of temperature information corresponding relation are adjusted in school, are by PMOS reasonable in design
Pipe P1-Pn and the breadth length ratio of NMOS tube N1-Nn so that under different process corner and operating temperature
School adjusts information different.
Control logical block 202, adjust information to compare with standard reference information for high-ranking officers, when letter is adjusted in school
When breath is inconsistent with standard reference information, adjust information that non-volatility memorizer is carried out school tune according to school, its
In, what standard reference information was corresponding is the initial state information of non-volatility memorizer.
Controlling logical block 202 is according to being stored in the school tune information controlled in logical block internal register
Non-volatility memorizer is carried out school tune.
School in depositor adjusts information to be not longer-term storage, and the school tune information in power-off late register can
Can disappear, accordingly, it would be desirable to high-ranking officers adjust information to be stored in the configuration information memory element of non-volatility memorizer
In 201, this is because the information in configuration information memory element 201 will not be lost after power-off.When non-volatile
After property memorizer powers on again, non-volatility memorizer processor in systems, can join from described
Put and information memory cell 201 reads school tune information, and adjust information that non-volatility memorizer is entered according to school
Row school is adjusted.
Test pattern control module 203, when described school adjusts information and standard reference information inconsistent, controls
Logical block 202 produces control signal and activates test pattern control module 203, makes non-volatility memorizer enter
Enter test pattern, and control described control logical block 202 high-ranking officers and adjust information to be stored in configuration information storage
In unit 201, after having stored, test pattern control module 203 is closed, and non-volatility memorizer moves back
Go out test pattern.
Certainly, in other embodiments, test pattern control module 203 also has other functions, at this not
Repeat again.
The school to non-volatility memorizer described in any embodiment disclosed by the invention is adjusted, and is all to non-
The quantity of electric current, voltage, resistance value, capacitor's capacity or metal-oxide-semiconductor in the whole circuit of volatile storage
Carry out school tune.
The circuit structure of the testing circuit in above-described embodiment is as it is shown on figure 3, specifically include that the first electric current
Source the 301, second current source the 302, first PMOS Pt, the first NMOS tube Nt, voltage-to-current turn
Info encoder 306 is adjusted in parallel operation 303, current comparator 304, bank of latches 305 and school.
The input of the first current source 301 is connected with DC source, the outfan of the first current source 301 with
The source electrode of the first PMOS Pt is connected, and the drain electrode of the first PMOS Pt is connected with earth terminal, and first
Grid and the drain electrode of PMOS Pt connect.
The input of the second current source 302 is connected with power supply, the outfan and first of the second current source 302
The drain electrode of NMOS tube Nt is connected, and the source electrode of the first NMOS tube Nt is connected with earth terminal, a NMOS
The drain and gate of pipe Nt connects.
Concrete, the first current source 301 is identical with the electric current that the second current source 302 produces is It.First
The breadth length ratio of PMOS Pt and the first NMOS tube Nt is identical, and described breadth length ratio is the ditch of MOS device
The ratio of road width and channel length.
When non-volatility memorizer powers on, the output electric current It of described first current source 301 flows through with two
The source electrode of described first PMOS Pt that pole pipe mode connects, the output electricity of described second current source 302
Stream It flows through the drain electrode of described first NMOS tube Nt connected with diode fashion.
Voltage-current converter 303 includes: the second PMOS P0, the second NMOS tube N0, wherein,
The grid of the second NMOS tube P0 is that the input of voltage-current converter 303 connects a described PMOS
The source electrode of pipe Pt, the source ground of the second NMOS tube N0, the drain electrode of the second NMOS tube N0 and the
The drain electrode of two PMOS P0 is connected, and the drain electrode of the second PMOS P0 connects with grid, the 2nd PMOS
The grid of pipe P0 is the outfan of voltage-current converter 303.Voltage-current converter 303 is used for will
The voltage of described first PMOS source electrode is converted to the first electric current Ip0.
Current comparator 304 includes: n PMOS P1, P2 ... Pn, n NMOS tube N1,
N2 ... Nn, and n is the integer more than 2.
The source electrode of n PMOS is all connected with DC source, and the grid of n PMOS is connected conduct
The first input end of current comparator 304, is connected with the outfan of voltage-current converter 303.
The source electrode of n NMOS tube is connected with earth terminal, and the grid of n NMOS tube is connected as electric current
Second input of comparator 304, is connected with the grid of described first NMOS tube Nt.
The drain electrode of n PMOS is connected with the drain electrode of n NMOS tube respectively, n PMOS
The outfan that points of common connection is current comparator with n NMOS tube.
Concrete, the drain electrode of P1 is connected with the drain electrode of N1, and the drain electrode of P2 is connected with the drain electrode of N2, depends on
Secondary analogizing, the drain electrode of Pn is connected with the drain electrode of Nn.
Current comparator 304 for obtaining n the first image current by the first electric current Ip0 scaled mirror
Ip1～Ipn, wherein, Ip1=k1 × Ip0 ... Ipn=kn × Ip0.
Current comparator 304, is additionally operable to obtain the electric current In0 scaled mirror in the first NMOS tube Nt
N the second image current In1～Inn, wherein, the electric current It in In0 and the second current source 302 is identical,
In1=M1 × In0, In2=M2 × In0, the like, Inn=Mn × In0, and, proportionality coefficient M1
By P1 and N1 breadth length ratio determine, M2 by P2 and N2 breadth length ratio determine, the like Mn by
The breadth length ratio of Pn and Nn determines.
Current comparator 304 is additionally operable to described n the first image current individual with corresponding described n respectively
Second image current compares, i.e. Ip1 Yu In1, Ip2 and In2 ... Ipn with Inn compares,
To n comparative result.
The input of bank of latches 305 is connected with n outfan of current comparator 304 respectively, is used for
N comparative result of latch-current comparator 304 output.
School adjusts the input of info encoder 306 to be connected with the outfan of bank of latches 305, for by institute
State n comparative result and carry out coding generation numeral school tune information, and be supplied to described control logical block 202.
The non-volatility memorizer that the embodiment of the present invention provides, at the circuit of traditional non-volatility memorizer
Middle addition testing circuit, after non-volatility memorizer powers on, testing circuit is started working, and detects in real time
The work state information of non-volatility memorizer, and generate corresponding school tune according to described work state information
Information, then adjusts information that non-volatility memorizer is carried out school tune further according to described school, due to test circuit
Need not connect external equipment input external command, school can be generated in real time and adjust information, it is achieved thereby that non-
The automatic school of volatile storage is adjusted, and greatly reduces the testing time, reduces testing cost.
The embodiment of the invention also discloses a kind of school adjust method, application above-described embodiment in non-volatile
Memorizer, the flow chart of the method as shown in Figure 4, comprises the following steps:
Step 401: the work state information of detection non-volatility memorizer, and believe according to described duty
Breath generates corresponding school and adjusts information.
After non-volatility memorizer powers on, testing circuit is started working, and constantly detects non-volatile holographic storage
The work state information of device, and generate corresponding school tune information according to work state information, wherein, described
Work state information is process corner during non-volatility memorizer work and state of temperature information.
Step 402: information and standard reference information are adjusted in relatively described school, when described school adjusts information to join with standard
When information of examining is inconsistent, described school tune information is stored in configuration information unit.
Wherein, standard reference information is corresponding to the initial state information of described non-volatility memorizer.Work as school
After the output of tune information extremely controls logical block, controlling logical block high-ranking officers can adjust information and standard reference information
Comparing, when school adjusts information and standard reference information inconsistent, high-ranking officers adjust information to be stored in configuration letter
Breath memory element.
Step 403: adjust information that described non-volatility memorizer is carried out school tune according to described school.
When school adjusts information and standard reference information inconsistent, controlling logical block can be in real time according to described
School adjusts information that described non-volatility memorizer is carried out school tune.After power-off, it is stored in configuration information storage single
School in unit adjusts information to disappear, and after again powering on, controls logical block or non-volatility memorizer institute
Processor in systems can read the school in configuration information memory element and adjust information, and according to described school
Tune information carries out school tune again.
Correcting and regulating method disclosed in the present embodiment, it is possible to the duty letter of detection non-volatility memorizer in real time
Breath, and generate corresponding school tune information according to described work state information, then adjust letter further according to described school
Breath carries out school tune to non-volatility memorizer, it is achieved that the automatic school of non-volatility memorizer is adjusted, and significantly saves
The about testing time, reduce testing cost.
The above is only the detailed description of the invention of the application, it is noted that general for the art
For logical technical staff, on the premise of without departing from the application principle, it is also possible to make some improvement and profit
Decorations, these improvements and modifications also should be regarded as the protection domain of the application.
Claims (8)
1. a non-volatility memorizer, it is characterised in that including: configuration information memory element, control
Logical block, test pattern control module and testing circuit, wherein:
Described testing circuit is connected with described control logical block, detects non-volatility memorizer in real time
Work state information, generate corresponding school according to described work state information and adjust information, and by described school
Tune information exports to controlling logical block；
Described control logical block, for described school tune information is compared with standard reference information, when
When described school adjusts information and standard reference information inconsistent, adjust information to non-volatile holographic storage according to described school
Device carries out school tune, and wherein, described standard reference information is the original state letter of described non-volatility memorizer
Breath；
Test pattern control module, is used for controlling described control logical block and described school tune information is stored in
Described configuration information memory element；
Wherein, described testing circuit includes: the first current source, the second current source, the first PMOS,
Info encoder is adjusted in first NMOS tube, voltage-current converter, current comparator, bank of latches and school,
Wherein:
The input of described first current source is connected with power supply, and the outfan of described first current source is with described
The source electrode of the first PMOS is connected, and the drain electrode of described first PMOS is connected with earth terminal, and described the
Grid and the drain electrode of one PMOS connect；
The input of described second current source is connected with power supply, and the outfan of described second current source is with described
The drain electrode of the first NMOS tube is connected, and the source electrode of described first NMOS tube is connected with earth terminal, and described the
The drain and gate of one NMOS tube connects；
The source electrode of described first PMOS is connected with the input of described voltage-current converter, and being used for will
The voltage of described first PMOS source electrode is converted to the first electric current；
The first input end of described current comparator is connected with the outfan of described voltage-current converter, institute
The grid of the second input and described first NMOS tube of stating current comparator is connected, and described current ratio is relatively
Device is used for described first current ratio mirror image obtains n the first image current, and by described first
The n that current ratio mirror image in NMOS tube obtains second image current, and by described n the first mirror
Image current compares with corresponding described n the second image current respectively, obtains n comparative result,
Wherein, n is the positive integer more than 2；
The input of described bank of latches is connected with n outfan of described current comparator, is used for latching
N comparative result of described current comparator output；
Described school adjusts the input of info encoder to be connected with the outfan of described bank of latches, and described school is adjusted
Info encoder generates numeral school tune information for described n comparative result carries out coding, and is supplied to
Described control logical block.
Non-volatility memorizer the most according to claim 1, it is characterised in that described duty
Information is process corner during non-volatility memorizer work and state of temperature information.
Non-volatility memorizer the most according to claim 1, it is characterised in that described control logic
Unit, is further used for, when described school adjusts information and standard reference information inconsistent, producing control signal,
Described control signal is used for activating described test pattern control module.
4. according to the non-volatility memorizer described in any one of claim 1-3, it is characterised in that described
School adjusts information to be electric current, voltage, capacitor's capacity or the metal-oxide-semiconductor in circuit whole to non-volatility memorizer
Quantity carries out the information of school tune.
Non-volatility memorizer the most according to claim 1, it is characterised in that described voltage-to-current
Transducer includes: the second NMOS tube and the second PMOS, wherein:
The input that grid is described voltage-current converter of described second NMOS tube, described second
The source ground of NMOS tube, described second NMOS tube drain electrode and the drain electrode phase of described second PMOS
Even, the drain electrode of described second PMOS connects with grid, and the grid of described second PMOS is described
The outfan of voltage-current converter.
Non-volatility memorizer the most according to claim 5, it is characterised in that described current ratio is relatively
Device includes: n PMOS and n NMOS tube, and n is the integer more than 2, wherein:
The source electrode of n PMOS is all connected with DC source, and the grid of n PMOS is connected conduct
The first input end of current comparator, the source electrode of n NMOS tube is all connected with earth terminal, n NMOS
Connected the second input as current comparator of the grid of pipe；
The drain electrode phase of the NMOS tube that the drain electrode of n PMOS is corresponding with n NMOS tube respectively
Continuous cropping is the outfan of described current comparator.
7. a correcting and regulating method, is applied to non-volatility memorizer, it is characterised in that the method includes:
Testing circuit is utilized to detect the work state information of described non-volatility memorizer, and according to described work
Make status information and generate corresponding school tune information；
Information and standard reference information are adjusted in relatively described school, when described school adjusts information with standard reference information not
Time consistent, described school tune information is stored in configuration information memory element；
Adjust information that described non-volatility memorizer is carried out school tune according to described school；
Wherein, described testing circuit include the first current source, the second current source, the first PMOS,
Info encoder is adjusted in one NMOS tube, voltage-current converter, current comparator, bank of latches and school；
The input of described first current source is connected with power supply, and the outfan of described first current source is with described
The source electrode of the first PMOS is connected, and the drain electrode of described first PMOS is connected with earth terminal, and described the
Grid and the drain electrode of one PMOS connect；
The input of described second current source is connected with power supply, and the outfan of described second current source is with described
The drain electrode of the first NMOS tube is connected, and the source electrode of described first NMOS tube is connected with earth terminal, and described the
The drain and gate of one NMOS tube connects；
The source electrode of described first PMOS is connected with the input of described voltage-current converter, and being used for will
The voltage of described first PMOS source electrode is converted to the first electric current；
The first input end of described current comparator is connected with the outfan of described voltage-current converter, institute
The grid of the second input and described first NMOS tube of stating current comparator is connected, and described current ratio is relatively
Device is used for described first current ratio mirror image obtains n the first image current, and by described first
The n that current ratio mirror image in NMOS tube obtains second image current, and by described n the first mirror
Image current compares with corresponding described n the second image current respectively, obtains n comparative result,
Wherein, n is the positive integer more than 2；
The input of described bank of latches is connected with n outfan of described current comparator, is used for latching
N comparative result of described current comparator output；
Described school adjusts the input of info encoder to be connected with the outfan of described bank of latches, and described school is adjusted
Info encoder generates numeral school tune information for described n comparative result carries out coding.
Correcting and regulating method the most according to claim 7, it is characterised in that also include:
Read the school in described configuration information memory element and adjust information, adjust information to non-volatile according to described school
Property memorizer carries out school tune.
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| CN105139891B (en) * | 2015-09-11 | 2023-04-18 | 四川易冲科技有限公司 | Method and device for calibrating analog integrated circuit |
| CN114758713B (en) * | 2022-06-14 | 2022-10-14 | 之江实验室 | Circuit and method for accelerating durability test of ferroelectric memory |
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| CN103339676A (en) * | 2011-01-31 | 2013-10-02 | 飞思卡尔半导体公司 | Integrated circuit device, voltage regulation circuitry and method for regulating a voltage supply signal |
| CN103348574A (en) * | 2010-12-03 | 2013-10-09 | 马维尔国际贸易有限公司 | Process and temperature insensitive inverter |
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|---|---|---|---|---|
| CN102203875A (en) * | 2008-09-30 | 2011-09-28 | Lsi公司 | Methods and apparatus for soft data generation for memory devices using reference cells |
| CN103348574A (en) * | 2010-12-03 | 2013-10-09 | 马维尔国际贸易有限公司 | Process and temperature insensitive inverter |
| CN103339676A (en) * | 2011-01-31 | 2013-10-02 | 飞思卡尔半导体公司 | Integrated circuit device, voltage regulation circuitry and method for regulating a voltage supply signal |
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