CN103593967A - DSP(Digital Signal Processor)-based automatic channel timing sequence voltage acquisition method - Google Patents
DSP(Digital Signal Processor)-based automatic channel timing sequence voltage acquisition method Download PDFInfo
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- CN103593967A CN103593967A CN201310591967.7A CN201310591967A CN103593967A CN 103593967 A CN103593967 A CN 103593967A CN 201310591967 A CN201310591967 A CN 201310591967A CN 103593967 A CN103593967 A CN 103593967A
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Abstract
The invention discloses a DSP (Digital Signal Processor) -based automatic channel timing sequence voltage acquisition method which is achieved through a voltage conditioning circuit (1), a voltage comparison circuit (2), a DSP chip (3), a communication circuit (4), a RAM (random-access memory) circuit (5) and a FLESH circuit (6). The DSP chip comprises an AD acquisition module (7), a level detection module (8), a data logging module (9) and a data transmission module (10). Through the method, multi-channel timing sequence voltage acquisition can be fulfilled, and detected N-channel timing sequences are conditioned through the voltage conditioning circuit (1), compared through the voltage comparison circuit (2) and acquired through the DSP chip (3). The method is simple in structure, easy to implement and can be widely used in circuits with higher requirements for real-time performance and integrality of acquisition results.
Description
Technical field
The present invention relates to sequence voltage automatic acquiring method when a kind of, particularly sequence voltage automatic acquiring method during a kind of passage based on DSP.
Background technology
In many commercial measurements such as automated detection system, computer data acquisition system and industrial control system, often need to be by in-site modeling signals collecting in microprocessor.In the process gathering, various undesired signals all can be along with measured signal enters in microprocessor, these signal superpositions can make the accuracy of measuring reduce in useful measured signal, in order on-the-spot electrical noise interference not to be incorporated into control system, often need on-the-spot AD collection result to carry out root mean square processing, with the impact of filtering interfering and noise.But collection result is carried out to root mean square, process and need to spend the regular hour, the real-time and the integrality that gather waveform are affected.
Summary of the invention
Sequence voltage automatic acquiring method when the object of the invention is to provide a kind of passage based on DSP, solves due to the problem of AD collection result being carried out to the time delay that root mean square processing produces.
During a kind of passage based on DSP, the concrete steps of sequence voltage automatic acquiring method are:
Sequence voltage automated collection systems when the first step is built
Time sequence voltage automated collection systems, comprising: voltage modulate circuit, voltage comparator circuit, dsp chip, communicating circuit, RAM circuit and FLASH circuit.Described dsp chip, comprising: AD acquisition module, level detection module, data recordin module and data transmission module.
The function of AD acquisition module is: complete the collection of AD result, and AD collection result is carried out to root mean square processing.
The function of level detection module is: the level value that reads voltage comparator circuit output.
The function of data recordin module is: during by N road, the equivalence value of sequence voltage AD collection result is stored in RAM circuit or FLASH circuit.
The function of data transmission module is: during by N road, the equivalence value of sequence voltage AD collection result is transferred to host computer.
The collection of sequence voltage when the method can complete multichannel, the sequence voltage when control circuit outside system produces tested N road, the N road sequential voltage output end of external control circuit is connected with the input end of N voltage modulate circuit respectively; The N of an external control circuit output terminal is connected with the input end of N voltage comparator circuit respectively; N voltage is nursed one's health from the output terminal of circuit and is connected with N AD collection terminal of dsp chip respectively; The output terminal of N voltage comparator circuit is connected with N GPIO end of dsp chip respectively, communicating circuit is connected with a SCI end of dsp chip, RAM circuit is connected with address, data and the control end of dsp chip, and FLASH circuit is connected with address, data and the control end of dsp chip.
Second step voltage modulate circuit is adjusted voltage range
During by tested N road, sequence voltage, after voltage modulate circuit, becomes the voltage of N road 0-3V, flows to N AD collection terminal of dsp chip.
The 3rd step voltage comparator circuit arranges level saltus step thresholding
During by tested N road, sequence voltage is input in voltage comparator circuit, the level saltus step thresholding of voltage comparator circuit is set, when when tested N road, sequence voltage is lower than saltus step thresholding, the level of voltage comparator circuit output terminal is low level, when when tested N road, sequence voltage is higher than saltus step thresholding, the level of voltage comparator circuit output terminal is high level.
The 4th step dsp chip initialization arranges
Acquisition mode and frequency acquisition that N AD collection terminal of dsp chip is set, AD acquisition mode is set to ordered mode, and frequency acquisition is 1Mbps, and the N of dsp chip GPIO end is set to input pattern.
The 5th step AD acquisition module carries out root mean square processing to collection result
N the AD collection terminal of AD acquisition module by dsp chip during to tested N road sequence voltage carry out AD collection, and the AD collection result in X millisecond is carried out to root mean square processing, result is set to the equivalence value of AD collection result in X millisecond.
The 6th step level detection module reads level value
Level detection module reads the level value of voltage comparator circuit output terminal by N on dsp chip GPIO end.
The 7th step data logging modle is stored in the equivalence value of AD collection result in RAM circuit or FLASH circuit
If there is 1 or several for high level in the level of N GPIO port, to take the 1st trip point that becomes high level from low level be starting point to data recordin module, the equivalence value of the AD collection result of sequence voltage while starting to record N road, and be recorded in time in RAM circuit, if the level of N GPIO port all becomes low level, and the duration is while meeting default time span, the equivalence value of the AD collection result of sequence voltage while stopping recording N road, and the equivalence value that is recorded in before all AD collection result in RAM circuit is stored in FLASH circuit.The automatic gatherer process of sequence voltage while completing N road.
The equivalence value of the 8th step data transport module sequence voltage AD collection result during by N road is transferred to host computer
Data transmission module responds the instruction of host computer by communicating circuit, during by N road, the equivalence value of sequence voltage AD collection result is uploaded to host computer.
While so far completing the passage based on DSP, sequence voltage gathers automatically.
This acquisition method increases a voltage comparator circuit by the input end at voltage modulate circuit, read the level value of N GPIO end input, when the level value saltus step on certain 1 Huo Ji road, road is high level, start to record the equivalence value of AD collection result, the level value of inputting when N GPIO end is all low level, and the duration, while reaching default time span, stops recording the equivalence value of AD collection result, completes gatherer process.The saltus step thresholding of voltage is set by voltage comparator circuit, can avoid interference the impact causing reading GPIO port level value, because IO changes response rapidly, by reading the level value of GPIO port, the Rule of judgment of sequence voltage when whether starting to record, can avoid, due to AD collection result is carried out to the time delay that root mean square processing produces, farthest keeping real-time and the integrality of waveform.The method is simple in structure, is easy to realize, and can be widely used in the circuit that the real-time of collection result and integrality are had relatively high expectations.
Accompanying drawing explanation
The block diagram of sequence voltage automated collection systems in sequence voltage automatic acquiring method time during a kind of passage based on DSP of Fig. 1.
1. voltage modulate circuit 2. voltage comparator circuit 3.DSP chip 4. communicating circuit 5.RAM circuit 6.FLASH circuit 7.AD acquisition module 8. level detection module 9. data recordin module 10. data transmission modules.
Embodiment
During a kind of passage based on DSP, the concrete steps of sequence voltage automatic acquiring method are:
Sequence voltage automated collection systems when the first step is built
Time sequence voltage automated collection systems, comprising: voltage modulate circuit 1, voltage comparator circuit 2, dsp chip 3, communicating circuit 4, RAM circuit 5 and FLASH circuit 6.Described dsp chip 3, comprising: AD acquisition module 7, level detection module 8, data recordin module 9 and data transmission module 10.
The function of AD acquisition module 7 is: complete the collection of AD result, and AD collection result is carried out to root mean square processing.
The function of level detection module 8 is: the level value that reads voltage comparator circuit 2 outputs.
The function of data recordin module 9 is: during by N road, the equivalence value of sequence voltage AD collection result is stored in RAM circuit 5 or FLASH circuit 6.
The function of data transmission module 10 is: during by N road, the equivalence value of sequence voltage AD collection result is transferred to host computer.
The collection of sequence voltage when the method can complete multichannel, the sequence voltage when control circuit outside system produces tested N road, the N road sequential voltage output end of external control circuit is connected with the input end of N voltage modulate circuit 1 respectively; The N of an external control circuit output terminal is connected with the input end of N voltage comparator circuit 2 respectively; N voltage is nursed one's health from the output terminal of circuit and is connected with N AD collection terminal of dsp chip 3 respectively; The output terminal of N voltage comparator circuit 2 is connected with N GPIO end of dsp chip 3 respectively, communicating circuit 4 is connected with a SCI end of dsp chip 3, RAM circuit 5 is connected with address, data and the control end of dsp chip 3, and FLASH circuit 6 is connected with address, data and the control end of dsp chip 3.
Second step voltage modulate circuit 1 is adjusted voltage range
During by tested N road, sequence voltage, after voltage modulate circuit 1, becomes the voltage of N road 0-3V, flows to N AD collection terminal of dsp chip 3.
The 3rd step voltage comparator circuit 2 arranges level saltus step thresholding
During by tested N road, sequence voltage is input in voltage comparator circuit 2, the level saltus step thresholding of voltage comparator circuit 2 is set, when when tested N road, sequence voltage is lower than saltus step thresholding, the level of voltage comparator circuit 2 output terminals is low level, when when tested N road, sequence voltage is higher than saltus step thresholding, the level of voltage comparator circuit 2 output terminals is high level.
The 4th step dsp chip 3 initialization settings
Acquisition mode and frequency acquisition that N AD collection terminal of dsp chip 3 is set, AD acquisition mode is set to ordered mode, and frequency acquisition is 1Mbps, and the N of dsp chip 3 GPIO end is set to input pattern.
7 pairs of collection result of the 5th step AD acquisition module are carried out root mean square processing
N the AD collection terminal of AD acquisition module 7 by dsp chip 3 during to tested N road sequence voltage carry out AD collection, and the AD collection result in X millisecond is carried out to root mean square processing, result is set to the equivalence value of AD collection result in X millisecond.
The 6th step level detection module 8 reads level value
Level detection module 8 holds by N GPIO on dsp chip 3 level value that reads voltage comparator circuit 2 output terminals.
The 7th step data logging modle 9 is stored in the equivalence value of AD collection result in RAM circuit 5 or FLASH circuit 6
If there is 1 or several for high level in the level of N GPIO port, to take the 1st trip point that becomes high level from low level be starting point to data recordin module 9, the equivalence value of the AD collection result of sequence voltage while starting to record N road, and be recorded in time in RAM circuit 5, if the level of N GPIO port all becomes low level, and the duration is while meeting default time span, the equivalence value of the AD collection result of sequence voltage while stopping recording N road, and the equivalence value that is recorded in before all AD collection result in RAM circuit 5 is stored in FLASH circuit 6.The automatic gatherer process of sequence voltage while completing N road.
The 8th step data transport module 10 is transferred to host computer by AD collection result
Data transmission module 10 is by the instruction of communicating circuit 4 response host computers, and during by N road, the AD collection result of sequence voltage is uploaded to host computer.
While so far completing the passage based on DSP, sequence voltage gathers automatically.
Claims (1)
1. the sequence voltage automatic acquiring method during passage based on DSP, is characterized in that the concrete steps of this method are:
Sequence voltage automated collection systems when the first step is built
Time sequence voltage automated collection systems, comprising: voltage modulate circuit (1), voltage comparator circuit (2), dsp chip (3), communicating circuit (4), RAM circuit (5) and FLASH circuit (6); Described dsp chip (3), comprising: AD acquisition module (7), level detection module (8), data recordin module (9) and data transmission module (10);
The function of AD acquisition module (7) is: complete the collection of AD result, and AD collection result is carried out to root mean square processing;
The function of level detection module (8) is: the level value that reads voltage comparator circuit (2) output;
The function of data recordin module (9) is: during by N road, the equivalence value of sequence voltage AD collection result is stored in RAM circuit (5) or FLASH circuit (6);
The function of data transmission module (10) is: during by N road, the equivalence value of sequence voltage AD collection result is transferred to host computer;
The collection of sequence voltage when the method can complete multichannel, the sequence voltage when control circuit outside system produces tested N road, the N road sequential voltage output end of external control circuit is connected with the input end of N voltage modulate circuit (1) respectively; The N of an external control circuit output terminal is connected with the input end of N voltage comparator circuit (2) respectively; N voltage is nursed one's health from the output terminal of circuit and is connected with N AD collection terminal of dsp chip (3) respectively; The output terminal of N voltage comparator circuit (2) is connected with N GPIO end of dsp chip (3) respectively, communicating circuit (4) is connected with a SCI end of dsp chip (3), RAM circuit (5) is connected with address, data and the control end of dsp chip (3), and FLASH circuit (6) is connected with address, data and the control end of dsp chip (3);
Second step voltage modulate circuit (1) is adjusted voltage range
During by tested N road, sequence voltage, after voltage modulate circuit (1), becomes the voltage of N road 0-3V, flows to N AD collection terminal of dsp chip (3);
The 3rd step voltage comparator circuit (2) arranges level saltus step thresholding
During by tested N road, sequence voltage is input in voltage comparator circuit (2), the level saltus step thresholding of voltage comparator circuit (2) is set, when when tested N road, sequence voltage is lower than saltus step thresholding, the level of voltage comparator circuit (2) output terminal is low level, when when tested N road, sequence voltage is higher than saltus step thresholding, the level of voltage comparator circuit (2) output terminal is high level;
The 4th step dsp chip (3) initialization setting
Acquisition mode and frequency acquisition that N AD collection terminal of dsp chip (3) is set, AD acquisition mode is set to ordered mode, and frequency acquisition is 1Mbps, and N GPIO end of dsp chip (3) is set to input pattern;
The 5th step AD acquisition module (7) carries out root mean square processing to collection result
N the AD collection terminal of AD acquisition module (7) by dsp chip (3) during to tested N road sequence voltage carry out AD collection, and the AD collection result in X millisecond is carried out to root mean square processing, result is set to the equivalence value of AD collection result in X millisecond;
The 6th step level detection module (8) reads level value
Level detection module (8) reads the level value of voltage comparator circuit (2) output terminal by upper N the GPIO end of dsp chip (3);
The 7th step data logging modle (9) is stored in the equivalence value of AD collection result in RAM circuit (5) or FLASH circuit (6)
If there is 1 or several for high level in the level of N GPIO port, to take the 1st trip point that becomes high level from low level be starting point to data recordin module (9), the equivalence value of the AD collection result of sequence voltage while starting to record N road, and be recorded in time in RAM circuit (5), if the level of N GPIO port all becomes low level, and the duration is while meeting default time span, the equivalence value of the AD collection result of sequence voltage while stopping recording N road, and the equivalence value that is recorded in all AD collection result in RAM circuit (5) is before stored in FLASH circuit (6), the automatic gatherer process of sequence voltage while completing N road,
The 8th step data transport module (10) is transferred to host computer by AD collection result
Data transmission module (10) is by the instruction of communicating circuit (4) response host computer, and during by N road, the AD collection result of sequence voltage is uploaded to host computer;
While so far completing the passage based on DSP, sequence voltage gathers automatically.
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Cited By (1)
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| CN106501581A (en) * | 2016-12-29 | 2017-03-15 | 洛阳宝盈智控科技有限公司 | Multigroup independent battery group voltage collection circuit |
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| JP2006017753A (en) * | 2004-06-30 | 2006-01-19 | Meidensha Corp | Device and method for detecting abnormal noise |
| CN101915868A (en) * | 2010-07-14 | 2010-12-15 | 中国科学院电工研究所 | Acquisition circuit for improving acquisition precision of voltage signal |
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