CN103579731B

CN103579731B - Lit-par-lit structure type balanced unbalanced transformer

Info

Publication number: CN103579731B
Application number: CN201210275819.XA
Authority: CN
Inventors: 远藤真
Original assignee: TDK Corp
Current assignee: TDK Corp
Priority date: 2012-08-03
Filing date: 2012-08-03
Publication date: 2018-04-03
Anticipated expiration: 2032-08-03
Also published as: CN103579731A

Abstract

The present invention provides a kind of lit-par-lit structure type balanced unbalanced transformer（1）, it is included：It is arranged on the uneven terminal of input and output unbalanced signal（2）The 1st balanced terminals with inputting and exporting balanced signal（3A）Between and include the 1st coil（4A）With the 1st capacitor（5A）Low pass filter（6）；And it is arranged on uneven terminal（2）The 2nd balanced terminals with inputting and exporting balanced signal（3B）Between and include the 2nd capacitor（5B）With the 2nd coil（4B）High-pass filter（7）.When in terms of the stacked direction from layered product, the 1st capacitor（5A）With the 2nd capacitor（5B）Configuration with the 1st coil（4A）With the 2nd coil（4B）In different regions.

Description

Laminated structure type balun transformer

Technical Field

The present invention relates to a laminated structure type balun which is an element for converting a balanced signal and an unbalanced signal to each other.

Background

A balun is an element that interconverts a balanced signal and an unbalanced signal. Some baluns use a High Pass Filter (HPF) and a Low Pass Filter (LPF) in combination (refer to, for example, japanese patent application laid-open No. 2000-236227 and japanese patent application laid-open No. H10-200360). The balun having such a configuration has a switching input and a switching output electrically connected. For this reason, for example, insertion loss is smaller as compared with an electromagnetic coupling type balun, and matching of input and output impedances can be performed while balanced and unbalanced signal conversion is performed. Further, japanese patent application laid-open No. 2000-236227 and japanese patent application laid-open No. H10-200360 describe a laminated structure balun (laminated structure type balun) in which a conductor pattern is formed between insulating layers.

However, the baluns described in japanese patent application laid-open No. 2000-236227 and japanese patent application laid-open No. H10-200360 have room for improvement in terms of improvement in electric properties.

Disclosure of Invention

According to an aspect of the present invention, there is provided a laminated configuration type balun transformer, including: a low pass filter provided between an unbalanced terminal to which the unbalanced signal is input and output and a 1 st balanced terminal to which the balanced signal is input and output, and including a 1 st coil and a 1 st capacitor; a high pass filter disposed between the unbalanced terminal and a 2 nd balanced terminal inputting and outputting a balanced signal, and including a 2 nd capacitor and a 2 nd coil; and a laminated body including a plurality of layers including a plurality of conductor layers having conductor patterns and a plurality of insulating layers laminated on a surface of the substrate, and including a low-pass filter and a high-pass filter, wherein the 1 st capacitor and the 2 nd capacitor are arranged in a region different from the 1 st coil and the 2 nd coil when viewed from a laminating direction of the laminated body.

The above and other objects, features, advantages and technical and industrial significance of this invention will be better understood by reading the following detailed description of preferred embodiments of the invention in conjunction with the accompanying drawings.

Drawings

Fig. 1 is a circuit diagram showing an equivalent circuit of a laminated structure type balun transformer in embodiment 1 of the present invention;

fig. 2 is a sectional view showing the configuration of the balun in embodiment 1;

fig. 3A is a plan view showing respective conductor layers of the balun in embodiment 1;

fig. 3B is a plan view showing the respective conductor layers of the balun in embodiment 1;

fig. 3C is a plan view showing the respective conductor layers of the balun in embodiment 1;

fig. 3D is a plan view showing the respective conductor layers of the balun in embodiment 1;

fig. 3E is a plan view showing the respective conductor layers of the balun in embodiment 1;

fig. 4A is a diagram showing an example of a method of manufacturing the balun transformer in embodiment 1;

fig. 4B is a diagram showing an example of a method of manufacturing the balun transformer in embodiment 1;

fig. 4C is a diagram showing an example of a method of manufacturing the balun transformer in embodiment 1;

fig. 4D is a diagram showing an example of a method of manufacturing the balun transformer in embodiment 1;

fig. 4E is a diagram showing an example of a method of manufacturing the balun transformer in embodiment 1;

fig. 4F is a diagram showing an example of a method of manufacturing the balun transformer in embodiment 1;

fig. 4G is a diagram showing an example of a method of manufacturing the balun transformer in embodiment 1;

fig. 4H is a diagram showing an example of a method of manufacturing the balun transformer in embodiment 1;

fig. 4I is a diagram showing an example of a method of manufacturing the balun transformer in embodiment 1;

fig. 4J is a diagram showing an example of a method of manufacturing the balun transformer in embodiment 1;

fig. 4K is a diagram showing an example of a method of manufacturing the balun transformer in embodiment 1;

fig. 4L is a diagram showing an example of a method of manufacturing the balun transformer in embodiment 1;

fig. 4M is a diagram showing an example of a method of manufacturing the balun transformer in embodiment 1;

fig. 5 is a sectional view showing a 1 st modification of the laminated structure of the balun transformer in embodiment 1;

fig. 6A is a diagram showing an example of a method of manufacturing a balun transformer in modification 1;

fig. 6B is a diagram showing an example of a method of manufacturing the balun transformer in modification 1;

fig. 6C is a diagram showing an example of a method of manufacturing the balun transformer in modification 1;

fig. 6D is a diagram showing an example of a method of manufacturing the balun transformer in modification 1;

fig. 6E is a diagram showing an example of a method of manufacturing the balun transformer in modification 1;

fig. 6F is a diagram showing an example of a method of manufacturing the balun transformer in modification 1;

fig. 6G is a diagram showing an example of a method of manufacturing the balun transformer in modification 1;

fig. 6H is a diagram showing an example of a method of manufacturing the balun in modification 1;

fig. 6I is a diagram showing an example of a method of manufacturing the balun transformer in modification 1;

fig. 6J is a diagram showing an example of a method of manufacturing the balun transformer in modification 1;

fig. 6K is a diagram showing an example of a method of manufacturing the balun transformer in modification 1;

fig. 6L is a diagram showing an example of a method of manufacturing the balun transformer in modification 1;

fig. 7 is a sectional view showing a 2 nd modification of the laminated structure of the balun transformer in embodiment 1;

fig. 8 is a sectional view showing a 3 rd modification of the laminated structure of the balun transformer in embodiment 1;

fig. 9 is a sectional view showing a 4 th modification of the laminated structure of the balun transformer in embodiment 1;

fig. 10 is a plan view showing a balun transformer in embodiment 2 of the present invention;

fig. 11 is a plan view showing a balun transformer in embodiment 3 of the present invention;

fig. 12 is a plan view showing a balun transformer in embodiment 4 of the present invention;

fig. 13 is a sectional view showing the configuration of the balun in comparative example 1;

fig. 14 is a plan view of the balun transformer in comparative example 1;

fig. 15 is a plan view of the balun transformer in comparative example 2;

fig. 16A is a graph showing the evaluation results of example 1, comparative example 1, and comparative example 2;

fig. 16B is a graph showing the evaluation results of example 1, comparative example 1, and comparative example 2;

fig. 16C is a graph showing the evaluation results of example 1, comparative example 1, and comparative example 2;

fig. 16D is a graph showing the evaluation results of example 1, comparative example 1, and comparative example 2;

fig. 17A is a graph showing the evaluation results of example 2 and comparative example 1;

fig. 17B is a graph showing the evaluation results of example 2 and comparative example 1;

fig. 17C is a graph showing the evaluation results of example 2 and comparative example 1;

fig. 17D is a graph showing the evaluation results of example 2 and comparative example 1;

fig. 18A is a graph showing the evaluation results of example 3 and comparative example 1;

fig. 18B is a graph showing the evaluation results of example 3 and comparative example 1;

fig. 18C is a graph showing the evaluation results of example 3 and comparative example 1;

fig. 18D is a graph showing the evaluation results of example 3 and comparative example 1;

fig. 19A is a graph showing the evaluation results of example 4 and comparative example 1;

fig. 19B is a graph showing the evaluation results of example 4 and comparative example 1;

fig. 19C is a graph showing the evaluation results of example 4 and comparative example 1;

fig. 19D is a graph showing the evaluation results of example 4 and comparative example 1;

fig. 20A is a graph showing the evaluation results of examples 1 to 4 and comparative example 1;

fig. 20B is a graph showing the evaluation results of examples 1 to 4 and comparative example 1;

fig. 20C is a graph showing the evaluation results of examples 1 to 4 and comparative example 1;

fig. 20D is a graph showing the evaluation results of examples 1 to 4 and comparative example 1.

Detailed Description

Embodiment mode 1

Fig. 1 is a circuit diagram showing an equivalent circuit of a laminated structure balun transformer in embodiment 1 of the present invention. The laminated-structure type balun (hereinafter, referred to as a balun if necessary) 1 is an LC type balun. The LC type balun is an element that converts a balanced signal and an unbalanced signal to each other by combining a Low Pass Filter (LPF) and a High Pass Filter (HPF) each composed of an L (coil) and a C (capacitor). The unbalanced signal is a signal having a ground potential as a reference potential. A balanced signal is a signal composed of two signals that are approximately 180 degrees (pi) out of phase with each other and approximately equal in amplitude.

In the present embodiment, the balun 1 includes an unbalanced terminal 2, a 1 st balanced terminal 3A, a 2 nd balanced terminal 3B, a low-pass filter 6 having a 1 st coil 4A and a 1 st capacitor 5A, and a high-pass filter 7 having a 2 nd coil 4B and a 2 nd capacitor 5B. The balun 1 further comprises a ground terminal 8. The ground terminal 8 is connected to the ground GND. The unbalanced terminal 2 inputs and outputs an unbalanced signal. The 1 st balanced terminal 3A and the 2 nd balanced terminal 3B each input and output a balanced signal. The low-pass filter 6 is provided between the unbalanced terminal 2 and the 1 st balanced terminal 3A. The high-pass filter 7 is provided between the unbalanced terminal 2 and the 2 nd balanced terminal 3B.

In the low-pass filter 6, the 1 st coil 4A is connected between the unbalanced terminal 2 and the 1 st balanced terminal 3A, and the 1 st capacitor 5A is connected between the 1 st balanced terminal 3A and the ground terminal 8. That is, the 1 st coil 4A is connected in series with respect to the 1 st signal flowing between the unbalanced terminal 2 and the 1 st balanced terminal 3A, and the 1 st capacitor 5A is connected in parallel with respect to the 1 st signal. In the high-pass filter 7, a 2 nd capacitor 5B is connected between the unbalanced terminal 2 and the 2 nd balanced terminal 3B, and a 2 nd coil 4B is connected between the 2 nd balanced terminal 3B and the ground terminal 8. That is, the 2 nd coil 4B is connected in parallel with respect to the 2 nd signal flowing between the unbalanced terminal 2 and the 2 nd balanced terminal 3B, and the 2 nd capacitor 5B is connected in series with respect to the 2 nd signal.

The low-pass filter 6 and the high-pass filter 7 each have a circuit configuration with a coil and a capacitor. Constants of the 1 st coil 4A and the 1 st capacitor 5A of the low-pass filter 6 and constants of the 2 nd coil 4B and the 2 nd capacitor 5B of the high-pass filter 7 vary depending on specifications of the balun 1, and are set to achieve impedance matching at a target frequency. The shape of the 1 st coil 4A and the 2 nd coil 4B is not limited to a specific form as long as the desired magnetic coupling in the balun 1 can be achieved, and may be any, for example, a spiral shape (coil shape), a meandering shape, a linear shape, or a curved shape.

Fig. 2 is a sectional view showing the configuration of the balun in embodiment 1. The balun 1 includes a laminated body 10. The laminated body 10 includes a plurality of layers including a plurality of conductor layers having conductor patterns and a plurality of insulating layers, and the low-pass filter 6 and the high-pass filter 7 described above, which are laminated on a substrate. In the present embodiment, the stacking direction of the stacked body 10 is a direction (direction indicated by arrow S in fig. 2) away from the surface 11S of the substrate 11 on which the conductor layer and the insulating layer are formed.

In the present specification, "viewed from the stacking direction" means a direction perpendicular to the stacking surface of the stacked body as indicated by an arrow S in fig. 2, or a case where the stacked body is viewed along the direction in which the layers are stacked, for example, a case of a plan view of the stacked body. The term "in the stacking direction" refers to a case where the layers are stacked as viewed in a cross section (a cross section as shown in fig. 2) obtained by cutting the stacked body perpendicular to the stacking surface, and the term "arranged in the same region of the stacked body in the stacking direction" refers to a region arranged at the same height (at the same horizontal position) in such a cross section.

The substrate 11 is an insulating substrate such as ferrite. The substrate 11 has a smoothing layer 12 on a surface 11S where a conductor layer and an insulating layer are formed, the smoothing layer burying irregularities to smooth the surface 11S. On the surface of the smoothing layer 12, a 1 st conductor layer 13, a dielectric layer 14, an intermediate conductor layer 15, a 1 st insulating layer 16, a 2 nd conductor layer 17, a 2 nd insulating layer 18, a 3 rd conductor layer 19, a 3 rd insulating layer (cover layer) 20, a 4 th conductor layer 21, and a terminal plating layer 22 are laminated in this order.

The 1 st conductor layer 13, the intermediate conductor layer 15, the 2 nd conductor layer 17, the 3 rd conductor layer 19, and the 4 th conductor layer 21 correspond to a plurality of conductor layers. These conductor layers are conductor layers of copper, silver, or the like, and patterns (conductor patterns) such as wiring patterns or terminal patterns are formed, for example. The 1 st conductor layer 13 includes a 1 st coil conductor 13LA to be the 1 st coil 4A, a 2 nd coil conductor 13LB to be the 2 nd coil 4B, a 1 st capacitor substrate-side electrode 13CA to be one electrode of the 1 st capacitor 5A, a 2 nd capacitor substrate-side electrode 13CB to be one electrode of the 2 nd capacitor 5B, and a terminal conductor 13T to be the unbalanced terminal 2, the ground terminal 8, and the like shown in fig. 1. The intermediate conductor layer 15 has a 1 st capacitor counter electrode 15CA which becomes the other electrode of the 1 st capacitor 5A, and a 2 nd capacitor counter electrode 15CB which becomes the other electrode of the 2 nd capacitor 5B.

The 2 nd conductor layer 17 includes a 1 st coil conductor 17LA to be the 1 st coil 4A, a 2 nd coil conductor 17LB to be the 2 nd coil 4B, a 1 st capacitor electrode 17CA connected to the 1 st capacitor counter electrode 15CA, a 2 nd capacitor electrode 17CB connected to the 2 nd capacitor counter electrode 15CB, and a terminal conductor 17T to be the unbalanced terminal 2 and the ground terminal 8 shown in fig. 1. The 3 rd conductor layer 19 includes a 1 st coil conductor 19LA to be the 1 st coil 4A, a 2 nd coil conductor 19LB to be the 2 nd coil 4B, a 1 st capacitor electrode 19CA connected to the 1 st capacitor electrode 17CA, a 2 nd capacitor electrode 19CB connected to the 2 nd capacitor electrode 17CB, and a terminal conductor 19T to be the unbalanced terminal 2 and the ground terminal 8 shown in fig. 1. The 4 th conductor layer 21 has a conductor 21T for a terminal for taking out the unbalanced terminal 2 or the ground terminal 8 shown in fig. 1 to the surface of the laminate 10. The surface of the terminal conductor 21T is covered with a terminal plating layer 22. The terminal conductor 21T protrudes from the surface of the laminate 10, and serves as the unbalanced terminal 2, the 1 st balanced terminal 3A, the 2 nd balanced terminal 3B, and the ground terminal 8.

The 1 st coil conductor 13LA of the 1 st conductor layer 13 and the 1 st coil conductor 17LA of the 2 nd conductor layer 17 are connected to each other via a through hole (via) 23A. Similarly, the 2 nd coil conductor 13LB of the 1 st conductor layer 13 and the 2 nd coil conductor 17LB of the 2 nd conductor layer 17 are connected to each other via the through hole 23B. In addition, the 1 st coil conductor 17LA of the 2 nd conductor layer 17 and the 1 st coil conductor 19LA of the 3 rd conductor layer 19 are connected to each other via the through hole 24A. Similarly, the 2 nd coil conductor 17LB of the 2 nd conductor layer 17 and the 2 nd coil conductor 19LB of the 3 rd conductor layer 19 are connected to each other via the through hole 24B. The 1 st capacitor electrode 17CA of the 2 nd conductor layer 17 and the 1 st capacitor electrode 19CA of the 3 rd conductor layer 19 are connected to each other via a through hole 25A, and the 2 nd capacitor electrode 17CB of the 2 nd conductor layer 17 and the 2 nd capacitor electrode 19CB of the 3 rd conductor layer 19 are connected to each other via a through hole 25B. The terminal conductors 17T, 19T, and 21T are connected to the 2 nd conductor layer 17, the 3 rd conductor layer 19, and the 4 th conductor layer 21, respectively.

The 1 st insulating layer 16, the dielectric layer 14, the 2 nd insulating layer 18, and the 3 rd insulating layer 20 correspond to insulating layers. The 1 st insulating layer 16, the 2 nd insulating layer 18, and the 3 rd insulating layer 20 are made of an insulating material. As the insulating material, for example, polyimide or epoxy resin is used. As a material of the dielectric layer 14, silicon nitride (SiN) or the like is used. A dielectric layer 14 is interposed between the 1 st conductor layer 13 and the intermediate conductor layer 15 to electrically isolate the two from each other. In addition, a dielectric layer 14 is interposed between the 1 st capacitor substrate-side electrode 13CA and the 1 st capacitor counter electrode 15CA, and between the 2 nd capacitor substrate-side electrode 13CB and the 2 nd capacitor counter electrode 15CB to constitute, together with these elements, the 1 st capacitor 5A and the 2 nd capacitor 5B. A 1 st insulating layer 16 is interposed between the dielectric layer 14 and the 2 nd conductor layer 17 to electrically isolate the two from each other. The 1 st insulating layer 16 has opening portions that electrically connect between the 1 st conductor layer 13 and the 2 nd conductor layer 17, and between the intermediate conductor layer 15 and the 2 nd conductor layer 17 via the through holes 23A and 23B. A 2 nd insulating layer 18 is interposed between the 2 nd conductor layer 17 and the 3 rd conductor layer 19 to electrically isolate the two from each other. The 2 nd insulating layer 18 has an opening portion for electrically connecting the 3 rd conductor layer 19 and the 2 nd conductor layer 17 via the through holes 24A, 25A, 24B, and 25B. The 3 rd insulating layer 20 covers the surface of the 3 rd conductor layer 19 to protect it from physical damage from outside the product. The laminated body 10 of the balun transformer 1 has the configuration described above. Next, the planar configuration of the respective conductor layers of the balun 1 will be described in detail.

Fig. 3A to 3E are plan views showing conductor layers of the balun in embodiment 1. As shown in fig. 3A, the 1 st conductor layer 13 includes a 1 st coil conductor 13LA, a 2 nd coil conductor 13LB, a 1 st capacitor substrate-side electrode 13CA, a 2 nd capacitor substrate-side electrode 13CB, and a terminal conductor 13T serving as the unbalanced terminal 2, the 1 st balanced terminal 3A, the 2 nd balanced terminal 3B, and the ground terminal 8. The 1 st coil conductor 13LA and the 1 st capacitor substrate-side electrode 13CA constitute a part of the low-pass filter 6, and the 2 nd coil conductor 13LB and the 2 nd capacitor substrate-side electrode 13CB constitute a part of the high-pass filter 7. For the 1 st coil conductor 13LA and the 2 nd coil conductor 13LB in the 1 st conductor layer 13, the width or the number of turns is not limited, and the two coil conductors 13LA and 13LB may be the same or different. In the 1 st conductor layer 13, the 1 st capacitor substrate-side electrode 13CA and the 2 nd capacitor substrate-side electrode 13CB are arranged in a region different from the 1 st coil conductor 13LA and the 2 nd coil conductor 13 LB.

The 1 st coil conductor 13LA on the low-pass filter 6 side is connected to the unbalanced terminal 2 and the through hole 23A. The 2 nd coil conductor 13LB on the high-pass filter 7 side is connected to the ground terminal 8 and the through hole 23B. The 1 st capacitor substrate-side electrode 13CA on the low-pass filter 6 side is connected to the ground terminal 8, and the 2 nd capacitor substrate-side electrode 13CB on the high-pass filter 7 side is connected to the unbalanced terminal 2. The unbalanced terminal 2, the 1 st balanced terminal 3A, the 2 nd balanced terminal 3B, and the ground terminal 8 are connected to the terminal conductors 13T, 17T, 19T, and 21T shown in fig. 3A to 3E, respectively, and they are arranged in the respective conductor layers in the same manner.

As shown in fig. 3B, the intermediate conductor layer 15 includes a 1 st capacitor counter electrode 15CA on the low-pass filter 6 side, a 2 nd capacitor counter electrode 15CB on the high-pass filter 7 side, and a terminal conductor 17T between the unbalanced terminal 2 and the ground terminal 8. As shown in fig. 3C, the 2 nd conductor layer 17 includes a 1 st coil conductor 17LA, a 2 nd coil conductor 17LB, a 1 st capacitor electrode 17CA, a 2 nd capacitor electrode 17CB, and a terminal conductor 17T. The 1 st coil conductor 17LA is connected to the 1 st coil conductor 13LA of the 1 st conductor layer 13 via the through hole 23A. The 2 nd coil conductor 17LB is connected to the 2 nd coil conductor 13LB of the 1 st conductor layer 13 via the through hole 23B. The 1 st coil conductor 17LA is connected to the through hole 24A, and the 2 nd coil conductor 17LB is connected to the through hole 24B. Also in the 2 nd conductor layer 17, as for the 1 st coil conductor 17LA and the 2 nd coil conductor 17LB, the width and the number of turns are not limited, and the two coil conductors 17LA and 17LB may be the same or different. In the 2 nd conductor layer 17, the 1 st capacitor electrode 17CA and the 2 nd capacitor electrode 17CB are arranged in a region different from the 1 st coil conductor 17LA and the 2 nd coil conductor 17 LB.

As shown in fig. 3D, the 3 rd conductor layer 19 includes a 1 st coil conductor 19LA, a 2 nd coil conductor 19LB, a 1 st capacitor electrode 19CA, a 2 nd capacitor electrode 19CB, and a terminal conductor 19T. The 1 st coil conductor 19LA is connected to the 1 st coil conductor 17LA of the 2 nd conductor layer 17 via the through hole 24A. The 2 nd coil conductor 19LB is connected to the 2 nd coil conductor 17LB of the 2 nd conductor layer 17 via the through hole 24B. The 1 st capacitor electrode 19CA is connected to the 1 st capacitor electrode 17CA of the 2 nd conductor layer 17 through a via 25A shown in fig. 2, and the 2 nd capacitor electrode 19CB is connected to the 2 nd capacitor electrode 17CB of the 2 nd conductor layer 17 through a via 25B shown in fig. 2.

The terminal conductor 19T serving as the 1 st balanced terminal 3A and the 1 st capacitor electrode 19CA on the low-pass filter 6 side are connected to each other via a wiring 19 PA. The 1 st coil conductor 19LA on the low-pass filter 6 side is connected to the wiring 19 PA. The terminal conductor 19T serving as the 2 nd balanced terminal 3B and the 2 nd capacitor electrode 19CB on the high-pass filter 7 side are connected to each other via a wiring 19 PB. The 2 nd coil conductor 19LB on the high-pass filter 7 side is connected to the wiring 19 PB. Also, in the 3 rd conductor layer 19, with respect to the 1 st coil conductor 19LA and the 2 nd coil conductor 19LB, the width and the number of turns are not limited, and the two coil conductors 19LA and 19LB may be the same or different. In the 3 rd conductor layer 19, the 1 st coil 4A of the low-pass filter 6 and the 2 nd coil 4B of the high-pass filter 7 are completed. Next, as shown in fig. 3E, in the 4 th conductor layer 21, the terminal conductor 21T serves as an external connection terminal, and the balun 1 constituting the equivalent circuit shown in fig. 1 is completed.

With such a configuration, in the balun 1, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged in a region different from the 1 st coil 4A and the 2 nd coil 4B when viewed from the lamination direction. Therefore, the influence of the 1 st capacitor 5A and the 2 nd capacitor 5B on the magnetic field generated by the 1 st coil 4A and the 2 nd coil 4B can be reduced. In the balun 1, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged in the same region as the 1 st coil 4A and the 2 nd coil 4B in the lamination direction. Therefore, thinning of the balun 1 (reduction in size in the stacking direction) can be achieved. As a result, the electrical characteristics of the balun 1 are improved. Next, an example of a method of manufacturing the balun transformer 1 is described.

Fig. 4A to 4M are diagrams illustrating an example of a method of manufacturing the balun in embodiment 1. First, as shown in fig. 4A, a substrate 11 is prepared. Next, as shown in fig. 4B, a smoothing layer 12 is formed on the surface of the substrate 11. Thereafter, as shown in fig. 4C, the 1 st conductor layer 13 is formed on the surface of the substrate 11, more specifically, on the surface of the smoothing layer 12. The 1 st conductor layer 13 may be formed of, for example, copper (Cu) plating. Next, as shown in fig. 4D, a dielectric layer 14 for determining the capacitance of the 1 st capacitor 5A and the 2 nd capacitor 5B is formed. The dielectric layer 14 is formed, for example, by depositing silicon nitride (SiN) by Chemical Vapor Deposition (CVD).

Next, as shown in fig. 4E, an intermediate conductor layer 15 is formed on the surface of the dielectric layer 14 at a position corresponding to the 1 st conductor layer 13 as a portion constituting the 1 st capacitor 5A and the 2 nd capacitor 5B. The intermediate conductor layer 15 may be formed of copper (Cu) plating, for example. In this way, the 1 st conductor layer 13, the dielectric layer 14, and the intermediate conductor layer 15 constitute the 1 st capacitor 5A and the 2 nd capacitor 5B. Next, as shown in fig. 4F, a 1 st insulating layer 16 is formed on the surface of the dielectric layer 14. The 1 st insulating layer 16 is formed, for example, in such a manner that polyimide is deposited on necessary sites on the surface of the dielectric layer 14 by photolithography.

Next, as shown in fig. 4G, in the through-hole (via) step, the dielectric layer 14 (SiN film) formed by the connection between the 1 st conductor layer 13 and the 2 nd conductor layer 17 is removed at the connection portion of the 1 st coil 4A and the 2 nd coil 4B and at the portions to be the unbalanced terminal 2, the 1 st balanced terminal 3A, the 2 nd balanced terminal 3B, and the ground terminal 8. Next, as shown in fig. 4H, a 2 nd conductor layer 17 is formed on the surface of the 1 st insulating layer 16. The 2 nd conductor layer 17 is formed of copper (Cu) plating, for example.

Next, as shown in fig. 4I, a 2 nd insulating layer 18 is formed on the surface of the 2 nd conductor layer 17. The 2 nd insulating layer 18 is formed, for example, in such a manner that polyimide is deposited on necessary sites on the surface of the 2 nd conductor layer 17 by photolithography. Next, as shown in fig. 4J, a 3 rd conductor layer 19 is formed on the surface of the 2 nd insulating layer 18. The 3 rd conductor layer 19 is formed of copper (Cu) plating, for example. Next, as shown in fig. 4K, a 3 rd insulating layer (cover layer) 20 is formed on the surface of the 3 rd conductor layer 19. The 3 rd insulating layer 20 is formed of, for example, polyimide. Next, as shown in fig. 4L, a 4 th conductor layer 21 to be the unbalanced terminal 2, the 1 st balanced terminal 3A, the 2 nd balanced terminal 3B, and the ground terminal 8 is formed. The 4 th conductor layer 21 is formed of copper (Cu) plating, for example. Finally, as shown in fig. 4M, the surface of the 4 th conductor layer 21 is covered with the terminal plating layer 22, thereby completing the balun 1. The terminal plating layer 22 may be formed by nickel (Ni) gold (Au) electroless plating. Note that the method of manufacturing the balun transformer 1 and the material of the balun transformer 1 are not limited to the above (and the following examples also apply).

Laminated structureModification 1 of

Fig. 5 is a sectional view of a 1 st modification of the laminated structure of the balun transformer in embodiment 1. The balun 1a shown in fig. 5 differs in that: there is no intermediate conductor layer 15 (see fig. 2) which the balun 1 of embodiment 1 has; the 1 st capacitor counter electrode 15CA and the 1 st capacitor electrode 17CA of the balun 1 are constituted by the 1 st capacitor common electrode 17A, and the 2 nd capacitor counter electrode 15CB and the 2 nd capacitor electrode 17CB of the balun 1 are constituted by the 2 nd capacitor common electrode 17B. In the balun 1, the 1 st capacitor counter electrode 15CA and the 2 nd capacitor counter electrode 15CB are formed, and then the 1 st capacitor electrode 17CA and the 2 nd capacitor electrode 17CB are formed on the respective surfaces. In the balun 1a, as described later, the 1 st capacitor common electrode 17A and the 2 nd capacitor common electrode 17B are formed in a single process. The 1 st capacitor common electrode 17A has the functions of the 1 st capacitor counter electrode 15CA and the 1 st capacitor electrode 17CA in the balun 1, and the 2 nd capacitor common electrode 17B has the functions of the 2 nd capacitor counter electrode 15CB and the 2 nd capacitor electrode 17CB in the balun 1.

The 1 st coil 4A on the low pass filter 6 side is constituted by the 1 st coil conductor 13LA, the 2 nd coil conductor 17LA, the 3 rd coil conductor 19LA, the through hole 23A, the through hole 24A, the 1 st insulating layer 16, the 2 nd insulating layer 18, and the 3 rd insulating layer 20 on the low pass filter 6 side. The 2 nd coil 4B on the high-pass filter 7 side is constituted by the 2 nd coil conductor 13LB, the 2 nd coil conductor 17LB, the 3 rd coil conductor 19LB, the through hole 23B, the through hole 24B, the 1 st insulating layer 16, the 2 nd insulating layer 18, and the 3 rd insulating layer 20 on the high-pass filter 7 side. The 1 st capacitor 5A on the low-pass filter 6 side has a 1 st capacitor substrate-side electrode 13CA, a dielectric layer 14, and a 1 st capacitor common electrode 17A. The 2 nd capacitor 5B on the high-pass filter 7 side has a 2 nd capacitor substrate-side electrode 13CB, a dielectric layer 14, and a 2 nd capacitor common electrode 17B. The terminal portion is constituted by the terminal conductors 13T, 17T, 19T, and 21T and the terminal plating layer 22. Next, an example of a method of manufacturing the balun 1a is described.

Fig. 6A to 6L are diagrams illustrating an example of a method of manufacturing the balun in modification 1. The steps up to the formation of the dielectric layer 14 shown in fig. 6D are the same as the method for manufacturing the balun in embodiment 1, and therefore, the description thereof is omitted. After the dielectric layer 14 is formed, as shown in fig. 6E, a 1 st insulating layer 16 is formed on the surface of the dielectric layer 14 except for the surface position corresponding to the 1 st conductor layer 13 as a portion constituting the 1 st and 2 nd capacitors 5A and 5B and the position corresponding to the 1 st conductor layer 13 as a portion constituting the unbalanced terminal 2, the 1 st and 2 nd balanced terminals 3A and 3B and the ground terminal 8. The 1 st insulating layer 16 is formed, for example, in such a manner that polyimide is deposited on necessary sites on the surface of the dielectric layer 14 by photolithography.

Next, as shown in fig. 6F, in the through-hole step, the dielectric layer 14 formed by the connection between the 1 st conductor layer 13 and the 2 nd conductor layer 17 is removed at the connection portion of the 1 st coil 4A and the 2 nd coil 4B and at the portions to be the unbalanced terminal 2, the 1 st balanced terminal 3A, the 2 nd balanced terminal 3B, and the ground terminal 8. Next, as shown in fig. 6G, a 2 nd conductor layer 17 is formed on the surface of the 1 st insulating layer 16 and on the surface of the 1 st conductor layer 13 opened to the dielectric layer 14. The 2 nd conductor layer 17 serves as the 1 st capacitor common electrode 17A and the 2 nd capacitor common electrode 17B shown in fig. 5. Subsequently, as shown in fig. 6H, a 2 nd insulating layer 18 is formed on the surface of the 2 nd conductor layer 17. Subsequently, the steps shown in fig. 6I to 6L are performed. These steps are the same as those in fig. 4J to 4M.

In the method of manufacturing the balun in modification 1, the 1 st capacitor common electrode 17A corresponding to the 1 st capacitor counter electrode 15CA and the 1 st capacitor electrode 17CA of the balun 1 in embodiment 1 is formed in a single step of forming the 2 nd conductor layer 17 shown in fig. 6G. The 2 nd capacitor common electrode 17B equivalent to the 2 nd capacitor counter electrode 15CB and the 2 nd capacitor electrode 17CB of the balun 1 is formed in the same manner. In this manner, the method of manufacturing the balun transformer in modification 1 does not require the step of forming the intermediate conductor layer 15 in the method of manufacturing the balun transformer in embodiment 1. Therefore, the process of manufacturing the balun transformer 1 can be reduced.

Modification 2 of the laminated structure

Fig. 7 is a cross-sectional view of a 2 nd modification of the laminated structure of the balun transformer in embodiment 1. In the balun 1B shown in fig. 7, the 1 st coil 4A on the low-pass filter 6 side, the 2 nd coil 4B on the high-pass filter 7 side, and the 1 st capacitor 5A on the low-pass filter 6 side and the 2 nd capacitor 5B on the high-pass filter 7 side are arranged in different regions when viewed from the lamination direction. In the balun 1B, the 1 st capacitor 5A on the low-pass filter 6 side and the 2 nd capacitor 5B on the high-pass filter 7 side are arranged in the same region in the stacking direction. Further, in the balun 1B, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged in a region between the 1 st coil 4A on the low-pass filter 6 side and the 2 nd coil 4B on the high-pass filter 7 side and different from the region where the coils 4A and 4B are formed, when viewed from the lamination direction.

The 1 st coil 4A on the low-pass filter 6 side is constituted by the 1 st coil conductor 13LA, the 2 nd coil conductor 17LA, the 3 rd coil conductor 19LA, the through hole 23A, and the through hole 24A on the low-pass filter 6 side, and the 1 st insulating layer 16A, the 2 nd insulating layer 18A, and the 3 rd insulating layer 20A on the low-pass filter 6 side. The 2 nd coil 4B on the high-pass filter 7 side is constituted by the 1 st coil conductor 13LB, the 2 nd coil conductor 17LB, the 3 rd coil conductor 19LB, the through hole 23B, and the through hole 24B on the high-pass filter 7 side, and the 1 st insulating layer 16B, the 2 nd insulating layer 18B, and the 3 rd insulating layer 20B on the high-pass filter 7 side. The 1 st capacitor 5A on the low-pass filter 6 side is constituted by the 1 st capacitor substrate-side electrode 13CA, the 1 st capacitor counter electrode 15CA, and the dielectric layer 14. The 2 nd capacitor 5B on the high-pass filter 7 side is constituted by the 2 nd capacitor substrate-side electrode 13CB, the 2 nd capacitor counter electrode 15CB, and the dielectric layer 14. The terminal portion is constituted by the terminal conductors 13TA, 17TA, 19TA, 13TC, 15TC, 13TB, 17TB, 19TB, and 21T and the terminal plating layer 22.

On the surface of the smoothing layer 12 for filling the irregularities to smooth the surface 11S of the substrate 11, the balun 1B is laminated in the order of the 1 st coil 4A on the low-pass filter 6 side, the 1 st capacitor 5A on the low-pass filter 6 side, the 2 nd capacitor 5B on the high-pass filter 7 side, and the 2 nd coil 4B on the high-pass filter 7 side thereafter. In this way, the laminated structure in modification 2 is formed.

In the balun 1B, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged in a region different from the 1 st coil 4A and the 2 nd coil 4B when viewed from the lamination direction. With such a configuration, the influence of the 1 st capacitor 5A and the 2 nd capacitor 5B on the magnetic field generated by the 1 st coil 4A and the 2 nd coil 4B can be reduced as compared with the related-art configuration in which the formation regions of the coil and the capacitor overlap when viewed from the lamination direction. Therefore, similarly to the balun 1 in embodiment 1, the electrical characteristics of the balun 1b can also be improved. In the balun 1B, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged in the same region in the lamination direction, and are arranged in a region between the 1 st coil 4A and the 2 nd coil 4B and different from the region where the coils 4A and 4B are formed.

Modification 3 of the laminated structure

Fig. 8 is a cross-sectional view of a 3 rd modification of the laminated structure of the balun transformer in embodiment 1. In the balun 1c, the 1 st capacitor substrate-side electrode 13CA of the 1 st capacitor 5A and the 2 nd capacitor substrate-side electrode 13CB of the 2 nd capacitor 5B are formed in a layer different from the 1 st coil conductor 13LA and the 2 nd coil conductor 13 LB. Therefore, in the balun 1c, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged in a region inside the 1 st coil 4A and the 2 nd coil 4B and different from a region where the coils 4A and 4B are formed. That is, in the balun 1c, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged between the 1 st coil 4A and the 2 nd coil 4B when viewed from the lamination direction. In addition, in the balun 1c, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged in the same region in the lamination direction. Further, in the balun 1c, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged in a region different from the 1 st coil 4A and the 2 nd coil 4B when viewed from the lamination direction. In the balun 1c, the 1 st coil 4A on the low-pass filter 6 side and the 2 nd coil 4B on the high-pass filter 7 side are arranged in the same region in the lamination direction.

The 1 st coil 4A on the low-pass filter 6 side is constituted by the 1 st coil conductor 13LA, the 2 nd coil conductor 17LA, the 3 rd coil conductor 19LA, the via 23A, and the via 24A on the low-pass filter 6 side, and the 1 st insulating layer 16 on the low-pass filter 6 side, the 2 nd insulating layer 18a on the dielectric layer side, the 2 nd insulating layer 18b between the capacitor and the coil, the 2 nd insulating layer 18c on the coil side, and the 3 rd insulating layer 20. The 2 nd coil 4B on the high-pass filter 7 side is constituted by the 2 nd coil conductor 13LB, the 2 nd coil conductor 17LB, the 3 rd coil conductor 19LB, the via hole 23B, and the via hole 24B on the high-pass filter 7 side, and the 1 st insulating layer 16 on the high-pass filter 7 side, the 2 nd insulating layer 18a on the dielectric layer side, the 2 nd insulating layer 18B between the capacitor and the coil, the 2 nd insulating layer 18c on the coil side, and the 3 rd insulating layer 20.

The 1 st capacitor 5A on the low-pass filter 6 side is constituted by the 1 st capacitor substrate-side electrode 13CA, the 1 st capacitor counter electrode 15CA, and the dielectric layer 14. The 2 nd capacitor 5B on the high-pass filter 7 side is constituted by the 2 nd capacitor substrate-side electrode 13CB, the 2 nd capacitor counter electrode 15CB, and the dielectric layer 14. The terminal portion is composed of the terminal conductors 13T, 13CT, 15T, 17TA, 19T, 21T and the terminal plating layer 22. A significant difference from the lamination method in embodiment 1 is that the lamination size of the through hole 23A and the through hole 23B is increased, so that the 1 st coil 4A on the low-pass filter 6 side and the 2 nd coil 4B on the high-pass filter 7 side are formed larger in the lamination direction. Such a configuration can be formed by ordinary photolithography and plating methods. In this way, the laminated structure of modification 3 is formed.

In the balun 1c, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged in a region different from the 1 st coil 4A and the 2 nd coil 4B when viewed from the lamination direction. With such a configuration, the influence of the 1 st capacitor 5A and the 2 nd capacitor 5B on the magnetic field generated by the 1 st coil 4A and the 2 nd coil 4B can be reduced as compared with the related-art configuration in which the formation regions of the coil and the capacitor overlap when viewed from the lamination direction. Therefore, similarly to the balun 1 of embodiment 1, the electrical characteristics of the balun 1c can also be improved. In the balun 1c, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged in the same region in the stacking direction, and are arranged in a region which is inside the 1 st coil 4A and the 2 nd coil 4B and which is different from the region where the coils 4A and 4B are formed, when viewed from the stacking direction.

Modification 4 of the laminated structure

Fig. 9 is a sectional view of a 4 th modification of the laminated structure of the balun transformer in embodiment 1. In the balun 1d, the 1 st capacitor 5A and the 2 nd capacitor 5B are formed in a region different from the 1 st coil 4A and the 2 nd coil 4B when viewed from the lamination direction. In the balun 1d, the 1 st coil 4A on the low-pass filter 6 side, the 1 st capacitor 5A on the low-pass filter 6 side, and the 2 nd capacitor 5B on the high-pass filter 7 side are arranged in the same region in the laminating direction. Only the 2 nd coil 4B on the high-pass filter 7 side is arranged in a region different from the 1 st coil 4A, the 1 st capacitor 5A, and the 2 nd capacitor 5B in the lamination direction. In this way, in the balun 1d, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged between the 1 st coil 4A and the 2 nd coil 4B when viewed from the lamination direction.

In the balun 1d, the 1 st coil 4A on the low-pass filter 6 side is constituted by the 1 st coil conductor 13LA, the 2 nd coil conductor 17LA, the 3 rd coil conductor 19LA, the via 23A, and the via 24A on the low-pass filter 6 side, and the 1 st insulating layer 16, the 2 nd insulating layer 18A, and the 3 rd insulating layer 20A on the low-pass filter 6 side. The 2 nd coil 4B on the high-pass filter 7 side is constituted by the 2 nd coil conductor 13LB, the 2 nd coil conductor 17LB, the 3 rd coil conductor 19LB, the through hole 23B, the through hole 24B on the high-pass filter 7 side, and the 1 st insulating layer 16B, the 2 nd insulating layer 18B, and the 3 rd insulating layer 20B on the high-pass filter 7 side. The 1 st capacitor 5A on the low-pass filter 6 side is constituted by the 1 st capacitor substrate-side electrode 13CA, the 1 st capacitor counter electrode 15CA, the 1 st capacitor electrode 17CA, and the dielectric layer 14. The 2 nd capacitor 5B on the high-pass filter 7 side is constituted by the 2 nd capacitor substrate-side electrode 13CB, the 2 nd capacitor counter electrode 15CB, the 2 nd capacitor electrode 17CB, and the dielectric layer 14. The terminal portion is constituted by the terminal conductors 13TA, 15TA, 17TA, 19TA, 13TB, 17TB, 19TB, and 21T, and the terminal plating layer 22. In this way, the laminated structure of the 4 th modification is formed.

In the balun 1d, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged in a region different from the 1 st coil 4A and the 2 nd coil 4B when viewed from the lamination direction. With such a configuration, the influence of the 1 st capacitor 5A and the 2 nd capacitor 5B on the magnetic field generated by the 1 st coil 4A and the 2 nd coil 4B can be reduced as compared with the related-art configuration in which the formation regions of the coil and the capacitor overlap when viewed from the lamination direction. Therefore, similarly to the balun 1 of embodiment 1, the electrical characteristics of the balun 1d can also be improved. In the balun 1d, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged in the same region as the region where the 1 st coil 4A is formed and in a region different from the region where the 2 nd coil 4B is formed in the stacking direction.

Embodiment mode 2

Fig. 10 is a plan view of a balun transformer in embodiment 2 of the present invention. In the balun 1A of embodiment 2, in a plan view, that is, when viewed from the stacking direction, the 1 st coil 4A, the 2 nd coil 4B, the 1 st capacitor 5A, and the 2 nd capacitor 5B are arranged differently from the baluns 1, 1A, and the like in embodiment 1 and its modified example. It is intended that fig. 10 shows the positional relationship of the 1 st coil 4A, the 2 nd coil 4B, the 1 st capacitor 5A, and the 2 nd capacitor 5B on the plane with each other. Accordingly, the details of the laminated structure shown in fig. 3A to 3E are omitted and simplified.

In the balun 1A, the 1 st capacitor 5A on the low-pass filter 6 side is arranged between the 1 st coil 4A on the low-pass filter 6 side and the 2 nd coil 4B on the high-pass filter 7 side, and the 2 nd capacitor 5B on the high-pass filter 7 side is arranged between the unbalanced terminal 2 and the ground terminal 8.

Embodiment 3

Fig. 11 is a plan view of a balun transformer in embodiment 3 of the present invention. The omission of the laminated structure is the same as in embodiment 2. In the balun 1B, the 2 nd capacitor 5B on the high-pass filter 7 side is arranged between the 2 nd coil 4B on the high-pass filter 7 side and the 1 st coil 4A on the low-pass filter 6 side, and the 1 st capacitor 5A on the low-pass filter 6 side is arranged between the unbalanced terminal 2 and the ground terminal 8.

Embodiment 4

Fig. 12 is a plan view of a balun transformer in embodiment 4 of the present invention. The omission of the laminated structure is the same as in embodiments 2 and 3. In the balun 1C, the 2 nd capacitor 5B on the high-pass filter 7 side and the 1 st capacitor 5A on the low-pass filter 6 side are arranged between the 2 nd coil 4B on the high-pass filter 7 side and the 1 st coil 4A on the low-pass filter 6 side.

Evaluation of

The influence of the positional relationship between the capacitor 5A on the low-pass filter 6 side and the capacitor 5B on the high-pass filter 7 side with respect to the 1 st coil 4A on the low-pass filter 6 side and the 2 nd coil 4B on the high-pass filter 7 side on the electrical characteristics was evaluated. The evaluation targets are baluns 1, 1A, 1B, and 1C in embodiments 1 to 4 described above, and comparative example 1 and comparative example 2 described later, respectively. The balun according to embodiment 1 corresponds to example 1, the balun according to embodiment 2 corresponds to example 2, the balun according to embodiment 3 corresponds to example 3, and the balun according to embodiment 4 corresponds to example 4.

For evaluation, computer simulations were used. A 2.5-dimensional simulator SONNET is used as simulation software. For example 1 to example 4 and comparative example 1 and comparative example 2 described later, the positional relationship of the 1 st capacitor 5A on the low-pass filter 6 side and the 2 nd capacitor 5B on the high-pass filter 7 side with respect to the 1 st coil 4A on the low-pass filter 6 side and the 2 nd coil 4B on the high-pass filter 7 side was changed in each example, and comparison of the electrical characteristics was performed. For this reason, in examples 1 to 4, comparative example 1, and comparative example 2, the coil and the terminal of each conductor layer were set exactly the same in position, arrangement, and shape.

As 4 characteristics for evaluating the necessary electrical characteristics of the balun, i.e., an insertion loss characteristic, a phase difference characteristic, an amplitude difference characteristic, and a reflection loss characteristic, were considered for evaluation. The target frequency band is 240MHz to 2500MHz used in a wireless Local Area Network (LAN), bluetooth, and the like. The insertion loss characteristic represents the transmission efficiency, and thus the characteristic is better as the loss value is closer to 0 dB. The phase difference characteristic is ideal when the phase difference of the 2 balanced signals is 180deg., and thus the characteristic is better as the phase difference is closer to 180 deg.. The amplitude difference characteristic is ideal when the amplitudes of the 2 balanced signals are completely the same, and thus the characteristic is better as the amplitude difference is closer to 0 dB. The reflection loss characteristic represents reflection efficiency, and thus the characteristic is better when the dB value is larger. In particular, insertion loss is considered to be the most important electrical characteristic, since it contributes to power saving, which is required for mobile electronic devices.

Comparative example 1

Fig. 13 is a sectional view showing the configuration of the balun in comparative example 1. In the balun 101, the 1 st capacitor 105A on the low-pass filter 106 side and the 2 nd capacitor 105B on the high-pass filter 107 side are configured to overlap a region where the 1 st coil 104A on the low-pass filter 106 side and the coil 104B on the high-pass filter 107 side are arranged, more specifically, a region within the coil opening, when viewed from the lamination direction. This results from a construction similar to the prior art (quasi-conditional).

In the balun 101, the 1 st coil 104A and the 1 st capacitor 105A constitute a low-pass filter 106, and the 2 nd coil 104B and the 2 nd capacitor 105B constitute a high-pass filter 107. The method for manufacturing the balun 101 is the same as the manufacturing method in embodiment 1 except that the 1 st capacitor 105A and the 2 nd capacitor 105B are formed in a region different from the region where the 1 st coil 104A and the 2 nd coil 104B are formed in the lamination direction. The 1 st capacitor 105A and the 2 nd capacitor 105B are constituted by a conductor layer B1, a conductor layer B2, and an I1 layer of a SiN film interposed between the B1 layer and the B2 layer. The 1 st coil 104A and the 2 nd coil 104B are constituted by a conductor layer M1, a conductor layer M2, a conductor layer M3, insulating layers I2 and I3 interposed between these layers, and an insulating layer I4 which protects the conductor layer M3 from physical damage from outside the product.

Fig. 14 is a plan view of the balun transformer in comparative example 1. The balun 101 has terminals of an unbalanced terminal 102, a 1 st balanced terminal 103A, a 2 nd balanced terminal 103B, and a ground terminal 108, a low-pass filter 106 having a 1 st coil 104A and a 1 st capacitor 105A, and a high-pass filter 107 having a 2 nd coil 104B and a 2 nd capacitor 105B. Note that, in fig. 14, it is intended to show the positional relationship of the 1 st coil 104A, the 2 nd coil 104B, the 1 st capacitor 105A, and the 2 nd capacitor 105B with respect to each other on the plane. Accordingly, the details of the laminated structure as shown in fig. 3A to 3E described above are omitted and simplified. The capacitance values of the 1 st capacitor 105A and the 2 nd capacitor 105B are set to be the same as those of embodiments 1 to 4. Further, it is necessary to set the thickness of the insulating layer I2 for isolating the conductor layer B2 from the conductor layer M1 to be the same as the planar direction distance between the 1 st coil 4A and the 1 st capacitor 5A and the planar direction distance between the 2 nd coil and the 2 nd capacitor in embodiments 1 to 4 for comparison, and therefore, the thickness of the insulating layer I2 is set to be the same as the planar direction distance between the 1 st coil 4A and the 1 st capacitor 5A in the lamination direction.

Comparative example 2

Fig. 15 is a plan view of the balun in comparative example 2. The balun 101a has terminals of an unbalanced terminal 102, a 1 st balanced terminal 103A, a 2 nd balanced terminal 103B, and a ground terminal 108, a low-pass filter 106 having a 1 st coil 104A and a 1 st capacitor 105Aa, and a high-pass filter 107 having a 2 nd coil 104B and a 2 nd capacitor 105 Ba. In fig. 15, similarly to fig. 14, the positional relationship of the 1 st coil 104A, the 2 nd coil 104B, the 1 st capacitor 105Aa, and the 2 nd capacitor 105Ba on the plane with each other is intended to be shown. Accordingly, the details of the laminated structure as shown in fig. 3A to 3E described above are omitted and simplified.

For the cross-sectional configuration of the balun 101a, only the sizes of the 1 st capacitor 105A and the 2 nd capacitor 105B in comparative example 1 are increased. That is, only the areas of B1 and B2 of the balun 101 in the planar direction in fig. 13 were changed, and the other configurations were the same as in comparative example 1. In the balun 101a, unlike in comparative example 1, the capacitors of the 1 st capacitor 105Aa and the 2 nd capacitor 105Ba are not housed in the openings of the 1 st coil 104A and the 2 nd coil 104B, respectively. However, the capacitance values of the 1 st capacitor 105Aa and the 2 nd capacitor 105Ba are set to be the same as those of embodiments 1 to 4 and comparative example 1. In addition, similarly to comparative example 1, the thickness of the insulating layer I2 for separating the conductor layer B2 from the conductor layer M1 was set to be the same as the planar direction distance between the 1 st coil 4A and the 1 st capacitor 5A in the lamination direction.

Evaluation of example 1

Fig. 16A to 16D are graphs showing evaluation results of example 1, comparative example 1, and comparative example 2. In fig. 16A to 16D, the solid line indicates the electrical characteristics of example 1, the dotted line indicates the electrical characteristics of comparative example 1, and the dashed line indicates the electrical characteristics of comparative example 2. With respect to fig. 16A to 16D, although the phase difference characteristics are not significantly different with respect to all of the insertion loss characteristics, the amplitude difference characteristics, and the reflection loss characteristics, example 1 is better than comparative examples 1 and 2. In addition, all the electrical characteristics of comparative example 2 are inferior to those of comparative example 1. The reason is considered to be that the sizes of the 1 st capacitor 105Aa and the 2 nd capacitor 105Ba in comparative example 2 are larger than the sizes of the 1 st capacitor 105A and the 2 nd capacitor 105B in comparative example 1. That is, the results show that in the LC laminated structure type balun having the structures of comparative examples 1 and 2, the size of the capacitor has an influence on the electrical characteristics.

The evaluation results of examples 2 to 4 and comparative example 1 are shown below. The electrical characteristics of comparative example 1 were somewhat better than those of comparative example 2. In comparative example 1, the electrode areas of the 1 st capacitor 105A on the low-pass filter 106 side and the 2 nd capacitor 105B on the high-pass filter 107 side are set to be the same as the electrode areas of the 1 st capacitor 5A on the low-pass filter 6 side and the 2 nd capacitor 5B on the high-pass filter 7 side in examples 2 to 4. Therefore, the comparison between comparative example 1 and examples 2 to 4 is of greater significance.

Evaluation of example 2

Fig. 17A to 17D are graphs showing the evaluation results of example 2 and comparative example 1. In fig. 17A to 17D, the solid line indicates the electrical characteristics of example 2, and the dotted line indicates the electrical characteristics of comparative example 1. As for fig. 17A to 17D, although example 2 is slightly inferior to comparative example 1 in phase difference, since example 2 improves insertion loss, which is considered to be the most important electrical characteristic, the overall electrical characteristic is better.

Evaluation of example 3

Fig. 18A to 18D are graphs showing the evaluation results of example 3 and comparative example 1. In fig. 18A to 18D, the solid line indicates the electrical characteristics of example 3, and the dotted line indicates the electrical characteristics of comparative example 1. As for fig. 18A to 18D, all the electrical characteristics of example 3 are superior to those of comparative example 1.Evaluation of example 4

Fig. 19A to 19D are graphs showing the evaluation results of example 4 and comparative example 1. In fig. 19A to 19D, the solid line indicates the electrical characteristics of example 4, and the dotted line indicates the electrical characteristics of comparative example 1. With respect to fig. 19A to 19D, all the electrical characteristics of example 4 are superior to those of comparative example 1.

Comparison between examples 1 to 4

Fig. 20A to 20D are graphs showing evaluation results of examples 1 to 4 and comparative example 1. In fig. 20A to 20D, the respective electrical characteristics of example 1 are shown by solid lines, example 2 is shown by dashed lines, example 3 is shown by dotted lines, example 4 is shown by chain lines, and comparative example 1 is shown by thick lines. The results show that example 3 has the best electrical properties.

The above results show that the configuration in which the 1 st capacitor 5A and the 2 nd capacitor 5B are formed in the region different from the region in which the 1 st coil 4A and the 2 nd coil 4B are formed when viewed from the lamination direction in examples 1 to 4 produces a greater effect of improving the electrical characteristics, as compared with the configuration in which the 1 st capacitor 105A and the 2 nd capacitor 105B are formed in the region in which the 1 st coil 104A and the 2 nd coil 104B are formed in comparative examples 1 and 2. In addition, in embodiments 1 to 4, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged in the same region as the 1 st coil 4A and the 2 nd coil 4B in the lamination direction. Therefore, in embodiments 1 to 4, thinning (reduction in size in the stacking direction) can be achieved as compared with comparative example 1 and comparative example 2 in which the 1 st capacitor 105A and the 2 nd capacitor 105B are stacked on the 1 st coil 104A and the 2 nd coil 104B.

In comparative examples 1 and 2, the 1 st capacitor 105A and the 2 nd capacitor 105B are configured to overlap with a region where the 1 st coil 104A and the 2 nd coil 104B are arranged when viewed from the lamination direction. Therefore, it is assumed that the influence of the magnetic field generated by all the conductors above, below, to the left, and to the right of the 1 st coil 104A and the 2 nd coil 104B is considerable. This phenomenon is confirmed by the fact that the electrical characteristics are further deteriorated in comparative example 2 in which the electrode sizes of the 1 st capacitor 105A and the 2 nd capacitor 105B are larger.

In embodiments 1 to 4, the 1 st capacitor 5A and the 2 nd capacitor 5B are formed in a different region from the 1 st coil 4A and the 2 nd coil 4B, and in the laminated body, the 1 st capacitor 5A and the 2 nd capacitor 5B are arranged in the same region as the 1 st coil 4A and the 2 nd coil 4B in the laminating direction. Therefore, in embodiments 1 to 4, it is assumed that the arrangement of the 1 st capacitor 5A and the 2 nd capacitor 5B significantly affects only the magnetic field generated by the conductors adjacent to the 1 st coil 4A and the 2 nd coil 4B, and therefore, the effect of improving the electrical characteristics is exhibited. However, the advantageous effects produced in embodiments 1 to 4 are not limited thereto.

The present invention is not limited to the above-described embodiments, modifications thereof, and examples, and various modifications may be made without changing the scope of the present invention. For example, the arrangement of the unbalanced terminal, the 1 st balanced terminal, the 2 nd balanced terminal, and the ground terminal is not limited to the above-described positions. The multilayer wiring configuration constituting the balun transformer may have less than the number of layers described above. The 1 st coil 4A and the 2 nd coil 4B may also be formed separately in different conductor layers, or may be formed only partially in the same conductor layer. The electrode of at least one of the 1 st capacitor 5A and the 2 nd capacitor 5B may be provided in the same conductor layer as the 1 st coil 4A or the 2 nd coil 4B, or the electrodes of the 1 st capacitor 5A and the 2 nd capacitor 5B may be provided in a different conductor layer from the conductor layer forming the 1 st coil 4A and the 2 nd coil 4B. The conductor layer on which the electrodes of the 1 st capacitor 5A and the 2 nd capacitor 5B are formed is not limited to the 1 st conductor layer and the intermediate conductor layer, and may be constituted by the 1 st conductor layer and the 2 nd conductor layer which are the same as the conductors of the 1 st coil 4A and the 2 nd coil 4B, or the 2 nd conductor layer and the 3 rd conductor layer. Obviously, the configuration may have the conductor layers in the reverse order on the insulating substrate. Various coil configurations and shapes may be employed without departing from the scope of the present invention. For example, the coil shape of the 1 st coil 4A and the 2 nd coil 4B or either one of them may be a circle, an ellipse, a polygon such as a hexagon, a shape in which only corners are rounded, a serpentine shape, or a spiral shape.

Claims

1. A laminated, build-up model balun, comprising:

a low pass filter provided between an unbalanced terminal to which the unbalanced signal is input and output and a 1 st balanced terminal to which the balanced signal is input and output, and including a 1 st coil and a 1 st capacitor;

a high pass filter disposed between the unbalanced terminal and a 2 nd balanced terminal inputting and outputting a balanced signal, and including a 2 nd capacitor and a 2 nd coil; and

a laminated body including a plurality of layers including a plurality of conductor layers having conductor patterns and a plurality of insulating layers laminated on a surface of a substrate, and the laminated body including the low-pass filter and the high-pass filter,

wherein,

the laminate comprises:

1 st conductor layer;

a dielectric layer covering the upper surface and the side surface of the 1 st conductor layer;

a 1 st insulating layer formed on a surface of the dielectric layer; and

a 2 nd conductor layer formed on the surface of the 1 st insulating layer,

the 1 st capacitor and the 2 nd capacitor each include:

a capacitor substrate-side electrode formed on the 1 st conductor layer and having an upper surface and a side surface covered with the dielectric layer;

a capacitor electrode formed on the 2 nd conductor layer so as to oppose the capacitor substrate-side electrode; and

a capacitor counter electrode connected to the capacitor electrode and penetrating the 1 st insulating layer to reach the dielectric layer,

the dielectric layer is interposed between and electrically insulates the capacitor substrate-side electrode and the capacitor counter electrode,

the 1 st capacitor and the 2 nd capacitor are arranged in a region different from the 1 st coil and the 2 nd coil when viewed from a lamination direction of the laminate,

electrodes constituting all of the 1 st capacitor and the 2 nd capacitor are disposed in a layer different from at least one of a forming layer of the 1 st coil and a forming layer of the 2 nd coil in a laminated cross section of the laminate,

the 1 st coil is disposed between the 1 st balanced terminal and the unbalanced terminal when viewed from the lamination direction,

the 2 nd coil is arranged between the 2 nd balanced terminal and a ground terminal when viewed from the lamination direction,

the 1 st and 2 nd capacitors are arranged between a region where the 1 st balanced terminal, the 1 st coil, and the unbalanced terminal are formed and a region where the 2 nd balanced terminal, the 2 nd coil, and the ground terminal are formed, when viewed from the stacking direction.

2. The stacked configuration balun according to claim 1,

the 1 st capacitor and the 2 nd capacitor are arranged between the 1 st coil and the 2 nd coil when viewed from the stacking direction.

3. The stacked configuration balun according to claim 1,

at least one of the 1 st capacitor and the 2 nd capacitor is disposed between the 1 st coil and the 2 nd coil when viewed from the stacking direction.

4. The stacked configuration type balun transformer according to claim 1 or 3,

at least one of the 1 st capacitor and the 2 nd capacitor is disposed between the unbalanced terminal and a ground terminal connected to ground when viewed from the stacking direction.

5. The stacked configuration balun according to claim 1,

the 1 st coil includes a 1 st coil conductor of the 1 st conductor layer, a 1 st coil conductor of the 2 nd conductor layer, and a via hole penetrating the 1 st insulating layer and the dielectric layer to connect the 1 st coil conductor of the 1 st conductor layer and the 1 st coil conductor of the 2 nd conductor layer.

6. The stacked configuration balun according to claim 5,

the 2 nd coil includes a 2 nd coil conductor of the 1 st conductor layer, a 2 nd coil conductor of the 2 nd conductor layer, and a via hole penetrating the 1 st insulating layer and the dielectric layer to connect the 2 nd coil conductor of the 1 st conductor layer and the 2 nd coil conductor of the 2 nd conductor layer.

7. The stacked configuration balun according to claim 1,

at least one of the 1 st coil and the 2 nd coil includes a 1 st annular pattern formed to be connected to the 1 st conductor layer, a 2 nd annular pattern formed to the 2 nd conductor layer, and a via hole penetrating the 1 st insulating layer and the dielectric layer to connect the 1 st annular pattern and the 2 nd annular pattern.

8. The stacked configuration balun according to claim 1,

the dielectric layer is thinner than the 1 st insulating layer.