CN103579373B - A kind of Trench-structure charge compensation Schottky semiconductor device and its manufacture method - Google Patents
A kind of Trench-structure charge compensation Schottky semiconductor device and its manufacture method Download PDFInfo
- Publication number
- CN103579373B CN103579373B CN201210269963.2A CN201210269963A CN103579373B CN 103579373 B CN103579373 B CN 103579373B CN 201210269963 A CN201210269963 A CN 201210269963A CN 103579373 B CN103579373 B CN 103579373B
- Authority
- CN
- China
- Prior art keywords
- semiconductor material
- conducting
- groove
- layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 119
- 238000000034 method Methods 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 71
- 239000002184 metal Substances 0.000 claims description 32
- 230000004888 barrier function Effects 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 239000012774 insulation material Substances 0.000 claims description 7
- 230000007797 corrosion Effects 0.000 claims description 5
- 238000005260 corrosion Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 4
- 230000003628 erosive effect Effects 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims 1
- 230000000903 blocking effect Effects 0.000 abstract description 2
- 239000002210 silicon-based material Substances 0.000 description 19
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 15
- 229910052796 boron Inorganic materials 0.000 description 15
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 125000004437 phosphorous atom Chemical group 0.000 description 6
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000035772 mutation Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
Abstract
The invention discloses a kind of Trench-structure charge compensation Schottky semiconductor device, charge compensation structure is introduced by groove structure, when semiconductor device connects certain reverse biased, first conducting semiconductor material can form charge compensation with the second conducting semiconductor material inside and outside groove, improve the reverse blocking voltage of device.Present invention also offers a kind of manufacture method of Trench-structure charge compensation Schottky semiconductor device.
Description
Technical field
The present invention relates to a kind of Trench-structure charge compensation Schottky semiconductor device, and the invention further relates to a kind of groove
Structure charge compensates the manufacture method of Schottky semiconductor device.The semiconductor device of the present invention is manufacture power rectifier device
Basic structure.
Background technology
Power semiconductor is widely used in power management and power supply using upper, is related specifically to the half of schottky junction
Conductor device has turned into the important trend of device development, and schottky device has the low turn-off speed of opening of positive cut-in voltage fast etc.
Advantage, while schottky device also has reverse leakage current big, it is impossible to the shortcomings of being applied to hyperbaric environment.
Schottky diode can be manufactured by a variety of different topologies, the most frequently used for plane figure, traditional
Planer schottky diode has the Electric Field Distribution curve of mutation in drift region, have impact on the reverse breakdown characteristics of device, simultaneously
Traditional planer schottky diode has higher conducting resistance.
The content of the invention
The present invention proposes regarding to the issue above, there is provided a kind of Trench-structure charge compensation Schottky semiconductor device and its system
Make method.
A kind of Trench-structure charge compensation Schottky semiconductor device, it is characterised in that：Including：Substrate layer, it is semiconductor
Material is formed；Drift layer, formed for the first conducting semiconductor material, on substrate layer；Multiple groove structures, groove are located at
Trench wall region is abutted against in drift layer, in drift layer and is provided with the second conducting semiconductor material, trench wall surface is provided with
Insulating materials, filling semiconductor material in groove；Schottky barrier junction, positioned at drift layer the first conducting semiconductor material upper table
Face.
A kind of manufacture method of Trench-structure charge compensation Schottky semiconductor device, it is characterised in that：Including following step
Suddenly：The first conducting semiconductor material layer is formed in substrate layer surface, then surface forms insulation material layer；Carry out photoetching corrosion work
Skill removes surface portion insulation material layer, and then etching removes partial denudation semi-conducting material and forms groove；Carried out in groove
Second conductive impurity spreads；Insulating materials is formed on trench wall surface, deposits polycrystalline semiconductor material, anti-etches polycrystalline is partly led
Body material, remove surface insulation material；Barrier metal is deposited, is sintered to form schottky barrier junction.
When semiconductor device connects certain reverse biased, the first conducting semiconductor material and the second conducting semiconductor material
Charge compensation can be formed with the polycrystalline semiconductor material in groove, improves the breakdown reverse voltage of device, or is improved
The impurity doping concentration of drift region reduces the forward conduction resistance of device.
The polycrystalline semiconductor material or electrode metal of high-concentration dopant are introduced by groove top, thus it is possible to vary Schottky table
Face Electric Field Distribution, the peak electric field strength on schottky junction surface when semiconductor device connects reverse biased is reduced, so as to further carry
The reverse blocking voltage of high device.
Brief description of the drawings
Fig. 1 is a kind of Trench-structure charge compensation Schottky semiconductor device diagrammatic cross-section of the present invention；
Fig. 2 is a kind of Trench-structure charge compensation Schottky semiconductor device diagrammatic cross-section of the present invention；
Fig. 3 is a kind of Trench-structure charge compensation Schottky semiconductor device diagrammatic cross-section of the present invention.
Wherein, 1, substrate layer；2nd, silica；3rd, the first conducting semiconductor material；4th, the second conducting semiconductor material；5、
Schottky barrier junction；6th, the conducting semiconductor material of polycrystalline second；7th, polycrystalline the second conductive semiconductor material of high concentration impurities doping
Material；10th, upper surface metal level；11st, lower surface metal layer.
Embodiment
Embodiment 1
Fig. 1 is a kind of Trench-structure charge compensation Schottky semiconductor device profile of the present invention, detailed with reference to Fig. 1
Describe bright semiconductor device of the invention in detail.
A kind of Schottky semiconductor device, including：Substrate layer 1, is N conductive type semiconductor silicon materials, and phosphorus atoms are mixed
Miscellaneous concentration is 1E19/CM3, in the lower surface of substrate layer 1, pass through the extraction electrode of lower surface metal layer 11；First conductive semiconductor material
Material 3, it is the semiconductor silicon material of N conduction types, the doping concentration of phosphorus atoms is 1E16/CM on substrate layer 13；Second
Conducting semiconductor material 4, it is the semiconductor silicon material of P conduction types near trench wall, the doping concentration of boron atom is
1E16/CM3；The second conducting semiconductor material of polycrystalline 6, it is boron doped poly semiconductor silicon materials, in groove, boron atom
Doping concentration be 1E16/CM3；Schottky barrier junction 5, it is semiconductor silicon material positioned at the surface of the first conducting semiconductor material 3
The silicide that material is formed with barrier metal；Silica 2, positioned at trench wall；Device upper surface has upper surface metal level 10,
Another electrode is drawn for device.
Its manufacture craft comprises the following steps：
The first step, the first conducting semiconductor material layer 3 is epitaxially formed on the surface of substrate layer 1, and deposit forms silicon nitride layer；
Second step, lithography corrosion process is carried out, semiconductor material surface removes partial silicon nitride, and then etching removes part
Bare semiconductor silicon materials form groove；
3rd step, boron impurity diffusion is carried out in groove；
4th step, silica 2 is formed in groove internal heating oxidation, the second conducting semiconductor material of deposit polycrystalline 6, is anti-carved more
Brilliant second conducting semiconductor material 6, erosion removal silicon nitride layer；
5th step, barrier metal is deposited in semiconductor material surface, is sintered to form schottky barrier junction 5, Ran Hou
Surface deposition metal forms upper surface metal level 10；
6th step, back side metallization technology is carried out, overleaf form lower surface metal layer 11, as shown in Figure 1.
Embodiment 2
Fig. 2 is a kind of Trench-structure charge compensation Schottky semiconductor device profile of the present invention, detailed with reference to Fig. 2
Describe bright semiconductor device of the invention in detail.
A kind of Schottky semiconductor device, including：Substrate layer 1, is N conductive type semiconductor silicon materials, and phosphorus atoms are mixed
Miscellaneous concentration is 1E19/CM3, in the lower surface of substrate layer 1, pass through the extraction electrode of lower surface metal layer 11；First conductive semiconductor material
Material 3, it is the semiconductor silicon material of N conduction types, the doping concentration of phosphorus atoms is 1E16/CM on substrate layer 13；Second
Conducting semiconductor material 4, it is the semiconductor silicon material of P conduction types near trench wall, the doping concentration of boron atom is
1E16/CM3；The second conducting semiconductor material of polycrystalline 6, it is boron doped poly semiconductor silicon materials, in groove, boron atom
Doping concentration be 1E16/CM3；Schottky barrier junction 5, it is semiconductor silicon material positioned at the surface of the first conducting semiconductor material 3
The silicide that material is formed with barrier metal；Silica 2, positioned at trench wall；Device upper surface and groove internal upper part are with upper
Surface metal-layer 10, another electrode is drawn for device.
Its manufacture craft comprises the following steps：
The first step, the first conducting semiconductor material layer 3 is epitaxially formed on the surface of substrate layer 1, and deposit forms silicon nitride layer；
Second step, lithography corrosion process is carried out, semiconductor material surface removes partial silicon nitride, and then etching removes part
Bare semiconductor silicon materials form groove；
3rd step, boron impurity diffusion is carried out in groove；
4th step, silica 2 is formed in groove internal heating oxidation, the second conducting semiconductor material of deposit polycrystalline 6, is anti-carved more
Brilliant second conducting semiconductor material 6 forms groove, erosion removal silicon nitride layer；
5th step, barrier metal is deposited in semiconductor material surface, is sintered to form schottky barrier junction 5, Ran Hou
Surface deposition metal forms upper surface metal level 10；
6th step, back side metallization technology is carried out, overleaf form lower surface metal layer 11, as shown in Figure 2.
Embodiment 3
Fig. 3 is a kind of Trench-structure charge compensation Schottky semiconductor device profile of the present invention, detailed with reference to Fig. 3
Describe bright semiconductor device of the invention in detail.
A kind of Schottky semiconductor device, including：Substrate layer 1, is N conductive type semiconductor silicon materials, and phosphorus atoms are mixed
Miscellaneous concentration is 1E19/CM3, in the lower surface of substrate layer 1, pass through the extraction electrode of lower surface metal layer 11；First conductive semiconductor material
Material 3, it is the semiconductor silicon material of N conduction types, the doping concentration of phosphorus atoms is 1E16/CM on substrate layer 13；Second
Conducting semiconductor material 4, it is the semiconductor silicon material of P conduction types near trench wall, the doping concentration of boron atom is
1E16/CM3；The second conducting semiconductor material of polycrystalline 6, is boron doped poly semiconductor silicon materials, the bottom in groove, boron
The doping concentration of atom is 1E16/CM3；The second conducting semiconductor material of polycrystalline 7 of high concentration impurities doping, it is boron doped more
Brilliant semiconductor silicon material, positioned at groove internal upper part, the doping concentration of boron atom is 1E18/CM3；Schottky barrier junction 5, positioned at
The surface of one conducting semiconductor material 3, it is the silicide that semiconductor silicon material is formed with barrier metal；Silica 2, positioned at ditch
Groove inwall；Device upper surface has upper surface metal level 10, and another electrode is drawn for device.
Its manufacture craft comprises the following steps：
The first step, the first conducting semiconductor material layer 3 is epitaxially formed on the surface of substrate layer 1, and deposit forms silicon nitride layer；
Second step, lithography corrosion process is carried out, semiconductor material surface removes partial silicon nitride, and then etching removes part
Bare semiconductor silicon materials form groove；
3rd step, boron impurity diffusion is carried out in groove；
4th step, silica 2 is formed in groove internal heating oxidation, the second conducting semiconductor material of deposit polycrystalline 6, injects boron
Impurity is annealed, and anti-carves the conducting semiconductor material of polycrystalline second, erosion removal silicon nitride layer；
5th step, barrier metal is deposited in semiconductor material surface, is sintered to form schottky barrier junction 5, Ran Hou
Surface deposition metal forms upper surface metal level 10；
6th step, back side metallization technology is carried out, overleaf form lower surface metal layer 11, as shown in Figure 3.
The present invention is elaborated by examples detailed above, while other examples can also be used to realize the present invention, not office of the invention
It is limited to above-mentioned instantiation, therefore the present invention is limited by scope.
Claims (6)
- A kind of 1. Trench-structure charge compensation Schottky semiconductor device, it is characterised in that：Including：Substrate layer, formed for high concentration impurities doped semiconductor materials；Drift layer, formed for the first conducting semiconductor material, on substrate layer；It is multipleGroove structure, groove are located in drift layer, and trench wall region is abutted against in drift layer and is provided with the second conductive semiconductor material Material, trench wall surface are provided with insulating materials, under-filled second conductive polycrystalline semi-conducting material in groove, groove internal upper part Fill the polycrystalline semiconductor material of high concentration impurities doping；Abut against the conducting semiconductor material of trenched side-wall second, the second conductive polycrystalline semi-conducting material under-filled in groove and drift Move the conducting semiconductor material of layer first and form charge compensation structure；Schottky barrier junction, positioned at the first conducting semiconductor material of drift layer upper surface；Upper and lower surface metal level, upper surface metal level connection schottky barrier junction, the second conducting semiconductor material upper surface and ditch Polycrystalline semiconductor material upper surface in groove, lower surface metal layer are located at the substrate layer back side.
- 2. semiconductor device as claimed in claim 1, it is characterised in that：The insulating materials on described trench wall surface is two Silica.
- 3. semiconductor device as claimed in claim 1, it is characterised in that：In described the second conducting semiconductor material and groove Filling semiconductor material is isolated by trench wall surface insulation material.
- 4. semiconductor device as claimed in claim 1, it is characterised in that：Described Schottky barrier becomes barrier metal and The barrier junction that one conducting semiconductor material is formed.
- 5. semiconductor device as claimed in claim 1, it is characterised in that：Described abuts against the conductive semiconductor of trenched side-wall second Material surface forms schottky barrier junction.
- 6. a kind of manufacture method of Trench-structure charge compensation Schottky semiconductor device as claimed in claim 1, its feature It is：Comprise the following steps：1) the first conducting semiconductor material layer is formed in substrate layer surface, is then formed in the first conducting semiconductor material layer surface Insulation material layer；2) carry out lithography corrosion process and remove surface portion insulation material layer, then etching removes partial denudation semi-conducting material shape Into groove；3) the second conductive impurity diffusion is carried out in groove；4) insulating materials is formed on trench wall surface, deposits the second conductive polycrystalline semi-conducting material, inject the second conductive impurity Annealing, erosion polycrystalline semiconductor material is anti-carved, remove surface insulation material；5) barrier metal is deposited, is sintered to form schottky barrier junction；6) metal is deposited in upper surface, forms upper surface metal level, connection schottky barrier junction, on the second conducting semiconductor material Polycrystalline semiconductor material upper surface in surface and groove, back side metallization technology is carried out, overleaf forms lower surface metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210269963.2A CN103579373B (en) | 2012-07-31 | 2012-07-31 | A kind of Trench-structure charge compensation Schottky semiconductor device and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210269963.2A CN103579373B (en) | 2012-07-31 | 2012-07-31 | A kind of Trench-structure charge compensation Schottky semiconductor device and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103579373A CN103579373A (en) | 2014-02-12 |
| CN103579373B true CN103579373B (en) | 2018-01-12 |
Family
ID=50050736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210269963.2A Active CN103579373B (en) | 2012-07-31 | 2012-07-31 | A kind of Trench-structure charge compensation Schottky semiconductor device and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103579373B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001068688A (en) * | 1999-08-26 | 2001-03-16 | Fuji Electric Co Ltd | Manufacture of schottky barrier diode and schottky barrier diode |
| CN101510557A (en) * | 2008-01-11 | 2009-08-19 | 艾斯莫斯技术有限公司 | Superjunction device having a dielectric termination and methods for manufacturing the device |
-
2012
- 2012-07-31 CN CN201210269963.2A patent/CN103579373B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001068688A (en) * | 1999-08-26 | 2001-03-16 | Fuji Electric Co Ltd | Manufacture of schottky barrier diode and schottky barrier diode |
| CN101510557A (en) * | 2008-01-11 | 2009-08-19 | 艾斯莫斯技术有限公司 | Superjunction device having a dielectric termination and methods for manufacturing the device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103579373A (en) | 2014-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103137710B (en) | A kind of groove Schottky semiconductor device with multiple insulator separation and preparation method thereof | |
| CN103199119B (en) | Groove schottky semiconductor device with super junction structure and manufacturing method thereof | |
| CN103137688B (en) | Semiconductor device with ditch groove metal oxide semiconductor (MOS) structure and manufacture method thereof | |
| CN103378171B (en) | A kind of groove Schottky semiconductor device and preparation method thereof | |
| CN103545381B (en) | A kind of horizontal structure groove Schottky semiconductor device and preparation method thereof | |
| CN103367396B (en) | Super junction Schottky semiconductor device and preparation method thereof | |
| CN103515450B (en) | Groove charge compensation Schottky semiconductor device and manufacturing method thereof | |
| CN103579373B (en) | A kind of Trench-structure charge compensation Schottky semiconductor device and its manufacture method | |
| CN103378178B (en) | Schottky semiconductor device with groove structures and preparation method thereof | |
| CN103515449B (en) | One kind has charge compensation groove Schottky semiconductor device and preparation method thereof | |
| CN103378172B (en) | Schottky semiconductor device and method for preparing same | |
| CN103378177B (en) | Schottky semiconductor device with grooves and preparation method thereof | |
| CN103378176B (en) | One kind has charge compensation Schottky semiconductor device and its manufacture method | |
| CN103489895B (en) | A kind of trench super junction semiconductor device | |
| CN103378170A (en) | Schottky semiconductor device with super junction and preparation method thereof | |
| CN103390651B (en) | Groove schottky semiconductor device and manufacturing method thereof | |
| CN103367462A (en) | Schottky semiconductor device with insulating layer isolated super-junction structure and preparation method for Schottky semiconductor device | |
| CN103367438B (en) | A kind of semiconductor device of metal semiconductor charge compensation and preparation method thereof | |
| CN103199102A (en) | Schottky semiconductor device with super junction structure and manufacturing method thereof | |
| CN103390652B (en) | Groove charge compensation schottky semiconductor device and manufacture method thereof | |
| CN103681778B (en) | Groove charge compensation schottky semiconductor device and preparation method thereof | |
| CN103383969B (en) | Schottky device and manufacturing method thereof | |
| CN103208533B (en) | Schottky super junction semiconductor device and preparation method thereof | |
| CN103137711A (en) | Schottky semiconductor device with insulating layer isolation structure and preparation method thereof | |
| CN103378174B (en) | Schottky semiconductor device with charge compensation and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210426 Address after: Room 301, 3rd floor, building 16, Guangxi Huike Technology Co., Ltd., No. 336, East extension of Beihai Avenue, Beihai Industrial Park, 536000, Guangxi Zhuang Autonomous Region Patentee after: Beihai Huike Semiconductor Technology Co.,Ltd. Address before: 113200 Fushun City, Liaoning Province Xinbin Manchu Autonomous County Federation of disabled persons Patentee before: Zhu Jiang |