CN103579318B - Multiple-gate transistors and manufacture method thereof - Google Patents

Multiple-gate transistors and manufacture method thereof Download PDF

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Publication number
CN103579318B
CN103579318B CN201210284812.4A CN201210284812A CN103579318B CN 103579318 B CN103579318 B CN 103579318B CN 201210284812 A CN201210284812 A CN 201210284812A CN 103579318 B CN103579318 B CN 103579318B
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semiconductor substrate
bridge
gate transistors
semiconductive bridge
semiconductive
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CN103579318A (en
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陈逸男
徐文吉
叶绍文
刘献文
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Nanya Technology Corp
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Nanya Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate

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  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a kind of multiple-gate transistors and manufacture method thereof, this transistor comprises: semiconductor substrate; One W shape groove, is positioned at a part for this semiconductor substrate and extends according to a first direction; Semiconductor bridge, according to extending on this semiconductor substrate perpendicular to a second direction of this first direction, this semiconductive bridge is across the part of this W shape groove and link this semiconductor substrate, and this semiconductive bridge has a flat top and a circular-arc bottom surface; Monoxide layer, partly around this flat top of this semiconductive bridge and a part for this circular-arc bottom surface; And a conductive layer, extend and be formed on this semiconductor substrate and this oxide skin(coating) according to this first direction, wherein this conductive layer fills in this W shape groove around this oxide skin(coating) part. The present invention has improved the combination between raceway groove and grid, increases grid for the control of raceway groove potential energy, the performance while contributing to the inhibition of short-channel effect and micro metal oxide semiconductor transistor.

Description

Multiple-gate transistors and manufacture method thereof
Technical field
The present invention relates to semiconductor fabrication, and be particularly related to a kind of multiple-gate transistors (multi-gateAnd manufacture method transistor).
Background technology
In the making of ultra-large type integrated (ULSI) circuit, mos field effect transistor(metal-oxidesemiconductorfieldeffecttransistor; MOSFET) manufacturing technology is occupied certainlyImpact qualitatively. Ten over several years, by the reduction of MOSFET size can reach element speed performance,Current densities and unit cost are improved. And in the time that the gate length of Traditional bulk MOSFET reduces, source electrode/ drain electrode just easily and channel region generation effect and affect the potential energy in it. So, there is shorter gate lengthTransistor may meet with as problems such as the channel switches states of uncontrollable grid.
The attenuating phenomenon with the transistorized gate groove control ability of short gate length will cause short-channel effect.And doping content, minimizing gate oxide thickness and the shallow source/drain joint etc. that increase main body are in order to reduceShort-channel effect cannot be satisfied with the traditional element structure as used bulk silicon base material. Therefore need soIn FEOL technology, the component structure of innovation or other types dwindles trend to maintain so element.
Be less than 30 nanometers when element is reduced to, adopt if multiplex grid structure is to control the side of short-channel effectMethod is disclosed. Dissimilar transistor arrangement is for example multiple-gate transistors, and multiple-gate transistorsBe for example dual-gate transistor, triple gate transistor, Omega type field-effect transistor and circulating typeGate transistor or parcel circulating type gate transistor. The use of multiple-gate transistors, can make complementary type metalThe manufacture of oxide semiconductor, surmounts the restriction of Traditional bulk mos field effect transistor,And more reduce and reach the limit restriction of the mos field effect transistor of silicon material. VolumeThe use of outer grid, improved the combination between raceway groove and grid, and increased grid for raceway groove potential energyControl, and help the inhibition of short-channel effect, and elongated the contracting of metal oxide semiconductor transistorLittle.
Summary of the invention
In view of this,, for solving the problem of prior art, according to an embodiment, the invention provides oneMultiple-gate transistors, comprising:
Semiconductor substrate; One W shape groove, is positioned at a part for this semiconductor substrate and according to oneOne direction is extended; Semiconductor bridge, according to extending this perpendicular to a second direction of this first direction partlyOn conductor substrate, this semiconductive bridge is across the part of this W shape groove and link this semiconductor substrate, shouldSemiconductive bridge has a flat top and a circular-arc bottom surface; Monoxide layer, partly around this partlyThis flat top of conducting bridge and a part for this circular-arc bottom surface; And a conductive layer, according to this firstDirection is extended and is formed on this semiconductor substrate and this oxide skin(coating), and wherein this conductive layer is around this oxidationThing layer also partly fills in this W shape groove.
According to another embodiment, the invention provides a kind of manufacture method of multiple-gate transistors, comprising:
Semiconductor substrate is provided; In this semiconductor substrate, in a part, form W shape groove and a halfConducting bridge, wherein this W shape groove is positioned at a part for this semiconductor substrate and prolongs according to a first directionStretch, and this semiconductive bridge extends this semiconductor substrate according to the second direction perpendicular to this first directionUpper and across the part of this W shape groove and link this semiconductor substrate, it is one flat that this semiconductive bridge hasSmooth end face and a circular-arc bottom surface; Form monoxide layer, this oxide skin(coating) is partly partly led around thisThis flat top of body bridge and a part for this circular-arc bottom surface; And formation one conductive layer, this conductive layerExtend and be formed on this semiconductor substrate and this oxide skin(coating) wherein this conductive layer according to this first directionAlso partly fill in this W shape groove around this oxide skin(coating).
The performance of multiple-gate transistors of the present invention also can surmount Traditional bulk metal oxide semiconductcor field effectAnswer transistor restriction, there is extra grid control ability, thereby improved the combination between raceway groove and gridAnd increased the control of grid for raceway groove potential energy, so contribute to the inhibition of short-channel effect and in micro-Performance when receding metal oxide semi conductor transistor.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, cited below particularly one is preferably realExecute example, and coordinate appended accompanying drawing, be described in detail below:
Brief description of the drawings
Fig. 1-16 have shown the manufacture method according to the multiple-gate transistors of one embodiment of the invention, whereinFig. 1,3,5,7,9,11,14 is a series of top views, and Fig. 2,4,6,8,10,12,13,15,16 is a series of profiles.
[main description of reference numerals]
100 ~ semiconductor substrate;
100a ~ semiconductive bridge;
The residual fraction of 100b ~ semiconductor substrate;
102 ~ isolated component;
104 ~ active area;
106 ~ mask layer;
108 ~ opening;
110 ~ etch process;
112 ~ groove;
114 ~ etch process;
116 ~ groove;
118 ~ end face;
120 ~ bottom surface;
122 ~ thermal oxidation technology;
124 ~ oxide skin(coating);
126 ~ conductive layer;
128 ~ ion cloth is planted technique;
130 ~ conductiving doping district;
D ~ degree of depth.
Detailed description of the invention
The manufacture according to the multiple-gate transistors of one embodiment of the invention with explanation by Fig. 1-16 belowMethod, wherein Fig. 1,3,5,7,9,11,14 is a series of top views, and Fig. 2,4,6,8,10,12,13,15,16 is a series of profiles, and it has shown respectively many in the different fabrication stagesThe situation of heavy gate transistor.
Please refer to Fig. 1-2, first semiconductor substrate 100 is provided, in it, be formed with multiple isolated components102, the plurality of isolated component defines multiple active areas 104 of separating mutually in semiconductor substrate 100,With thereon and/or an element (not shown) is set in it. In an embodiment, semiconductor substrate 100 examplesAs be a bulk silicon substrate (bulksiliconsubstrate), and be formed at the isolation in semiconductor substrate 100102 of elements are to comprise if the shallow trench isolation of the insulating materials of silica is from (shallowtrenchIsolation, STI) element.
As shown in the top view of Fig. 1, multiple isolated components 102 comprise according in Fig. 1 directions X extend andExtend and be with multiple strip isolated components 102 of separation and according to Y-direction in Fig. 1 for parallel to each otherMultiple strip isolated components 102 with separating parallel to each other, and extend according to X in Fig. 1 and Y-directionMultiple strip isolated components 102 are substantially overlooked form according to one " well " shape and are mutually intersected, and then in halfIn conductor substrate 100, define multiple active areas 104. Can be in multiple active areas 104 in subsequent techniqueIn and/or the identical or different at least one element (not shown) of upper formation.
Please refer to Fig. 2, shown the section situation along line segment 2-2 in Fig. 1, its part has shown edgeThe multiple isolated components 102 that arrange on directions X in Fig. 1 with and multiple active areas 104 of being definedInterior semiconductor substrate 100.
Please refer to Fig. 3-4, on semiconductor substrate 100, smooth covering forms a mask layer 106. In an enforcementIn example, mask layer 106 is for example silicon nitride layer, and it can be by as a method institute shape of chemical vapour deposition (CVD)Become. Then the suitable optical mask pattern (all aobvious by suitable photoetching and the enforcement of etch process of arranging in pairs or groupsShow), two openings 108 of separating mutually with the interior formation of mask layer 106 in active area 104.
As shown in Figure 3, multiple openings 108 are formed at respectively mask layer 106 in an active area 104Different piece, it has substantially oval-shaped one overlooks external form. As shown in Figure 4, shown along in Fig. 3A section situation in line segment 4-4, has partly shown and has been positioned at the active area that isolated component 102 definesTwo openings 108 of the mask layer 106 on 104. At this, two 108 of openings are mask layer 106Institute separates.
Please refer to Fig. 5-6, then implement an etch process 110 for structure shown in Fig. 3-4, to be etched toThe semiconductor substrate 100 that opening 108 exposes. In an embodiment, etch process 108 is for example oneDry etching process, it can adopt as Cl2、HBr、CH2F2、O2Etch chemistries. In etch processIn 110, adopt the mask layer 106 that is formed with opening 108 to remove as opening taking part as etching maskA part for 108 semiconductor substrates that expose 100, and then semiconductor-based in an active area 104Two grooves 112 of the interior formation of plate 100. Two grooves 112 are separated mutually for semiconductor substrate 100, andThere is the oval-shaped situation of overlooking of a cardinal principle that is same as opening 108. But, opening 108 and groove 112Shape not for ellipse is limited, it also can be as circle or polygonal other shapes.
As shown in Figure 6, shown along the section situation in line segment 6-6 in Fig. 5, its shown by everyTwo grooves 112 in the semiconductor substrate 100 of the active area 104 defining from element 102, andTwo grooves 112 are separated mutually for semiconductor substrate 100. In an embodiment, groove 112 has distanceOne depth D of the about 1500-2500 dust of end face of semiconductor substrate 100.
Please refer to Fig. 7-8, then implement an etch process 114 for structure shown in Fig. 5-6. In an enforcementIn example, etch process 114 is a wet etching, and it adopts as HF, NH4OH、H2O2Etching chemistryProduct. In etch process 114, part is removed in the active area 104 that is formed with opening 108 and is adjacent toSemiconductor substrate 100 parts of groove 112 (please refer to Fig. 5-6). After etch process 108 is implemented, pointEvery the below part of the semiconductor substrate 100 of groove 112 (please refer to Fig. 5-6) by etched removal, and thenConducting groove 112 (please refer to Fig. 5-6) becomes single groove 116, and in a part for groove 116The semiconductor bridge 100a that is formed with leap, the two ends of this semiconductive bridge 100a are linked to respectively active areaIn 104, without other parts of etched semiconductor substrate 100, groove 116 has exposed and has been formed withThe residual fraction 100b of the semiconductor substrate in the active area 104 of this groove 116.
As shown in Figure 6, show along the section situation in line segment 6-6 in Fig. 5, shown in this partInterior the formed groove 116 of active area 104 defining in isolated component 102, be positioned at groove 116The semiconductive bridge 100a of the surface of an interior part and the semiconductor substrate that exposes for groove 116 residualStay part 100b. At this, groove 116 has the section situation of W shape substantially, and semiconductive bridge 100aThere is a substantially semicircular section situation, and semiconductive bridge 100a has contact mask layer 106 and for largeThe end face 118 that body is smooth and contact trench 116 and be a substantially circular-arc bottom surface 120, and beThe residual fraction 100b of semiconductor substrate that groove 116 exposes also has a substantially round and smooth W shape surface.
Please refer to Fig. 9-10, then implement an etch process (not shown) for structure shown in Fig. 7-8, withRemove the mask layer 106 being formed on semiconductor substrate 100 completely, and expose semiconductor substrate 100, halfThe surface of the residual fraction 100b of conducting bridge 100a and semiconductor substrate and expose and be formed at an active areaA groove 116 in 104. Then implement a thermal oxidation technology 122, with partly leading in active area 104Structure base board 100, semiconductive bridge 100a and the residual fraction for semiconductor substrate that lead-through opening 116 exposesOn the surface of 100b, form oxide skin(coating) 124, it has the thickness between 10-50 dust. In an enforcementIn example, semiconductor substrate 100 is a bulk silicon substrate, and thermal oxidation technology 122 is for example wet type or dryThe thermal oxidation technology of formula, it can adopt as H2、O2、N2, Ar chemicals and between 800-1000DEG C temperature under implement, to form the oxide skin(coating) 124 that comprises silica material.
As shown in figure 10, shown that it has shown shape along the section situation in line segment 10-10 in Fig. 9Be formed in the semiconductive bridge 100a in the active area 104 that isolated component 102 defines and be groove 116The lip-deep oxide skin(coating) 124 of the residual fraction 100b of the semiconductor substrate exposing with and contiguousThe lip-deep oxide skin(coating) 124 of semiconductor substrate 100 of active area 104. At this, oxide skin(coating) 124Substantially arrange with bottom surface 120 around the end face 118 of semiconductive bridge 100a, and be also substantially formed at as ditchGroove 116 exposes on the W shape surface of residual fraction 100b of semiconductor substrate.
Please refer to Figure 11-13, then carry out a depositing operation (not shown) for structure shown in Fig. 9-10,With the smooth ground deposits conductive material of covering on semiconductor substrate 100, with capping oxide layer 124 and fill up ditchGroove 116. Then, adopt the enforcement of suitable photoetching and etch process and arrange in pairs or groups suitable optical mask pattern (allDo not show) with this conductive material of patterning, and then a conductive layer 126 of strip.
As shown in figure 11, the conductive layer 126 of this strip extends and has covered number along directions X in Figure 11Individual active area 104 and isolated component 102, it also partly fills in groove 116, and groove 116 is stillExpose one of oxide skin(coating) 124 on the residual fraction 100b that forms semiconductor substrate 100 in the innerPart. In an embodiment, the conductive material of conductive layer 126 is for example that it can through the polysilicon of dopingFormed by the method as chemical vapour deposition (CVD).
As shown in figure 12, shown along the section situation in line segment 12-12 in Figure 11, in this demonstrationBe formed at interior covering of active area 104 that isolated component 102 defines and be positioned at semiconductive bridge 100aAnd the lip-deep silicon oxide layer 124 of the residual fraction 100b of the semiconductor substrate exposing for groove 116With and the conductive layer of the lip-deep silicon oxide layer 124 of semiconductor substrate 100 of contiguous active area 104126。
Moreover, as shown in figure 13, show along the section situation in line segment 13-13 in Figure 11, byPass through that patterning forms but do not filled up groove 116 completely in conductive layer 126, therefore shown at thisBeing formed at interior covering of active area 104 that isolated component 102 defines is positioned at semiconductive bridge 100a and isThe lip-deep silicon oxide layer 124 of the residual fraction 100b of the semiconductor substrate that groove 116 exposes andOne of the lip-deep silicon oxide layer 124 of semiconductor substrate 100 of its contiguous active area and groove 116Part.
Please refer to Figure 14-16, then implement an etch process (not shown), adopt conductive layer 126 as erosionCarve mask, remove silicon oxide layer 124 parts that do not cover for conductive layer 126, and exposed each activeThe semiconductor substrate 100, semiconductive bridge 100a and the semiconductor that in district 104, do not cover for conductive layer 126The surface of the residual fraction 100b of substrate. In an embodiment, above-mentioned etch process is for example a dry ecthingTechnique, it has adopted as CF4、CH2F2, HBr, Ar etch chemistries. Then, implement one fromSub-cloth is planted technique 128, and adopts conductive layer 126 to plant mask as cloth, plants suitable ion to respectively having with clothSemiconductor substrate 100, the semiconductive bridge 100a not covering for conductive layer 126 in source region 104 and partly leadingIn the residual fraction 100b of structure base board, and then form in the inner a conduction region 130. In an embodiment,According to the transistorized conduction form forming, ion cloth is planted technique 128 and can be adopted as the N-shaped of phosphorus, arsenicIon or as the p-type ion of boron, and the conduction region 130 forming can have the conduction shape of N-shaped or p-typeState.
As shown in figure 15, shown along the section situation in line segment 15-15 in Figure 14, in this demonstrationBe formed at interior covering of active area 104 that isolated component 102 defines and be positioned at semiconductive bridge 100aAnd the lip-deep silicon oxide layer of the residual fraction 100b of the semiconductor substrate exposing for lead-through opening 116124 with and the conductive layer of the lip-deep silicon oxide layer 124 of semiconductor substrate 100 of contiguous active area126。
Moreover, as shown in figure 16, show along the section situation in line segment 16-16 in Figure 14, inImplement ion cloth and plant after technique 128, in partly leading of two symmetrical sides of the interior adjacent trenches 116 of active area 104The conductiving doping district 130 having formed in a part for structure base board 100, using as transistorized source/drainThe utmost point.
In after process implementing as shown in Fig. 1-16, just can obtain the one according to one embodiment of the inventionMultiple-gate transistors, as shown in Figure 14-16, comprising:
Semiconductor substrate (for example semiconductor substrate 100); One W shape groove (for example groove 116), is positioned atIn the part of semiconductor substrate and for example, extend according to a first direction (directions X); Semiconductor bridge (exampleAs semiconductive bridge 100a), for example, extend semiconductor according to the second direction perpendicular to first direction (Y)On substrate, semiconductive bridge is across the part of this W shape groove and link this semiconductor substrate, semiconductive bridgeThere is a flat top (for example end face 118) and a circular-arc bottom surface (for example bottom surface 120); MonoxideLayer (for example oxide skin(coating) 124), partly around the flat top of semiconductive bridge and of circular-arc bottom surfacePoint; And a conductive layer (for example conductive layer 126), extend and be formed at semiconductor substrate according to first directionOn oxide skin(coating), wherein conductive layer also partly fills in W shape groove around oxide skin(coating).
In another embodiment, above-mentioned multiple-gate transistors also comprises that pair of conductive doped region (for example mix by conductionAssorted district 130), be arranged at respectively along a part for the semiconductive bridge of the symmetrical side of the conductive layer in second directionIn a part for the semiconductor substrate linking with semiconductive bridge, using as source/drain region.
The performance of the multiple-gate transistors as shown in Figure 14-16 also can surmount Traditional bulk metal oxide halfThe restriction of conductor field-effect transistor, has extra grid control ability, thereby has improved raceway groove and gridBetween combination and increased the control of grid for raceway groove potential energy, so contribute to the inhibition of short-channel effectAnd performance in the time of micro metal oxide semiconductor transistor.
Although the present invention with preferred embodiment openly as above, so it is not in order to limit the present invention, anyThose of ordinary skill in the art, without departing from the spirit and scope of the present invention, when doing to change and retouching,Therefore the scope that protection scope of the present invention ought define depending on appended claim is as the criterion.

Claims (10)

1. a multiple-gate transistors, is characterized in that, comprising:
Semiconductor substrate;
One W shape groove, is positioned at a part for this semiconductor substrate and extends according to a first direction;
Semiconductor bridge, extends this semiconductor substrate according to the second direction perpendicular to this first directionUpper, this semiconductive bridge is across the part of this W shape groove and link this semiconductor substrate, this semiconductive bridgeThere is a flat top and a circular-arc bottom surface;
Monoxide layer, partly around one of this flat top of this semiconductive bridge and this circular-arc bottom surfacePart; And
One conductive layer, extends and is formed on this semiconductor substrate and this oxide skin(coating) according to this first direction,This conductive layer also partly fills in this W shape groove around this oxide skin(coating).
2. multiple-gate transistors according to claim 1, is characterized in that, also comprises pair of conductiveDoped region, is arranged at respectively along one of this semiconductive bridge of the symmetrical side of this conductive layer in this second directionIn a part for this semiconductor substrate that part links with this semiconductive bridge, using as source/drain electrodeDistrict.
3. multiple-gate transistors according to claim 1, is characterized in that, this semiconductor substrate withThis semiconductive bridge comprises same material, and this semiconductive bridge part that is this semiconductor substrate.
4. multiple-gate transistors according to claim 3, wherein this semiconductor substrate and this semiconductorBridge comprises silicon.
5. multiple-gate transistors according to claim 1, is characterized in that, this oxide skin(coating) comprisesSilica.
6. a manufacture method for multiple-gate transistors, is characterized in that, comprising:
Semiconductor substrate is provided;
In this semiconductor substrate, in a part, form a W shape groove and semiconductor bridge, wherein this WShape groove is positioned at a part for this semiconductor substrate and extends according to a first direction, and this semiconductive bridgeAccording to extending on this semiconductor substrate and across this W shape perpendicular to a second direction of this first directionA part for groove and link this semiconductor substrate, this semiconductive bridge has a flat top and a circular arcShape bottom surface;
Form monoxide layer, this oxide skin(coating) partly around this flat top of this semiconductive bridge with shouldA part for circular-arc bottom surface; And
Form a conductive layer, this conductive layer extend according to this first direction and be formed at this semiconductor substrate withOn this oxide skin(coating), wherein this conductive layer also partly fills in this W shape groove around this oxide skin(coating)In.
7. the manufacture method of multiple-gate transistors according to claim 6, is characterized in that, also bagDraw together and form pair of conductive doped region in this semiconductive bridge of the symmetrical side of this conductive layer along in this second directionA part and the part of this semiconductor substrate of linking of this semiconductive bridge in, using as one source pole/Drain region.
8. the manufacture method of multiple-gate transistors according to claim 6, is characterized in that, should be partlyConductor substrate and this semiconductive bridge comprise same material, and this semiconductive bridge is this semiconductor substrate onePoint.
9. the manufacture method of multiple-gate transistors according to claim 8, is characterized in that, should be partlyConductor substrate and this semiconductive bridge comprise silicon.
10. the manufacture method of multiple-gate transistors according to claim 6, is characterized in that, shouldOxide skin(coating) comprises silica.
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JP2008311355A (en) * 2007-06-13 2008-12-25 Rohm Co Ltd Nitride semiconductor element
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