CN103579318A - Multiple-grid transistor and manufacturing method thereof - Google Patents

Multiple-grid transistor and manufacturing method thereof Download PDF

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Publication number
CN103579318A
CN103579318A CN201210284812.4A CN201210284812A CN103579318A CN 103579318 A CN103579318 A CN 103579318A CN 201210284812 A CN201210284812 A CN 201210284812A CN 103579318 A CN103579318 A CN 103579318A
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semiconductor substrate
semiconductive bridge
bridge
gate transistors
semiconductor
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CN201210284812.4A
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CN103579318B (en
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陈逸男
徐文吉
叶绍文
刘献文
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Nanya Technology Corp
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Nanya Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate

Abstract

The invention provides a multiple-grid transistor and a manufacturing method thereof. The transistor comprises a semiconductor substrate, a W-shaped groove, a semiconductor bridge, an oxide layer and a conducting layer. The W-shaped groove is formed in part of the semiconductor substrate and extends in a first direction. The semiconductor bridge extends in a second direction perpendicular to the first direction on the semiconductor substrate. The semiconductor bridge stretches across part of the W-shaped groove and is connected with the semiconductor substrate. The semiconductor bridge is provided with a flat top face and an arc bottom face. The oxide layer partially surrounds the flat top face of the semiconductor bridge and part of the arc bottom face. The conducting layer extends in the first direction and is formed on the semiconductor substrate and the oxide layer. The conducting layer surrounds the oxide layer and is partially filled into the W-shaped groove. According to the multiple-grid transistor and the manufacturing method thereof, combining of a channel and a grid electrode is improved, control of the grid electrode over channel potential energy is enhanced, short-channel effect restraining is facilitated, and miniature metal oxide semiconductor transistor performance is facilitated.

Description

Multiple-gate transistors and manufacture method thereof
Technical field
The present invention relates to semiconductor fabrication, and be particularly related to a kind of multiple-gate transistors (multi-gate transistor) and manufacture method thereof.
Background technology
In the making of ultra-large type integrated (ULSI) circuit, mos field effect transistor (metal-oxide semiconductor field effect transistor; MOSFET) manufacturing technology is occupied conclusive impact.Ten over several years, can reach speed performance, current densities and the unit cost of element improve by the reduction of MOSFET size.And when gate length when reduction of Traditional bulk MOSFET, source/drain just easily and channel region generation effect and affect the potential energy in it.So, the transistor that has a shorter gate length may meet with the problems such as channel switches state as uncontrollable grid.
The attenuating phenomenon with the transistorized gate groove control ability of short gate length will cause short-channel effect.And doping content, minimizing gate oxide thickness and the shallow source/drain joint etc. that increase main body cannot be satisfied with as used the traditional element structure of bulk silicon base material in order to reduce short-channel effect.Therefore so in FEOL technology, the component structure of innovation or other types dwindles trend to maintain so element.
When element is reduced to, be less than 30 nanometers, adopt as multiplex grid structure is disclosed with the method for control short-channel effect.Dissimilar transistor arrangement is for example multiple-gate transistors, and multiple-gate transistors is for example dual-gate transistor, triple gate transistor, Omega type field-effect transistor and circulating type gate transistor or parcel circulating type gate transistor.The use of multiple-gate transistors, can make the manufacture of CMOS (Complementary Metal Oxide Semiconductor), surmount the restriction of Traditional bulk mos field effect transistor, and more reduce and reach the limit restriction of the mos field effect transistor of silicon material.The use of additional gate, has improved the combination between raceway groove and grid, and has increased the control of grid for raceway groove potential energy, and helps the inhibition of short-channel effect, and has elongated dwindling of metal oxide semiconductor transistor.
Summary of the invention
In view of this, for solving the problem of prior art, according to an embodiment, the invention provides a kind of multiple-gate transistors, comprising:
Semiconductor substrate; One W shape groove, is positioned at a part for this semiconductor substrate and extends according to a first direction; Semiconductor bridge, extends on this semiconductor substrate according to the second direction perpendicular to this first direction, and this semiconductive bridge is across the part of this W shape groove and link this semiconductor substrate, and this semiconductive bridge has a flat top and a circular-arc bottom surface; Monoxide layer, partly around this flat top of this semiconductive bridge and a part for this circular-arc bottom surface; And a conductive layer, according to this first direction, extend and be formed on this semiconductor substrate and this oxide skin(coating), wherein this conductive layer is around this oxide skin(coating) and partly fill in this W shape groove.
According to another embodiment, the invention provides a kind of manufacture method of multiple-gate transistors, comprising:
Semiconductor substrate is provided; In this semiconductor substrate, in a part, form a W shape groove and semiconductor bridge, wherein this W shape groove is positioned at a part for this semiconductor substrate and extends according to a first direction, and this semiconductive bridge extends the upper of this semiconductor substrate according to the second direction perpendicular to this first direction and across the part of this W shape groove and link this semiconductor substrate, this semiconductive bridge has a flat top and a circular-arc bottom surface; Form monoxide layer, this oxide skin(coating) is partly around this flat top of this semiconductive bridge and a part for this circular-arc bottom surface; And form a conductive layer, and this conductive layer extends according to this first direction and is formed on this semiconductor substrate and this oxide skin(coating), and wherein this conductive layer also partly fills in this W shape groove around this oxide skin(coating).
The performance of multiple-gate transistors of the present invention also can surmount the restriction of Traditional bulk mos field effect transistor, there is extra grid control ability, thereby improved the combination between raceway groove and grid and increased the control of grid for raceway groove potential energy, so contribute to inhibition and the performance when micro metal oxide semiconductor transistor of short-channel effect.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and coordinate appended accompanying drawing, be described in detail below:
Accompanying drawing explanation
Fig. 1-16 have shown the manufacture method according to the multiple-gate transistors of one embodiment of the invention, and wherein Fig. 1,3,5,7,9,11,14 is a series of vertical views, and Fig. 2,4,6,8,10,12,13,15,16 is a series of profiles.
[main description of reference numerals]
100 ~ semiconductor substrate;
100a ~ semiconductive bridge;
The residual fraction of 100b ~ semiconductor substrate;
102 ~ isolated component;
104 ~ active area;
106 ~ mask layer;
108 ~ opening;
110 ~ etch process;
112 ~ groove;
114 ~ etch process;
116 ~ groove;
118 ~ end face;
120 ~ bottom surface;
122 ~ thermal oxidation technology;
124 ~ oxide skin(coating);
126 ~ conductive layer;
128 ~ ion cloth is planted technique;
130 ~ conductiving doping district;
D ~ degree of depth.
Embodiment
Below by Fig. 1-16 to explain orally the manufacture method according to the multiple-gate transistors of one embodiment of the invention, wherein Fig. 1,3,5,7,9,11,14 is a series of vertical views, and Fig. 2,4,6,8,10,12,13,15,16 is a series of profiles, it has shown respectively the situation of the multiple-gate transistors in the different fabrication stages.
Please refer to Fig. 1-2, first semiconductor substrate 100 is provided, in it, be formed with a plurality of isolated components 102, the plurality of isolated component defines mutually a plurality of active areas 104 of separating in semiconductor substrate 100, with thereon and/or an element (not shown) is set in it.In an embodiment, semiconductor substrate 100 is for example a bulk silicon substrate (bulk silicon substrate), the isolated component 102 being formed in semiconductor substrate 100 is to comprise if the shallow trench isolation of the insulating material of silica is from (shallow trench isolation, STI) element.
As shown in the vertical view of Fig. 1, a plurality of isolated components 102 comprise according to directions X in Fig. 1 and extend and extend and be a plurality of strip isolated components 102 with separating parallel to each other for a plurality of strip isolated components 102 with separating parallel to each other and according to Y-direction in Fig. 1, and substantially according to one " well " shape, overlook form and mutually intersect with a plurality of strip isolated components 102 that Y-direction is extended according to X in Fig. 1, and then in semiconductor substrate 100, define a plurality of active areas 104.Can be in a plurality of active areas 104 in subsequent technique and/or the identical or different at least one element (not shown) of upper formation.
Please refer to Fig. 2, shown the section situation along line segment 2-2 in Fig. 1, its partial display along a plurality of isolated components 102 that arrange on directions X in Fig. 1 with and a plurality of active areas 104 of being defined in semiconductor substrate 100.
Please refer to Fig. 3-4, on semiconductor substrate 100, smooth covering forms a mask layer 106.In an embodiment, mask layer 106 is for example silicon nitride layer, and it can form by the method as chemical vapour deposition (CVD).Then arrange in pairs or groups suitable optical mask pattern by suitable photoetching and the enforcement of etch process (all not showing), two openings 108 of separating mutually with the interior formation of mask layer 106 in active area 104.
As shown in Figure 3, a plurality of openings 108 are formed at respectively the different piece of the mask layer 106 in an active area 104, and it has substantially oval-shaped one overlooks external form.As shown in Figure 4, shown along the section situation in line segment 4-4 in Fig. 3, partial display be positioned at two openings 108 of the mask layer 106 on the active area 104 that isolated component 102 defines.At this, two 108 of openings are separated by mask layer 106.
Please refer to Fig. 5-6, then for structure shown in Fig. 3-4, implement an etch process 110, the semiconductor substrate 100 being exposed to be etched to opening 108.In an embodiment, etch process 108 is for example a dry etching process, and it can adopt as Cl 2, HBr, CH 2f 2, O 2etch chemistries.In etch process 110, adopt the mask layer 106 be formed with opening 108 to take part as etching mask and remove the part of the semiconductor substrate 100 being exposed as opening 108 and then two grooves 112 of the interior formation of the semiconductor substrate 100 in an active area 104.Two grooves 112 are that semiconductor substrate 100 is separated mutually, and have the oval-shaped situation of overlooking of a cardinal principle that is same as opening 108.Yet opening 108 is with the shape of groove 112 not for ellipse is limited, it also can be as circular or polygonal other shapes.
As shown in Figure 6, shown along the section situation in line segment 6-6 in Fig. 5, it has shown two grooves 112 in the semiconductor substrate 100 of the active area 104 being defined by isolated component 102, and two grooves 112 are that semiconductor substrate 100 is separated mutually.In an embodiment, groove 112 has apart from a depth D of the about 1500-2500 dust of end face of semiconductor substrate 100.
Please refer to Fig. 7-8, then for structure shown in Fig. 5-6, implement an etch process 114.In an embodiment, etch process 114 is a wet etching, and it adopts as HF, NH 4oH, H 2o 2etch chemistries.In etch process 114, part is removed to semiconductor substrate 100 parts that are adjacent to groove 112 (please refer to Fig. 5-6) in the active area 104 that is formed with opening 108.After etch process 108 is implemented, the below part of the semiconductor substrate 100 of separation groove 112 (please refer to Fig. 5-6) is by etched removal, and then conducting groove 112 (please refer to Fig. 5-6) becomes single groove 116, and in a part for groove 116, be formed with the semiconductor bridge 100a of leap, the two ends of this semiconductive bridge 100a are linked to respectively interior other parts without etched semiconductor substrate 100 in active area 104, and groove 116 has exposed the residual fraction 100b of the semiconductor substrate in the active area 104 that is formed with this groove 116.
As shown in Figure 6, shown along the section situation in line segment 6-6 in Fig. 5, at this partial display the interior formed groove 116 in active area 104 defining in isolated component 102, the semiconductive bridge 100a of surface that is positioned at groove 116 parts and the residual fraction 100b of the semiconductor substrate that exposes for groove 116.At this, groove 116 has the section situation of W shape substantially, and semiconductive bridge 100a has a semicircular section situation substantially, and semiconductive bridge 100a has contact mask layer 106 and for a substantially smooth end face 118 and contact trench 116 and be a substantially circular-arc bottom surface 120, and be that the residual fraction 100b of semiconductor substrate that groove 116 exposes also has a substantially round and smooth W shape surface.
Please refer to Fig. 9-10, then for structure shown in Fig. 7-8, implement an etch process (not shown), to remove the mask layer 106 being formed on semiconductor substrate 100 completely, and expose semiconductor substrate 100, semiconductive bridge 100a and semiconductor substrate residual fraction 100b surface and expose the groove 116 being formed in an active area 104.Then implement a thermal oxidation technology 122, take on the surface of semiconductor substrate 100 in active area 104, semiconductive bridge 100a and residual fraction 100b as semiconductor substrate that lead-through opening 116 is exposed and form oxide skin(coating) 124, it has the thickness between 10-50 dust.In an embodiment, semiconductor substrate 100 is a bulk silicon substrate, and thermal oxidation technology 122 is for example the thermal oxidation technology of wet type or dry type, and it can adopt as H 2, O 2, N 2, Ar chemicals and at the temperature between 800-1000 ℃, implement, to form the oxide skin(coating) 124 that comprises silica material.
As shown in figure 10, shown along the section situation in line segment 10-10 in Fig. 9, its shown the semiconductor substrate that is formed at the semiconductive bridge 100a in the active area 104 that isolated component 102 defines and exposes for groove 116 residual fraction 100b lip-deep oxide skin(coating) 124 with and the lip-deep oxide skin(coating) 124 of semiconductor substrate 100 of contiguous active area 104.At this, oxide skin(coating) 124 arranges with bottom surface 120 around the end face 118 of semiconductive bridge 100a substantially, and is also substantially formed on the W shape surface for the residual fraction 100b of semiconductor substrate that groove 116 exposes.
Please refer to Figure 11-13, then for structure shown in Fig. 9-10, carry out a depositing operation (not shown), with the smooth ground deposits conductive material of covering on semiconductor substrate 100, with capping oxide layer 124 and fill up groove 116.Then, adopt the enforcement of suitable photoetching and etch process and the suitable optical mask pattern of arranging in pairs or groups (all do not show) with this electric conducting material of patterning, an and then conductive layer 126 of strip.
As shown in figure 11, the conductive layer 126 of this strip extends and has covered several active areas 104 and isolated component 102 along directions X in Figure 11, it also partly fills in groove 116, and groove 116 has still exposed a part for the oxide skin(coating) 124 on the residual fraction 100b that forms semiconductor substrate 100 in the inner.In an embodiment, the electric conducting material of conductive layer 126 is for example that it can be formed by the method as chemical vapour deposition (CVD) through the polysilicon of doping.
As shown in figure 12, shown along the section situation in line segment 12-12 in Figure 11, this shown the lip-deep silicon oxide layer 124 that is formed at the interior residual fraction 100b that has covered the semiconductor substrate that is positioned at semiconductive bridge 100a and exposes for groove 116 in active area 104 that isolated component 102 defines with and the conductive layer 126 of the lip-deep silicon oxide layer 124 of semiconductor substrate 100 of contiguous active area 104.
Moreover, as shown in figure 13, shown along the section situation in line segment 13-13 in Figure 11, because conductive layer 126 has passed through that patterning forms but do not filled up groove 116 completely, thus this shown the lip-deep silicon oxide layer 124 that is formed at the interior residual fraction 100b that has covered the semiconductor substrate that is positioned at semiconductive bridge 100a and exposes for groove 116 in active area 104 that isolated component 102 defines with and the lip-deep silicon oxide layer 124 of semiconductor substrate 100 of contiguous active area and a part for groove 116.
Please refer to Figure 14-16, then implement an etch process (not shown), adopt conductive layer 126 as etching mask, remove silicon oxide layer 124 parts that do not cover for conductive layer 126, and the surface of having exposed the residual fraction 100b of the semiconductor substrate 100, semiconductive bridge 100a and the semiconductor substrate that do not cover for conductive layer 126 in each active area 104.In an embodiment, above-mentioned etch process is for example a dry etching process, and it has adopted as CF 4, CH 2f 2, HBr, Ar etch chemistries.Then, implement an ion cloth and plant technique 128, and adopt conductive layer 126 to plant mask as cloth, the cloth of take is planted suitable ion to the residual fraction 100b of the semiconductor substrate 100, semiconductive bridge 100a and the semiconductor substrate that are not covered as conductive layer 126 in each active area 104, and then has formed in the inner a conduction region 130.In an embodiment, according to formed transistorized conduction form, ion cloth is planted technique 128 and can be adopted as the N-shaped ion of phosphorus, arsenic or as the p-type ion of boron, and formed conduction region 130 can have the conduction form of N-shaped or p-type.
As shown in figure 15, shown along the section situation in line segment 15-15 in Figure 14, this shown the lip-deep silicon oxide layer 124 that is formed at the interior residual fraction 100b that has covered the semiconductor substrate that is positioned at semiconductive bridge 100a and exposes for lead-through opening 116 in active area 104 that isolated component 102 defines with and the conductive layer 126 of the lip-deep silicon oxide layer 124 of semiconductor substrate 100 of contiguous active area.
Moreover, as shown in figure 16, shown along the section situation in line segment 16-16 in Figure 14, in implementing ion cloth, plant after technique 128, the conductiving doping district 130 having formed in a part for the semiconductor substrate 100 of two symmetrical sides of the interior adjacent trenches 116 in active area 104, usings as transistorized source/drain.
In after process implementing as shown in Fig. 1-16, just can obtain a kind of multiple-gate transistors according to one embodiment of the invention, as shown in Figure 14-16, comprising:
Semiconductor substrate (for example semiconductor substrate 100); One W shape groove (for example groove 116), is positioned at a part for semiconductor substrate and for example, extends according to a first direction (directions X); Semiconductor bridge (for example semiconductive bridge 100a), for example, according to the second direction perpendicular to first direction (Y), extend on semiconductor substrate, semiconductive bridge is across the part of this W shape groove and link this semiconductor substrate, and semiconductive bridge has a flat top (for example end face 118) and a circular-arc bottom surface (for example bottom surface 120); Monoxide layer (for example oxide skin(coating) 124), partly around the flat top of semiconductive bridge and a part for circular-arc bottom surface; And a conductive layer (for example conductive layer 126), according to first direction, extend and be formed on semiconductor substrate and oxide skin(coating), wherein conductive layer is around oxide skin(coating) and partly fill in W shape groove.
In another embodiment, above-mentioned multiple-gate transistors also comprises pair of conductive doped region (for example conductiving doping district 130), be arranged at respectively along in the part for semiconductive bridge and a part for the semiconductor substrate that semiconductive bridge links of the symmetrical side of the conductive layer in second direction, using as source/drain region.
The performance of the multiple-gate transistors as shown in Figure 14-16 also can surmount the restriction of Traditional bulk mos field effect transistor, there is extra grid control ability, thereby improved the combination between raceway groove and grid and increased the control of grid for raceway groove potential energy, so contribute to inhibition and the performance when micro metal oxide semiconductor transistor of short-channel effect.
Although the present invention with preferred embodiment openly as above; so it is not in order to limit the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; when doing to change and retouching, so the scope that protection scope of the present invention ought define depending on appended claim is as the criterion.

Claims (10)

1. a multiple-gate transistors, is characterized in that, comprising:
Semiconductor substrate;
One W shape groove, is positioned at a part for this semiconductor substrate and extends according to a first direction;
Semiconductor bridge, extends on this semiconductor substrate according to the second direction perpendicular to this first direction, and this semiconductive bridge is across the part of this W shape groove and link this semiconductor substrate, and this semiconductive bridge has a flat top and a circular-arc bottom surface;
Monoxide layer, partly around this flat top of this semiconductive bridge and a part for this circular-arc bottom surface; And
One conductive layer, extends and is formed on this semiconductor substrate and this oxide skin(coating) according to this first direction, and this conductive layer also partly fills in this W shape groove around this oxide skin(coating).
2. multiple-gate transistors according to claim 1, it is characterized in that, also comprise pair of conductive doped region, be arranged at respectively along in the part for this semiconductive bridge and a part for this semiconductor substrate that this semiconductive bridge links of the symmetrical side of this conductive layer in this second direction, using as source/drain region.
3. multiple-gate transistors according to claim 1, is characterized in that, this semiconductor substrate and this semiconductive bridge comprise same material, and this semiconductive bridge part that is this semiconductor substrate.
4. multiple-gate transistors according to claim 3, wherein this semiconductor substrate and this semiconductive bridge comprise silicon.
5. multiple-gate transistors according to claim 1, is characterized in that, this oxide skin(coating) comprises silica.
6. a manufacture method for multiple-gate transistors, is characterized in that, comprising:
Semiconductor substrate is provided;
In this semiconductor substrate, in a part, form a W shape groove and semiconductor bridge, wherein this W shape groove is positioned at a part for this semiconductor substrate and extends according to a first direction, and this semiconductive bridge extends on this semiconductor substrate according to the second direction perpendicular to this first direction and across the part of this W shape groove and link this semiconductor substrate, this semiconductive bridge has a flat top and a circular-arc bottom surface;
Form monoxide layer, this oxide skin(coating) is partly around this flat top of this semiconductive bridge and a part for this circular-arc bottom surface; And
Form a conductive layer, this conductive layer extends according to this first direction and is formed on this semiconductor substrate and this oxide skin(coating), and wherein this conductive layer also partly fills in this W shape groove around this oxide skin(coating).
7. the manufacture method of multiple-gate transistors according to claim 6, it is characterized in that, also comprise in a part that forms this semiconductor substrate that pair of conductive doped region links in a part and this semiconductive bridge of this semiconductive bridge of the symmetrical side of this conductive layer along in this second direction, using as source/drain region.
8. the manufacture method of multiple-gate transistors according to claim 6, is characterized in that, this semiconductor substrate and this semiconductive bridge comprise same material, and this semiconductive bridge part that is this semiconductor substrate.
9. the manufacture method of multiple-gate transistors according to claim 8, is characterized in that, this semiconductor substrate and this semiconductive bridge comprise silicon.
10. the manufacture method of multiple-gate transistors according to claim 6, is characterized in that, this oxide skin(coating) comprises silica.
CN201210284812.4A 2012-08-10 2012-08-10 Multiple-gate transistors and manufacture method thereof Active CN103579318B (en)

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JP2008311355A (en) * 2007-06-13 2008-12-25 Rohm Co Ltd Nitride semiconductor element
US20100193770A1 (en) * 2009-02-04 2010-08-05 International Business Machines Corporation Maskless Process for Suspending and Thinning Nanowires
CN102422401A (en) * 2009-05-20 2012-04-18 国际商业机器公司 Method for forming robust top-down silicon nanowire structure using conformal nitride and such structure

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US20080191271A1 (en) * 2007-01-12 2008-08-14 Atsushi Yagishita Semiconductor device having fins fet and manufacturing method thereof
JP2008311355A (en) * 2007-06-13 2008-12-25 Rohm Co Ltd Nitride semiconductor element
US20100193770A1 (en) * 2009-02-04 2010-08-05 International Business Machines Corporation Maskless Process for Suspending and Thinning Nanowires
CN102422401A (en) * 2009-05-20 2012-04-18 国际商业机器公司 Method for forming robust top-down silicon nanowire structure using conformal nitride and such structure

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