CN103579095B - Produce the method for contact openings and the method for generation self-aligned contact structure - Google Patents

Produce the method for contact openings and the method for generation self-aligned contact structure Download PDF

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Publication number
CN103579095B
CN103579095B CN201310187935.0A CN201310187935A CN103579095B CN 103579095 B CN103579095 B CN 103579095B CN 201310187935 A CN201310187935 A CN 201310187935A CN 103579095 B CN103579095 B CN 103579095B
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self
semiconductor body
alignment structure
groove
sidewall
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CN103579095A (en
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马丁·佩尔茨尔
海莫·霍费尔
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides the method for the contact openings in generation semiconductor body and the self-aligned contact structure on semiconductor body. In described semiconductor body, produce contact openings by form multiple self-alignment structures on the first type surface of semiconductor body, each self-alignment structure is all filled in the groove forming in described semiconductor body and above described first type surface, is extending and extending on described first type surface. Adjacent described self-alignment structure has the interval facing with each other and separates sidewall. On the described sidewall of described self-alignment structure, form spacer layers. In on sidewall in described spacer layers in described self-alignment structure, between adjacent described self-alignment structure, in described semiconductor body, form opening. Each opening all has a width and the distance corresponding to the described sidewall to adjacent trenches of the thickness of described spacer layers. Can also be on semiconductor body, with or do not produce self-aligned contact structure by spacer layers.

Description

Produce the method for contact openings and the method for generation self-aligned contact structure
Priority request
The application is the U.S. Patent application No.13/235 submitting on September 19th, 2011,550 partial continuous application, and it requires the priority of the German patent application No.102010046213.6 submitting on September 21st, 2010, and the full content of these two applications is all incorporated into this by quoting mode as proof.
Background technology
Semicon industry is striven for less characteristic size all the time. For this object, must reduce the size of desired structure element. But, in this case, must not ignore tolerance limit. For this object, use more and more autoregistration production method, and make it possible to meet to compared with the requirement of minor structure, meanwhile meet the margin of tolerance that will meet.
Become known for the example of the power semiconductor technologies of self-alignment structure element from DE102004057237A1, these examples have been described the contact hole for channel/source region in the situation that of grid trench transistor. In mesa region between two grooves, produce contact hole, itself and described slot trough are from a restriction, small distance. This this can be by means of so-called " distance piece ", or utilize the oxide skin(coating) producing by thermal oxide to be used as realizing for the mask of contact etch. But " distance piece " in the situation that, tolerance is relatively large, and the in the situation that of oxide mask, especially, in the situation of grid trench transistor, in order to carry out thermal oxide, grid ditch must be made and there is the larger degree of depth.
Summary of the invention
Embodiment described herein provides the method for the self-alignment structure element in structural detail and the semiconductor devices that a kind of production has the closed tolerance limit.
The embodiment of this method generally comprises following characteristics: provide and have surperficial semiconductor body; Produce otch in this surface, wherein this otch extends to semiconductor body from the surface of semiconductor body in the direction perpendicular to described surface, and wherein this otch has base portion and at least one sidewall; On described surface and in described otch, produce the first auxiliary layer, to make the first auxiliary layer form trap above otch, wherein this well has well base portion and at least one well sidewall, the angle [alpha] of described well sidewall within the scope of forming 20 ° to 80 ° with respect to the surface of described semiconductor body; In this well, produce the second auxiliary layer at Jing Jibuchu and at least one well side-walls, wherein the first auxiliary layer and the second auxiliary layer form the common surface in similar face level place, and wherein the second auxiliary layer is by the material production that is different from the first auxiliary layer; And optionally remove the first auxiliary layer not by second auxiliary layer cover region.
The angle [alpha] of well sidewall can be very accurately set. By angle [alpha], also can very accurately be limited to the surface of semiconductor body from the distance of otch extension. Due to the material difference of the first and second auxiliary layers; by optionally removing the first auxiliary layer; also due to the protective effect of the second auxiliary layer on the first auxiliary layer; by means of the angle [alpha] of setting, can very accurately on semiconductor body surface, produce the width of the first auxiliary layer and also produce thus laterally overlapping. In this case, the selection of angle [alpha] allows to arrange the very little laterally overlapping of the first auxiliary layer on the surface of semiconductor body in conjunction with the thickness of lip-deep first auxiliary layer of semiconductor body. Therefore this form the Alignment Method with the closed tolerance limit, therefore the interval with respect to the otch in semiconductor body can be accurately set, and described interval can be kept to very little. Particularly, the structural detail producing according to described method is suitable as the mask layer for the follow-up further processing of the semiconductor body of semiconductor devices, such as the mask layer as in etching or method for implantation.
A kind of development of this method provides the first auxiliary layer being produced by HDP technique. HDP technique is a kind of method from chemical vapor deposition material, it has splash effect to the material of deposition simultaneously, that is to say, also again removes the material of deposition by peening particle, this especially occurs in the edge of deposition materials, but deposition is greater than sputtering raste. Therefore, result is in HDP technique, and layer growth entirety occurs. Edge in deposition materials flattens, but this causes the inclined surface of the edge of deposition materials, especially the angle within the scope of 35 °-50 ° with respect to first type surface.
In HDP technique, the already present edge that therefore may need protection especially, the surperficial edge such as otch with respect to semiconductor body, prevents because the splash effect of HDP technique is removed. For this object, in one embodiment, for example, before producing the first auxiliary layer, just on the surface of semiconductor body He in otch, produce continuous protective layer.
A kind of development of the present invention provides second auxiliary layer that will produce by deposit different materials in well. Therefore, keeping well sidewall be its primitive form, and also therefore in subsequent method step, still has identical size, particularly has and the second auxiliary layer sedimentary facies before angle [alpha] together.
If the second auxiliary layer is full of this well completely, simple especially production modification that Here it is. If particularly produced the common surface of the first and second auxiliary layers by CMP method, just first in the entire area in well and also produce the second auxiliary layer above the first auxiliary layer, and then, by evenly removing, the common surface of the first and second auxiliary layers very accurately can be set to similar face level height. In the situation that using CMP working apparatus, terminal stage first machinery and then chemistry remove, wherein chemical removal can very accurately finish on the first auxiliary layer.
One embodiment of the present of invention are removed the second auxiliary layer from well after being defined in the technique in region not covered by the second auxiliary layer of optionally removing the first auxiliary layer.
If remove the second auxiliary layer produce groove in semiconductor body during, just can realize especially this step. For example, in the time that the second auxiliary layer is used to such material, can use identical this material of etching media etching using with semiconductor body, being feasible by trench etch to removing the second auxiliary layer during in semiconductor body, and without extra charge. Especially, in this case, the first auxiliary layer being produced by different materials can be served as the mask of groove etching process.
The exemplary embodiments of semiconductor devices comprises following Structural Characteristics: the semiconductor body with a surface; Otch in semiconductor body, wherein otch surface from semiconductor body in the direction perpendicular to described surface extends to semiconductor body, and wherein this otch has base portion and at least one sidewall; Layer on the surface of semiconductor body and in otch, wherein this layer forms the well of otch top, this well has well base portion and at least one well sidewall, wherein this at least one well sidewall forms the angle [alpha] in 20 ° of-80 ° of scopes with respect to the surface of semiconductor body, and wherein, this layer has at least one edge 22, and described at least one Cong Jing edge, edge starts to extend in the surperficial direction of semiconductor body.
Layer in the surface of semiconductor body forms size with self-aligned manner by the angle [alpha] of sidewall, and only has the very little margin of tolerance.
Particularly, thereby may provide a kind of semiconductor element, wherein this layer covers the sidewall from otch of semiconductor body and extends past from the surface of the distance x within the scope of 50nm-150nm.
An exemplary embodiments of semiconductor devices can provide the groove forming in semiconductor body, and this groove has at least one trenched side-wall, and described at least one trenched side-wall starts to extend to semiconductor body from the edge of described layer.
In this modification, this layer can be used as the mask layer for trench etch or subsequent method step (such as implanting), it makes it possible to realize point-device characteristic size, particularly very accurate the and very little distance between otch and the groove of generation.
According to another embodiment, the method that produces contact openings in semiconductor body comprises: on the first type surface of semiconductor body, form multiple self-alignment structures, each self-alignment structure be all filled in the groove that forms in semiconductor body and contiguous have the interval facing with each other separate sidewall, above first type surface, extending and extending to the self-alignment structure on first type surface; On the sidewall of self-alignment structure, form spacer layers; And when spacer layers is positioned on the sidewall of self-alignment structure, in semiconductor body, between adjacent self-alignment structure, form opening, so that each opening all has certain width and arrives the distance of the sidewall of adjacent trenches, it is corresponding to the thickness of spacer layers.
According to a kind of embodiment of the method that produces self-aligned contact structure on semiconductor body, the method comprises: form multiple grooves, described multiple grooves extend to semiconductor body from the first type surface of semiconductor body; In the part of the bottom of groove, form the conductive plate with semiconductor body insulation; On first type surface and on the conductive plate of groove, form the first material, the first material has the recessed region on groove; Fill the recessed region of the first material with the second material; In the first material, form opening, described opening is at the Dao district (islandregion between adjacent trenches of semiconductor body, insulation layer) on extend to described first type surface, the self-alignment structure separating to form multiple intervals, comprising the second material in the recessed region of the first material; In semiconductor body, between adjacent self-alignment structure, form groove; And fill groove and the open gap between adjacent self-alignment structure to there is the material of the etching selectivity that is different from the first and second materials.
Read detailed description below and observe after accompanying drawing, those skilled in the art should understand other feature and advantage.
Brief description of the drawings
The element of accompanying drawing may not be proportional relative to each other. Similarly reference number is indicated corresponding similar portions. Can combine the feature that each illustrates embodiment, unless it repels each other. Describe in the accompanying drawings these embodiment, and in explanation thereafter in detail these embodiment have been described in detail.
Fig. 1 illustrates independent, the exemplary methods step for generation of the method for structural detail at schematic sectional view 1A-Fig. 1 E.
Fig. 2 illustrates the schematic sectional view for generation of the further method step in the method for structural detail.
Fig. 3 illustrates the schematic sectional view of the selections of the exemplary semiconductor devices with self-alignment structure element.
Fig. 4 illustrates the schematic sectional view of the selections of grid ditch power transistor.
Fig. 5 shown in schematic sectional view 5A-Fig. 5 C for produce at semiconductor body contact openings method separately, exemplary methods step.
Fig. 6 shown in schematic sectional view 6A-Fig. 6 H on semiconductor body, produce self-aligned contact structure method separately, exemplary methods step.
Detailed description of the invention
Hereinafter with reference accompanying drawing, explains exemplary embodiments in more detail. But, the invention is not restricted to the special embodiment describing, but can improve in a suitable manner and change. Following steps also within the scope of the invention,, in order to realize further embodiment, suitably combine feature and the Feature Combination of the independent feature of an embodiment and Feature Combination and another embodiment.
Figure 1A illustrates the semiconductor body 10 with first surface 11. Can, by any known semi-conducting material, particularly can produce semiconductor body 10 by silicon. Depend on application, semiconductor body 10 can carry out n doping or p doping. Particularly, semiconductor body 10 also can comprise the Semiconductor substrate that deposits epitaxial layer on it, wherein differently dope semiconductor substrates and epitaxial layer. Then, epitaxial layer can have surface 11. Exemplary use for semiconductor body 10 in power semiconductor, that is to say in the semiconductor devices that can exist between two electrodes up to the voltage of even several kilovolts of hundreds of, this semiconductor body 10 is made up of the Semiconductor substrate of high doped and the epitaxial layer of its upper light dope depositing conventionally.
Figure 1B is illustrated in the otch 12 of the surface 11 places generation of semiconductor 10. In this case, otch 12 extends to semiconductor body 10 from the surface 11 of semiconductor body 10 in the direction perpendicular to surface 11. Otch has base portion 13 and sidewall 14.
Otch 12 can have from several nanometers to several micrometer depth, described otch can be for to extend to the groove in semiconductor body 10 in elongation mode, or can be the some depression in semiconductor body 10, wherein, in plane, the form of this some depression can be for example circular, square or hexagon. Also can in otch 12, form other functional elements of semiconductor devices. As an example, for example, the electrode occurring in can being created in power semiconductor in otch 12. In these cases, as an example, in otch 12, form passage control electrode (gate electrode). In addition, even also other electrodes can be produced in otch 12, such as field plate.
Fig. 1 C is illustrated on surface 11 and in otch 12, produces the structure after the first auxiliary layer 15. In this case, the first auxiliary layer 15 itself is formed on the well 16 on otch 12, and wherein well 16 has well base portion 17 and well sidewall 18. In this case, sidewall 18 is with respect to the surface 11 angulation α of semiconductor body 10. Angle [alpha] can have the value in 20 ° of-80 ° of scopes.
In this case, the first auxiliary layer 15 is by the material production different from the material of semiconductor body 10. As an example, the material of the first auxiliary layer 15 can be dielectric. Particularly, in this case, for example oxide is (as SiO2) be applicable to.
In this case, realize and producing by this way, on otch 12, form well 16, and set up expected angle α. In this case, well sidewall 18, on the edge of the sidewall 14 of otch 12, and extends on apart from x in the restriction on the surface 11 of semiconductor body 10. For example, limited by angle [alpha] apart from x, and can be between 50nm and 150nm. In this case, also depend on the layer thickness of auxiliary layer 15 apart from x. In this case, for example, typical layer thickness is in the scope of 100nm to 500nm.
For example, the first auxiliary layer 15 can be directly at base portion 13 places or in otch 12 on already present functional element (such as on the gate electrode of having mentioned) in otch 12, produce.
For example, the first auxiliary layer 15 can pass through HDP(high concentration plasma) technique generation. This technique is CVD method and the combination of wherein removing the sputtering method of material (particularly removing the material in edge). By this HDP technique, can form the slant well sidewall 18 with angle [alpha] in simple especially mode by sputtering power and deposition are set. For example, typical sputtering power value is about 1000 watts. In this case, for example, the surface of existence with arsenic process approximately 82 seconds, process approximately 234 seconds with oxygen, or with SiH4Process approximately 100 seconds.
Fig. 1 D is illustrated in the second auxiliary layer 20 producing in well 16. In this case, first in the entire area on well base portion 17, well sidewall 18 and produce the second auxiliary layer 20 in the surface of the first auxiliary layer 15. For example, this can complete by the technique of the vapour deposition material different from the material of the first auxiliary layer 15. As an example, doping or unadulterated polysilicon or nitride (such as silicon nitride) are suitable as the material of the second auxiliary layer 20.
After this deposition in entire area, from surface removal second auxiliary layer 20 of the first auxiliary layer 15, so that the second auxiliary layer 20 is only retained in well 16. For example, can pass through chemical mechanical polishing method (CMP method) and realize surface removal the second auxiliary layer 20 from the first auxiliary layer 15. In this case, in the first method step, mechanically the second auxiliary layer 20 is removed to the just lip-deep degree at the first auxiliary layer 15 by (for example, such as by polishing and grinding). In further method step during CMP, then, finally by mechanical etching step completely from surface removal second auxiliary layer 20 of the first auxiliary layer 20, consequently the first auxiliary layer 15 and the common surface 21 that is retained in the second auxiliary layer 20 in well 16 form at similar face level place, and transition between the first auxiliary layer 15 and the second auxiliary layer 20 occurs at 23 places, well edge at surperficial 21 places. In this case, etch-stop can be played in the surface of the first auxiliary layer 15. Mode as an alternative, also can remove the second auxiliary layer 20 to etching method by waiting.
Remaining the second auxiliary layer 20 only can be partially filled well 16(as shown in the figure), or well 16 can be filled by the second auxiliary layer 20 completely. In this case, the common surface 21 shown in Fig. 1 D will form continuously on whole well 16.
Fig. 1 E illustrates the situation of optionally removing the region not covered by the second auxiliary layer 20 from the first auxiliary layer 15. Preferably, realize this selective removal by the material of selective material etching the first auxiliary layer 15 with respect to the second auxiliary layer 20. In this case, this selectively should be interpreted as to the pass of the rate of etch that refers to two kinds of different materials is the ratio of 10:1 at least. In this case, by waiting to etching method, can be in the direction towards semiconductor body surface 11, almost vertically at 23 places, well edge on surface 21 and at transition position etching the first auxiliary layer 15 from the first auxiliary layer 15 to second auxiliary layers 20. This produces such structural detail, and it is formed and had edge 22 by the first auxiliary layer 15 and the second auxiliary layer 20, and this edge extends by this way, in the direction on the surface 11 towards semiconductor body 10, extends from the well edge 23 on surface 21. Due to the corrosion of the second auxiliary layer 20, edge 22 also can have at 23 places, well edge circular a little form, so that not shape angle beta in 90 ° of the 23Chu edge, well edge between the second auxiliary layer 20 and edge 22, but form less angle beta, conventionally angle beta is in the scope from 45 ° to 90 °, particularly in the scope between 75 ° and 80 °. At the selections figure of the circular edge at 23 places, well edge shown in Fig. 1 E '.
Fig. 2 illustrates the embodiment of this method, wherein, before producing the first auxiliary layer 15, produces continuous protective layer 25, so that the edge protected seam 25 of the sidewall 14 about otch 12 at surperficial 11 places covers on the surface 11 of semiconductor body 10 and in otch 12. As a result, during the exemplary HDP technique of deposition the first auxiliary layer 15, this edge of semiconductor body 10 is protected, and makes it can be because the splash effect of HDP technique is removed.
Fig. 3 illustrates the exemplary embodiments of this method, wherein in semiconductor body 10, produces groove 30, and its middle level 15 is as mask layer. In this case, can produce groove 30 by anisotropic etching process, wherein, in exemplary silicon semiconductor body 10 and polysilicon the material as the second auxiliary layer 20, similarly follow the second auxiliary layer 20 etching and thereby remove described the second auxiliary layer with the anisotropic etching of groove 30, to do not cover well base portion 17 and well sidewall 18.
Fig. 4 illustrates the example having as the semiconductor devices of the grid ditch of otch 12. In lower area in grid ditch 12, form field plate 36, described field plate insulate by field dielectric 37 and semiconductor body 10. Passage control electrode 35 is arranged in the upper area of grid ditch 12 in the mode insulating with field plate 36. Passage control electrode 35 is also by such as SiO of gate-dielectric 41(2Gate-dielectric) insulate with the passage area 38 forming in semiconductor body 10. Gate-dielectric 41 be implemented turn to thinner than field dielectric 37. Passage area 38 arranges along the grid ditch 12 between the source region 39 forming in semiconductor body 10 and the drain region 40 of contiguous field plate 36. In the layer 15 grid ditch 12 being disposed on passage control electrode 35, layer 15 forms well 16 on grid ditch 12. In this case, well 16 has well base portion 17 and well sidewall 18, and described well sidewall forms 20 ° of-80 ° of scopes with respect to the surface 11 of semiconductor body 10, particularly the angle [alpha] within the scope of approximately 40 °-45 °. Layer 15 is limited by edge 22. Edge 22 extends by this way, in the direction on the surface 11 towards semiconductor body 10, starts from well edge 23 to extend. Layer 15, from the sidewall of grid ditch 12, covers the surface 11 certain distance x of semiconductor body 10, for example, in the scope of 50nm-150nm.
As shown in the example about Fig. 4, in semiconductor devices, can in semiconductor body 10, form groove 30. In this case, the mode that groove 30 has to start from the edge 22 of layer 15 extends to the trenched side-wall 42 semiconductor body 10. Can in groove 30, arrange the public connecting electrode for source region 39 and passage area 38.
The exemplary embodiments that is depicted as the semiconductor devices of the selections in Fig. 4 is MOS field-effect transistor, and it for providing the application of approximately 20 volts of voltages to hundreds of volt between source electrode and drain electrode.
Can produce layer 15 by said method, and this layer is as the mask layer that produces contact hole groove 30. This autoregistration layer 15 makes contact hole groove 30 can have the interval very little from gate groove 12. As a result, may reduce significantly spacing, that is to say compared to distance before, with the distance between two gate grooves 12 of parallel arrangement. As an example, above-mentioned solution has been shown the spacing of about 950nm, and it is caused by such fact, and the contact hole connecting for source/passage area must be contained between two gate grooves. Due to self-aligned mask layer 15, spacing for example can be contracted to 750nm. Therefore, the passage of MOSFET also can be designed shorter, because field can not penetrate passage area so far forth. In addition, can in the transistorized existing method for generation of gate groove, implement the put forward the methods step for generation of this structural detail, and not need large extraneous expense.
Can use self-registered technology hereinafter described further to reduce or optimize the distance between adjacent unit. About Fig. 5 A-Fig. 5 C, this self-registered technology is described.
In Fig. 5 A, it illustrates that the several procedure of processings of executed are to form the semiconductor body 100 after autoregistration mesa structure 102, all types as described above. Groove 104 extends to semiconductor body 100 from the first first type surface 106 of main body 100. Then, carry out HDP deposition step (for example describing before) herein, thereby on semiconductor body 100, form HDP layer 108 and filling groove 104. Then, deposit carbon or any other suitable material 110, thus fill the HDP profile with the well corresponding with the shape of groove 104 or recessed region. For example, use dark etching (etchback) and/or CMP technique to remove too much packing material 110, and stop on HDP material 108. Then, in the HDP material 108 between adjacent trenches 104, form opening 112, thereby produce autoregistration HDP mesa structure 102.
Depend on the etch process of use, the sidewall 114 of HDP mesa structure 102 can be convergent or non-convergent. Distance d1 between adjacent HDP mesa structure 102 determines the interval between neighboring devices unit. Described device unit is partly formed in groove 104, for example, grid and gate-dielectric can form (for example above with reference to described in figure 4) in groove 104, and can between adjacent trenches 104, in Dao district 116, form at semiconductor body 100 main body and the source region of described device. Processing semiconductor main body island district 116 subsequently, to form described device.
This processing is included in and in semiconductor island district 116, forms contact openings 122, and by dopant implant thing in contact openings 122Dao district 116. For example, in order to suppress Implantation in contact openings 122 and the interaction of the liner oxide of injection zone (main body) or trenched side-wall 118, enough large (for example, about 50-100nm) of minimum range d2 between the sidewall 118 of contact openings 122 and adjacent trenches 104. Otherwise electrical quantity can change and worsen device quality. On the other hand, for fear of high resistance or filling problem (space), contact openings 122 should be not too narrow, for example < 70nm.
Fig. 5 B is illustrated in and carries out TEOS(tetraethyl orthosilicate) or carbon depositing operation to form the semiconductor body 100 after TEOS/ carbon spacer layers 120 on semiconductor body 100 and HDP mesa structure 102. The thickness of this TEOS/ carbon spacer layers 120 has been determined the width w of the contact openings 122 in the semiconductor body 100Dao district 116 between adjacent trenches 104, and distance d2 between contact openings 122 and the sidewall 118 of adjacent trenches 104.
Regardless of the actual range d1 between adjacent table top 102, all can pre-determine the thickness of TEOS/ carbon spacer layers 120. In one embodiment, the concrete hypothesis of the width w based on to contact openings 122, for example, suppose wide contact openings, selects the thickness of TEOS/ carbon spacer layers 120. In another embodiment, the measuring distance based between adjacent HDP mesa structure 102 is determined the thickness of TEOS/ carbon spacer layers 120.
For example, can use SEM(scanning electron microscopy) or any other suitable electron microscope technique measure the distance between adjacent HDP table top 102. On can the several points on wafer, (for example, center, edge etc.) carries out this measurement, to solve the variation on wafer. Can be by the mean value of measured value and for the desired value comparison of the distance between adjacent HDP mesa structure 102. Conventionally, (through measuring) mean value is greater than desired value. This difference has represented after meeting desired value processes the required thickness of TEOS/ carbon spacer layers 120. In order to realize higher uniformity, can consider the typical homogeneity of HDP deposition, etching and TEOS/ carbon deposition.
Can in closed loop environment, carry out TEOS/ carbon depositing operation. Pinpoint accuracy control to layer thickness is provided like this, thereby in semiconductor body island district 116, produces highly accurate contact openings width w, and produce highly accurately apart from d2 between contact openings 122 and the sidewall 118 of adjacent trenches 104. In the time that the accurate control of these key parameters is provided, can optimize the interval between unit. Also can during TEOS/ carbon-coating depositing operation, use variable time, control to realize even more accurately.
Fig. 5 C is illustrated in the semiconductor body 100 forming in semiconductor body 100Dao district 116 after contact openings 122. As mentioned above, the thickness based on TEOS/ carbon spacer layers 120 is determined the distance d2 between width w and each contact openings 122 and the sidewall 118 of adjacent trenches 104 of contact openings 122. Remove the base section of the TEOS/ carbon spacer layers 120 arranging on the first first type surface 106 of semiconductor body 100, to can form contact openings 122 in Dao district 116. Use anisotropic etching process, to form the contact openings 122 with desired width w and trench sidewall spacer d2. Can remove alternatively TEOS/ carbon spacer layers 120. Form source region (and body region, if before inchoate words) by Implantation. For this target, by contact openings 122, the alloy of suitable electric conductivity is injected to semiconductor body island district 116. Then, fill contact openings 122 with conductive material, thereby provide and electrically contact to source electrode and body region. For ease of illustrating, not shown source electrode, main body and corresponding contact site in Fig. 5 A-Fig. 5 C.
Self-registered technology embodiment shown in Fig. 5 A-Fig. 5 C can be used to relatively undersized technology, the technology of for example spacing～400-1500nm and mesa width～100-1000nm. These sizes depend on the concrete semiconductor technology of use certainly. More large scale of this utilization if injecting, contact site uses very high energy, even if also can be avoided the horizontal discrete impact on electrical property by this program of narrowing.
Fig. 6 A-Fig. 6 H is illustrated in the sectional view of semiconductor body 200 during the different step of the method that is used to form self-aligned contact structure. Fig. 6 A illustrates the semiconductor body 200 after groove 202 is etched in main body 200, field oxide 204 forms along sidewall 203 and the bottom 205 of groove 202, groove 202 is filled conductive material, such as polysilicon, and dark this conductive material of etching to form field plate 206 in the part of the bottom of groove 202. In the drawings, field plate 206 is indicated ' S ', this field plate 206 can be connected to source potential to indicate.
Fig. 6 B illustrates the semiconductor body 200 after the HF technique of the top part removal field oxide 204 of groove 202. Field oxide 204 remains in the bottom part of groove 202, so that by field plate 206 and semi-conducting material insulation around. Can carry out optional source electrode at this some place and main body injects to form source electrode and body region, for example pass through following steps: with resist filling groove 202, resist is etched to deeply to the first type surface 201 of semiconductor body 200, and the alloy of suitable electric conductivity is injected to semiconductor body 200. Otherwise, can more late or more early form source electrode and/or body region.
Fig. 6 C illustrates and for example deposits by such HDP of execution mentioned above to form HDP layer 208 semiconductor body 200 afterwards on semiconductor body 200 and in groove 202. Field plate 206 is recessed dearly in groove 202, to can form grid conductor (as shown in Fig. 6 E) in the groove 202 on field plate 206 subsequently. This is deeply recessed produces such HDP profile, and this profile is more clear and allow wider process window, and allows the more high tolerance (as shown in Fig. 6 E) of process deviation (such as groove etching subsequently) subsequently.
Fig. 6 D illustrates that deposit carbon ' C ' is to fill HDP profile semiconductor body 200 afterwards, and this HDP profile has well or the recessed region corresponding to the shape of groove 202 and the recessed degree of depth of field plate 206. For example use dark etching and/or CMP technique to remove too much carbon, and stop on HDP material, to form carbon plug 210 in well or in the recessed region of HDP layer 208.
Fig. 6 E is illustrated in the semiconductor body 200 forming in the semiconductor body 200Dao district 214 between groove 202 after groove 212. Use anisotropic etching process, to remove the HDP material of selecting for material with carbon element, thereby cause autoregistration and interval to separate HDP/ carbon structure 216. Autoregistration HDP/ carbon structure 21
6 separate with open gap ' g ' each interval each other, and can have convergent or non-convergent sidewall 218 according to the etch process using. As above with reference to as described in figure 5B, for the open gap ' g ' further narrowing between HDP/ carbon structure 216, can be before etching HDP layer 208, on semiconductor body 200 and HDP/ carbon structure 216, deposit optional spacer layers (not shown in Fig. 6 E). For wider unit, on the HDP layer 208 in can edge region, form resist layer 220, to prevent from removing the HDP layer 208 in fringe region. Then,, by the open gap ' g ' between adjacent HDP/ carbon structure 216, between groove 202, groove 212 is etched in semiconductor body island district 214. Alternatively, can after etched recesses 212 and before filling groove 212, complete source/body and contact site injection.
Fig. 6 F illustrates to have nitride or other materials 222 filling grooves 212 semiconductor body 200 afterwards of the etching selectivity different with material with carbon element 210 from HDP material 208. Use dark etching and/or CMP technique to remove too much groove packing material 222, and stop on material with carbon element 210.
Fig. 6 G illustrates for example semiconductor body 200 after groove 202 is removed the autoregistration HDP/ carbon structure 216 of selecting for groove packing material 222 by O2 plasma etching. Also can for example pass through wet chemical etching (HF) and remove any residue HDP residue 223 on the sidewall of groove packing material 222, and form gate oxide 224 along trenched side-wall 203 in the part of the top of groove 202. Field oxide 204 and field plate 206 remain in the bottom part of groove 202. After removing HDP/ carbon structure 216, groove packing material 222 is also residual.
Fig. 6 H is illustrated in groove 202 and on semiconductor body 200 and deposits grid conductor material 226(such as polysilicon) semiconductor body 200(is afterwards shown in dotted line). Use dark etching and/or CMP technique to remove multiple-grid conductor material, thereby produce grid conductor 228 in groove 202. Grid conductor 228 is arranged on the field plate 206 in groove 202, and is separated and separate by gate oxide 224 and semiconductor body 200 lateral separations in interval vertically by field oxide 204 and field plate 206. Can carry out traditional procedure of processing subsequently, such as depositing insulation oxide (as BPSG, CMP) or dark etching plug table top, removal plug, filling metal, source/body injection, contact injection etc. As mentioned above, can remove subsequently groove packing material 222, to form source electrode and/or body region and corresponding contact structures in semiconductor body 200.
Use such as " ... under ", " under ", " bottom ", " ... on ", the space relative terms on " top " etc. is with simplified illustration, thereby explain that an elements relative is in the location of the second element. Except those different orientations to that indicated in the drawings, these terms are also intended to the difference orientation that comprises device. In addition, also use such as the term of " first ", " second " etc. to describe various elements, region, part etc., and not also to be intended to be restrictive. In whole explanation, identical term all represents similar elements.
Term used herein " has ", " comprising ", " comprising ", " by ... composition " etc. be open-ended term, and it represents to exist described element or feature, does not still get rid of other element or feature. Unless explicitly point out in addition in literary composition, otherwise article " ", " one " and " being somebody's turn to do " are intended to comprise plural number and odd number.
Should be understood that unless otherwise expressly stated, the feature of various embodiment as herein described can combination with one another.
Although illustrated and described specific embodiment herein, it will be understood by those skilled in the art that in the situation that not departing from scope of the present invention, shown in can replacing with multiple replaceable and/or equivalent enforcement and described specific embodiment. This application is intended to contain any amendment or the modification of specific embodiment discussed in this article. Therefore, the present invention is intended to only be limited by claim and equivalent thereof.

Claims (19)

1. produce a method for the contact openings in semiconductor body, described method comprises:
On the first type surface of semiconductor body, form multiple self-alignment structures, each autoregistration knotStructure is all filled in the groove forming in described semiconductor body and prolongs above described first type surfaceStretch and extend on described first type surface, the adjacent self-alignment structure tool in described self-alignment structureThere is the isolated sidewall facing with each other;
On the sidewall of described self-alignment structure, form spacer layers; And
When described spacer layers is positioned on the described sidewall of described self-alignment structure,Between adjacent self-alignment structure in described self-alignment structure, shape in described semiconductor bodyBecome opening, so that each opening all has a width and has to one of the sidewall of adjacent trenchesDistance, it is corresponding with the thickness of described spacer layers, wherein, at described semiconductor bodyOn described first type surface, forming described self-alignment structure comprises:
Form and extend to described semiconductor body from the described first type surface of described semiconductor bodyIn multiple grooves;
On described first type surface and in described groove, form ground floor, described ground floor existsOn described groove, have recessed region, wherein said recessed region has recessed region base portionAnd at least one recessed region side walls, the female region side walls is with respect to described semiconductorThe angle [alpha] of the described first type surface of main body within the scope of forming 20 ° to 80 °, the female area sideWall is on the edge of the sidewall of described groove, and in the restriction of the first type surface of semiconductor bodyExtend apart from x is upper, described restriction apart from x between 50nm and 150nm;
On described ground floor, form the second layer, the described second layer is filled the recessed of described ground floorEnter region; And
In described first and second layers, form opening, described opening is at described semiconductor bodyThe adjacent trenches in described groove between extend to described first type surface on Dao district.
2. method according to claim 1, wherein, described ground floor deposits formation by HDP.
3. method according to claim 1, wherein, the described second layer comprises carbon.
4. method according to claim 1, wherein, described spacer layers deposits by TEOSForm.
5. method according to claim 1, wherein, described spacer layers comprises carbon.
6. method according to claim 1, wherein, the described sidewall of described self-alignment structure graduallyContracting.
7. method according to claim 1, the further phase based in described self-alignment structureThe preset width of the opening forming in described semiconductor body between adjacent self-alignment structure comes reallyThe thickness of fixed described spacer layers.
8. method according to claim 1, also comprises:
Before forming described spacer layers, measure adjacent autoregistration in described self-alignment structureDistance between structure; And
Distance based on measured is determined the thickness of described spacer layers.
9. method according to claim 8, wherein, surveys by SEM methodMeasure the distance between the adjacent self-alignment structure in described self-alignment structure.
10. method according to claim 8, wherein, described semiconductor body is semiconductor waferPart, and forming before described spacer layers the difference place on described waferMeasure the multiple distances between adjacent self-alignment structure.
11. methods according to claim 10, also comprise:
Calculate the mean value of the measured value of described multiple distances; And
Mean value based on calculated is determined the thickness of described spacer layers.
12. methods according to claim 11, wherein, the thickness of described spacer layers and described fromInstitute's calculating mean value and the desired value of the distance between the adjacent self-alignment structure in align structuresBetween difference corresponding.
13. 1 kinds produce the method for the self-aligned contact structure on semiconductor body, and described method comprises:
Form from the first type surface of semiconductor body and extend to multiple described semiconductor bodyGroove;
In the part of the bottom of described groove, form the conduction with described semiconductor body insulationPlate;
On described conductive plate on described first type surface and in described groove, form firstMaterial, described the first material has the recessed region above described groove, wherein said recessedEnter region and there is recessed region base portion and at least one recessed region side walls, the female districtTerritory sidewall is within the scope of forming 20 ° to 80 ° with respect to the described first type surface of described semiconductor bodyAngle [alpha], the female region side walls is on the edge of the sidewall of described groove, and halfThe restriction of the first type surface of conductor main body is apart from the upper extension of x, described restriction apart from x at 50nmAnd between 150nm;
Fill the female region of described the first material with the second material;
In described the first material, form opening, described opening is located described semiconductor bodyBetween adjacent trenches in described groove, top, Dao district extends to described first type surface, therebyForm the self-alignment structure that multiple intervals separate, described self-alignment structure is included in described firstDescribed the second material in the female region of material;
Between adjacent self-alignment structure in described self-alignment structure described semiconductor masterIn body, form groove; And
To there is the etching selectivity different with described the second material from described the first materialMaterial is filled opening between the adjacent self-alignment structure in described groove and described self-alignment structureStandard width of a room in an old-style house gap.
14. methods according to claim 13, wherein, described the first material deposits shape by HDPBecome.
15. methods according to claim 13, wherein, described the second material comprises carbon.
16. methods according to claim 13, also comprise for filling described groove and described opening wideThe material in gap and optionally remove described self-alignment structure.
17. methods according to claim 16, are also included in the top part of described groove and formGrid conductor, described grid conductor and described semiconductor body and the insulation of described field plate.
18. methods according to claim 16, described in being also included in described semiconductor body and formingBefore groove, on the sidewall of described self-alignment structure, form spacer layers, and wherein,In on described sidewall in described spacer layers in described self-alignment structure, byIn described semiconductor body, between the adjacent self-alignment structure of described self-alignment structure, form and openMouthful in described semiconductor body, form described groove, one wide so that each opening all hasSpend and have the distance to adjacent trenches, it is corresponding with the thickness of described distance piece.
19. methods according to claim 13, wherein, fill described groove and described open gapDescribed material comprise nitride.
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