CN103578993B - The forming method of a kind of semiconducter device - Google Patents
The forming method of a kind of semiconducter device Download PDFInfo
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- CN103578993B CN103578993B CN201210261932.2A CN201210261932A CN103578993B CN 103578993 B CN103578993 B CN 103578993B CN 201210261932 A CN201210261932 A CN 201210261932A CN 103578993 B CN103578993 B CN 103578993B
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 64
- 239000011229 interlayer Substances 0.000 claims description 11
- 150000001875 compounds Chemical class 0.000 claims description 10
- 238000002347 injection Methods 0.000 claims description 10
- 239000007924 injection Substances 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 9
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 2
- 229910052582 BN Inorganic materials 0.000 claims 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 3
- 229910052799 carbon Inorganic materials 0.000 claims 3
- 150000002500 ions Chemical class 0.000 description 19
- 230000000694 effects Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28105—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
Abstract
The present invention provides the forming method of a kind of semiconducter device, comprising: provide semiconducter substrate; Substrate is formed gate dielectric, polysilicon layer and hard mask layer successively; Patterned hard mask layer; The sidewall of the hard mask layer at patterning forms the first clearance wall; Taking hard mask layer and the first clearance wall as mask etch polysilicon layer and gate dielectric, form grid structure; The sidewall of grid mechanism is formed the 2nd clearance wall; Remove hard mask layer or the first clearance wall; As mask, polysilicon layer is performed work function adjustment ion implantation taking the first clearance wall or hard mask layer, form the grid electrode of the work function with transverse variable; Perform the step forming source electrode and drain electrode. Formed the semiconducter device of the grid of the work function with symmetrical or asymmetric transverse variable by mask in selected region, solve the problem of the insufficient automatically controlled level of the gate electrode on channel region.
Description
Technical field
The present invention relates to a kind of technical field of manufacturing semiconductors, more precisely, the present invention relates to the forming method of the semi-conductor that can comprise metal oxide semiconductor field effect transistor (MOSFET) (MOSFET) device.
Background technology
Along with the reduction of the dimensions of semiconductor devices comprising MOSFET element, especially along with the reduction of MOSFET gate electrode size, the new effects such as short-channel effect are more outstanding in MOSFET element, insufficient automatically controlled level of the gate electrode that short-channel effect comes from MOSFET on channel region, harmful short-channel effect can cause MOSFET off-state current big in MOSFET, high standby power dissipation and the change of harmful electrical parameter. Also having some trials to solve the problem in prior art, such as, make MOSFET element to have and do not adulterate and very thin body region, it comprises and not adulterating and very thin channel region; But other electrical parameter can be caused infringement by such structure. So the forming method needing a kind of semiconducter device overcomes the above problems.
Summary of the invention
In view of above problem, the present invention provides the forming method of a kind of semi-conductor, comprises the following steps: a) provide semiconducter substrate; B) gate dielectric, polysilicon layer and hard mask layer is formed over the substrate successively; C) hard mask layer described in patterning; D) sidewall of hard mask layer at described patterning forms the first clearance wall; E) taking described hard mask layer and described first clearance wall as polysilicon layer described in mask etch and described gate dielectric, grid structure is formed; F) on the sidewall of described grid structure, the 2nd clearance wall is formed; G) described hard mask layer or described first clearance wall is removed; H) as mask, described polysilicon layer is performed work function adjustment ion implantation taking described first clearance wall or described hard mask layer, form the grid electrode of the work function with transverse variable; I) step of source electrode and drain electrode is performed to be formed.
Further, described step h also it is included in) remove the step of described first clearance wall or described hard mask layer afterwards.
Further, wherein said 2nd clearance wall higher than, short in or equal described polysilicon layer.
Further, be also included in described 2nd clearance wall formed after form interlayer dielectric layer on described substrate.
Further, described step h also it is included in) remove described interlayer dielectric layer afterwards.
Further, also comprise and described interlayer dielectric layer is carried out CMP and etch-back to expose the step of described first clearance wall.
Further, wherein use oxide compound, nitride, oxynitride, A-C, BN or its be combined to form described hard mask layer.
Further, wherein use oxide compound, nitride, oxynitride, A-C, BN or its be combined to form described first clearance wall.
Further, wherein use oxide compound, nitride, oxynitride, A-C, BN or its be combined to form described 2nd clearance wall.
Further, wherein step c) described in the hard mask layer that formed there is the thickness being greater than 100 dusts.
Further, III-th family or V group element ion is wherein used to adjust ion as described work function.
Further, the implantation dosage of wherein said work function adjustment ion is 10E10-10E20 ion/cm2.
Further, also it is included in step e) after, the sidewall of described grid structure is formed offset side wall and carries out the step of LDD injection.
Further, wherein said semiconducter device is MOSFET.
Further, wherein step g) in the removal of the first clearance wall only the first clearance wall of side is performed.
Further, wherein said grid electrode has transverse variable and asymmetric work function.
Further, wherein step g) in the removal of the first clearance wall whole first clearance wall is performed.
Further, wherein grid electrode has the work function of transverse variable and symmetry.
Owing to have employed the forming method of the semiconducter device of the present invention, the grid electrode of (it can the be symmetrical or asymmetric) work function with transverse variable can be formed, and can control to make the work function of work function higher or lower than the mid-way of grid in the region, edge of grid. Namely the semiconducter device of the grid of the work function with transverse variable easily can be formed on selected region by the mask of the present invention. Due to the problem of the insufficient automatically controlled level of gate electrode solved in prior art on channel region, the method for the present invention can effectively improve the performance of semiconducter device.
Accompanying drawing explanation
Fig. 1-10 is the device profile map of each processing step of the present invention.
Embodiment
In the following description, details concrete in a large number is given to provide more thorough understanding of the invention. But, to those skilled in the art it is apparent that the present invention can be implemented without the need to these details one or more. In other example, in order to avoid obscuring with the present invention, technology features more well known in the art are not described.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to explain the forming method that the present invention proposes semiconducter device. Obviously, the execution of the present invention is not limited to the specific details that the technician of semiconductor applications has the knack of. The better embodiment of the present invention is described in detail as follows, but except these describe in detail, the present invention can also have other enforcement modes.
Should be understood that, when using term " comprising " and/or " comprising " in this manual, it indicates exists described feature, entirety, step, operation, element and/or assembly, but do not get rid of and there is or add other features one or more, entirety, step, operation, element, assembly and/or their combination next, will more intactly describe the present invention by reference to the accompanying drawings.
See Fig. 1. Semiconducter substrate 200 is provided. Described substrate can be at least one in following mentioned material: stacking germanium SiClx (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. on stacking silicon (SSOI), isolator on silicon, silicon-on-insulator (SOI), isolator. Can being formed with doped region and/or isolation structure in described substrate, described isolation structure is that shallow trench isolation isolates structure from (STI) structure or selective oxidation silicon (LOCOS), not shown. In an embodiment of the present invention, described substrate can be Si substrate.
Then forming gate dielectric layer 201 thereon, described gate dielectric layer is the SiO2 gate dielectric layer formed by rapid thermal oxidation process (RTO) or atom layer deposition process (ALD).
Then on described gate dielectric layer 201, polysilicon layer 202 is formed. Forming method comprises chemical Vapor deposition process (CVD) etc.
Then hard mask layer 203 is formed on the polysilicon layer. It can use oxide compound, nitride, oxynitride, A-C, BN or its combination to be formed. Forming method can be low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD), it is possible to use such as spatters the general similarity method such as plating and physical vapor deposition (PVD).
Then firmly mask patterning step is carried out. Photoetching process can be used to perform this step. The hard mask layer that this step stays after carrying out has the thickness being greater than 100 dusts. See Fig. 2.
See Fig. 3. Then on hard mask layer sidewall, the first clearance wall 210 is formed, it is possible to use oxide compound, nitride, oxynitride, A-C, BN or its method being combined through deposition and etching are to form this clearance wall.
See Fig. 4. Taking hard mask layer and the first clearance wall as mask etch polysilicon layer and gate dielectric, form grid structure, namely the polysilicon layer 202 exposed and the gate dielectric layer 201 below it are performed the step that etching is removed, such as, uses the methods such as dry etching or wet corrosion quarter. Area of grid at substrate forms institute's polysilicon layer and gate dielectric layer 201 is positioned at below hard mask layer 203 and the first clearance wall 210 to form grid structure.
See Fig. 5. Can also carry out being formed the step of offset side wall (offsetspacer) 211, not shown. The material of offset side wall can be silicon nitride, the insulating material such as silicon oxide or silicon oxynitride. Offset side wall can improve the channel length of the transistor of formation, the hot carrier's effect reducing short-channel effect and causing due to short-channel effect. The technique forming offset side wall can be chemical vapour deposition.
Then the step of light dope source/drain (LDD) in the substrate of grid structure can also be carried out being formed, not shown. The method of described formation LDD can be ion implantation technology or diffusion technique. The ionic type that described LDD injects is according to the electrical decision of the semiconducter device that will be formed, and the device namely formed is nmos device, then the foreign ion mixed in LDD injection technology is the one in phosphorus, arsenic, antimony, bismuth or combination; If the device formed is PMOS device, then the foreign ion injected is boron. Concentration according to required foreign ion, ion implantation technology can a step or multistep complete.
Then form the 2nd clearance wall 220 on the sidewall of substrate 200 and polysilicon layer 202, the height of this clearance wall can lower than, greater than or equal to polysilicon layer. The material that can use comprises: oxide compound, nitride, oxynitride, A-C, BN or its combination. The method formed comprises deposition and etching.
With reference to Fig. 6. Then interlayer dielectric layer (ILD) 400 is deposited on substrate. The interlayer dielectric layer of silicon oxide having doping or not adulterating that can adopt that thermal chemical vapor deposition (thermalCVD) manufacturing process or high density plasma (HDP) manufacturing process formed, the silex glass (USG) of such as undoped, phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG). In addition, interlayer dielectric layer can also be the tetraethoxysilane (BTEOS) of spin cloth of coating-type glass (spin-on-glass, SOG) of doped with boron or Doping Phosphorus, the tetraethoxysilane (PTEOS) of Doping Phosphorus or doped with boron.
Then interlayer dielectric layer 220 is carried out planarization and returns etching processing. The limiting examples of described planarization comprises mechanical planarization method and chemically machinery polished flattening method (CMP).
Sulfur fluoride (SF6), nitrogen and chlorine can be used to carry out back etching as etching reagent and selective reaction ion etching (RIE) technique that oxide compound has highly selective. Such that it is able to expose the first clearance wall 210.
See Fig. 7. Then carry out removing the step of the first clearance wall 210, only leave hard mask layer 203 on polysilicon layer 202. It will adjust the mask layer of the injection of ion as work function.
Then the step of the injection of work function adjustment ion is carried out. Concrete, the direction being namely perpendicular to substrate by the direction shown in figure is injected. The doping agent that can use comprises any one in III-th family or V race dopant species. Work function adjustment ion can be provided by the dosage of 10E10-10E20 ion/cm2. The grid electrode formed has the work function of transverse variable and symmetry.
In the embodiment that the present invention is other, in the step removing the first clearance wall 210, it is possible to use the clearance wall of side is only performed removal by light cover, as shown in Figure 8. Then the step of the injection of work function adjustment ion is carried out using the clearance wall of another left side and hard mask layer as the mask layer of the injection of work function adjustment ion. Concrete, the direction being namely perpendicular to substrate by the direction shown in Fig. 9 is injected. The doping agent that can use comprises any one in III-th family or V race dopant species. Work function adjustment ion can be provided by the dosage of 10E10-10E20 ion/cm2. The grid electrode formed has transverse variable and asymmetric work function.
See Fig. 9. In the other embodiment of the present invention, do not perform the step that the first clearance wall is removed, but carry out the removal of hard mask layer 203, leave the first clearance wall and will adjust the mask layer of the injection of ion as work function. Then the step of the injection of work function adjustment ion is carried out. Namely this ion implantation will be perpendicular to the direction injection of substrate by the direction shown in figure. The doping agent that can use comprises any one in III-th family or V race dopant species. Work function adjustment ion can be provided by the dosage of 10E10-10E20 ion/cm2.
The semiconducter device formed so just has the work function of transverse variable. And can control to make the work function of work function higher or lower than the mid-way of grid in the region, edge of grid. Namely the semiconducter device of the grid of the work function (it can be symmetrical or asymmetric) with transverse variable easily can be formed on selected region by the mask of the present invention.
Then with reference to Figure 10. Carry out removing the step of the first clearance wall and/or hard mask layer and the interlayer dielectric layer stayed after above step performs, it is possible to use method comprise wet etching erosion or dry etching. Hydrofluoric acid solution can be adopted, such as buffer oxide etch agent (BOE) or hydrofluoric acid buffered soln (BHF). Can also be reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting etc. An embodiment carries out dry etching by one or more RIE step.
Then the step of source and drain pole (S/D) is carried out being formed, not shown.
Then subsequent technique can also be carried out to complete the manufacture of semiconductor element.
In order to the purpose of illustration and description, give the above description of all respects of the present invention. It is not intended to exclusive list or limits the invention to disclosed precise forms, and it will be apparent that can carry out numerous modifications and variations. The present invention is intended to it will be apparent to those skilled in the art that in the scope that these modifications and variations are included in the present invention being defined by the following claims.
Claims (17)
1. a forming method for semiconducter device, comprises step:
A) semiconducter substrate is provided;
B) gate dielectric, polysilicon layer and hard mask layer is formed over the substrate successively;
C) hard mask layer described in patterning;
D) sidewall of hard mask layer at described patterning forms the first clearance wall;
E) taking described hard mask layer and described first clearance wall as polysilicon layer described in mask etch and described gate dielectric, grid structure is formed;
F) on the sidewall of described grid structure, form the 2nd clearance wall, and form interlayer dielectric layer on described substrate after described 2nd clearance wall is formed;
G) described hard mask layer or described first clearance wall is removed;
H) as mask, described polysilicon layer is performed work function adjustment ion implantation taking described first clearance wall or described hard mask layer, form the grid electrode of the work function with transverse variable;
I) step of source electrode and drain electrode is performed to be formed.
2. method according to claim 1, is also included in described step h) remove the step of described first clearance wall or described hard mask layer afterwards.
3. method according to claim 1, wherein said 2nd clearance wall higher than, short in or equal described polysilicon layer.
4. method according to claim 1, is also included in described step h) remove described interlayer dielectric layer afterwards.
5. method according to claim 1, also comprises and described interlayer dielectric layer carries out CMP and etch-back to expose the step of described first clearance wall.
6. method according to claim 1, wherein use oxide compound, nitride, oxynitride, decolorizing carbon, boron nitride or its be combined to form described hard mask layer.
7. method according to claim 1, wherein use oxide compound, nitride, oxynitride, decolorizing carbon, boron nitride or its be combined to form described first clearance wall.
8. method according to claim 1, wherein use oxide compound, nitride, oxynitride, decolorizing carbon, boron nitride or its be combined to form described 2nd clearance wall.
9. method according to claim 1, wherein step c) described in formed hard mask layer there is the thickness being greater than 100 dusts.
10. method according to claim 1, wherein uses III-th family or V group element ion to adjust ion as described work function.
11. methods according to claim 1, the implantation dosage of wherein said work function adjustment ion is 10E10-10E20 ion/cm2��
12. methods according to claim 1, are also included in step e) after, the sidewall of described grid structure is formed offset side wall and carries out the step of LDD injection.
13. methods according to claim 1, wherein said semiconducter device is MOSFET.
14. method according to claim 1, wherein step g) in the first clearance wall removal only to side first clearance wall perform.
15. methods according to claim 14, wherein said grid electrode has transverse variable and asymmetric work function.
16. method according to claim 1, wherein step g) in the first clearance wall removal to whole first clearance wall perform.
17. methods according to claim 16, wherein grid electrode has the work function of transverse variable and symmetry.
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| CN102184961A (en) * | 2011-04-26 | 2011-09-14 | 复旦大学 | Asymmetrical gate metal oxide semiconductor (MOS) device and manufacturing method thereof |
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