CN103576168B - A kind of Big Dipper satellite signal simulator and its implementation - Google Patents
A kind of Big Dipper satellite signal simulator and its implementation Download PDFInfo
- Publication number
- CN103576168B CN103576168B CN201210280519.0A CN201210280519A CN103576168B CN 103576168 B CN103576168 B CN 103576168B CN 201210280519 A CN201210280519 A CN 201210280519A CN 103576168 B CN103576168 B CN 103576168B
- Authority
- CN
- China
- Prior art keywords
- module
- signal
- big dipper
- dipper satellite
- chip microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/23—Testing, monitoring, correcting or calibrating of receiver elements
Abstract
The present invention discloses a kind of Big Dipper satellite signal simulator and its implementation, is mainly made up of power module, clock module, LCD MODULE, single-chip microcomputer, FPGA processing module, D/A converter module, up-converter module and signal attenuation module. Power module part completes 5V and the 3.3V power supply of general 220V alternating current to modules such as single-chip microcomputer, FPGA, up-conversions; Clock provides the clock frequency of standard mainly to single-chip microcomputer, FPGA, up-conversion; Single-chip microcomputer mainly carries out the demonstration control of 12864 liquid crystal displays, the control of FPGA, the power control of up-converter module; FPGA mainly carries out the generation of gps signal, the GPS data signal of output Low Medium Frequency; The data signal that D/A module completes FPGA is converted to the analog signal of Low Medium Frequency; The GPS analog signal of Low Medium Frequency is converted to the nominal radiofrequency signal consistent with outdoor gps satellite by up-converter module. It can simulate the present invention Big Dipper satellite signal, and has feature easy to carry and simple to operate.
Description
Technical field
The present invention relates to Beidou satellite navigation and field tests, be specifically related to a kind of Big Dipper satellite signal simulationDevice and its implementation.
Background technology
Beidou satellite navigation system (Compass) is China's global positioning satellite and communication system of development voluntarilySystem (GNSS), the global positioning system (GPS) of the Shi Ji U.S. and Muscovite GLONASS afterwards the 3rdThe satellite navigation system of individual maturation. System is made up of vacant terminal, ground surface end and user side three parts, can beRound-the-clock in global range, round-the-clock for all types of user provide high accuracy, highly reliable location, navigation,Time service service, and have short message communication capacity concurrently. End in May, 2,012 12 of satellite in orbit,Tentatively possess area navigation, location and time service ability. Beidou satellite navigation system will form at the year two thousand twenty entirelyBall covering power. Because big-dipper satellite is still in construction, if therefore will produce Beidou receiver,Test and technical research, measure receiver to satellite signal receiving and positioning performance, or Beidou receiverThe application scenarios such as the location availability under the complex environments such as missile-borne, need first to develop Big Dipper simulationDevice is simulated all satellite navigation signals that produce dipper system, is development, the survey of Beidou receiverExamination provides simulated environment. But, in view of Beidou satellite navigation system has just started to carry to China and surrounding areaFor continuous navigator fix and time service service, Beidou satellite navigation signal simulator research field is open abroadThe technical literature of delivering is little.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of Big Dipper satellite signal simulator and realization side thereofMethod, it can be simulated Big Dipper satellite signal, and has feature easy to carry and simple to operate.
For addressing the above problem, the present invention is achieved by the following scheme:
A kind of Big Dipper satellite signal simulator of the present invention, comprises simulator, and described simulator is mainly by power supplyModule, clock module, LCD MODULE, single-chip microcomputer, FPGA processing module, D/A converter module,Up-converter module and signal attenuation module composition; Wherein,
Power module: having required power supply according to the power output of simulator and the inner each module of simulatorBecome supply voltage conversion, for the each module in simulator inside provides linear stabilized power supply;
Clock module: provide stable clock to single-chip microcomputer, realize the control to whole simulator; SimultaneouslyWork reference clock is provided and obtains corresponding stable system break by phaselocked loop to FPGA processing moduleSignal and Channel Synchronous pulse, drive the work of the baseband board in FPGA processing module; Realize mould simultaneouslyThe active configuration of number conversion module; The local oscillator clock of required standard is provided to up-converter module simultaneously;
Single-chip microcomputer: be first connected with outer PC by serial ports, receive serial ports send defend asterisk setting andPower setting order, so control FPGA processing module produce the C/A code of respective satellite and navigation message withAnd control signal attenuation module; Then the asterisk of defending receiving is sent to FPGA processing module, realize singleThe control of sheet machine to FPGA processing module; The running parameter of control simulation device is on LCD MODULE simultaneouslyShow;
FPGA processing module: that first sends according to single-chip microcomputer defends asterisk, generates phase by the method for tabling look-upShould defend the navigation message of asterisk; Then under the control of symbol phases and code frequency word, produce corresponding code phasePosition and the spreading code of bit rate, generate the C/A code of corresponding Big Dipper satellite signal, to produced leadingAvionics literary composition numeric data code carries out DSSS; Last according to set IF carrier, in carrier phaseUnder the control of carrier frequency register, produce the digital sine range value of required frequency and phase place, withBand spectrum modulation code multiplies each other, and completes the BPSK(two-phase PSK to carrier wave) modulation, by the data of modulationStream signal, through formed filter, then, by output after each passage digital intermediate frequency Big Dipper signal stack, is sent intoTo D/A converter module;
D/A converter module: the modulated digital intermediate frequency Big Dipper satellite signal from FPGA processing moduleBe converted to simulation Big Dipper satellite signal, after by analog bandpass filtering device, export to up-converter module;
Up-converter module: receive the simulation Big Dipper satellite signal after D/A converter module conversion, by Low Medium FrequencySimulation Big Dipper satellite signal through up-conversion, be converted to the nominal consistent with outdoor Big Dipper satellite signal and penetrateFrequently signal, sends into signal attenuation module;
Signal attenuation module; This signal attenuation module is serially connected in up-converter module and Big Dipper satellite signal outputBetween mouthful; The watt level of the radiofrequency signal of up-converter module output is fed back to monolithic by signal attenuation moduleMachine, single-chip microcomputer is according to the output power signal size of setting, and control signal attenuation module is to up-converter moduleThe radiofrequency signal of output decays, to adjust the emission of radio frequency signals of Big Dipper satellite signal delivery outlet outputWatt level; Finally export to user for Beidou satellite receiver by Big Dipper satellite signal delivery outletTest.
A kind of Big Dipper satellite signal simulation realizing method of the present invention, comprises the steps:
1. first single-chip microcomputer is connected with outer PC by serial ports, receive serial ports send defend asterisk setting andPower setting order, so control FPGA processing module produce the C/A code of respective satellite and navigation message withAnd control signal attenuation module; Then the asterisk of defending receiving is sent to FPGA processing module, realize singleThe control of sheet machine to FPGA processing module; The running parameter of control simulation device is on LCD MODULE simultaneouslyShow;
What 2. first FPGA processing module was sent according to single-chip microcomputer defends asterisk, generates phase by the method for tabling look-upShould defend the navigation message of asterisk; Then under the control of symbol phases and code frequency word, produce corresponding code phasePosition and the spreading code of bit rate, generate the C/A code of corresponding Big Dipper satellite signal, to produced leadingAvionics literary composition numeric data code carries out DSSS; Last according to set IF carrier, in carrier phaseUnder the control of carrier frequency register, produce the digital sine range value of required frequency and phase place, withBand spectrum modulation code multiplies each other, and completes the BPSK(two-phase PSK to carrier wave) modulation, by the data of modulationStream signal, through formed filter, then, by output after each passage digital intermediate frequency Big Dipper signal stack, is sent intoTo D/A converter module;
3. D/A converter module is the modulated digital intermediate frequency big-dipper satellite letter from FPGA processing moduleNumber be converted to simulation Big Dipper satellite signal, after by analog bandpass filtering device, export to up-converter module;
4. up-converter module receives the simulation Big Dipper satellite signal after D/A converter module conversion, by Low Medium FrequencySimulation Big Dipper satellite signal through up-conversion, be converted to the nominal consistent with outdoor Big Dipper satellite signal and penetrateFrequently signal, sends into signal attenuation module;
5. the watt level of the radiofrequency signal of up-converter module output is fed back to monolithic by signal attenuation moduleMachine, single-chip microcomputer is according to the output power signal size of setting, and control signal attenuation module is to up-converter moduleThe radiofrequency signal of output decays, to adjust the emission of radio frequency signals of Big Dipper satellite signal delivery outlet outputWatt level; Finally export to user for Beidou satellite receiver by Big Dipper satellite signal delivery outletTest.
Compared with prior art, the present invention has following features:
1, can form and realize the simulation of Big Dipper satellite signal by simple circuit, thereby can be the Big DipperDevelopment, the test of receiver provide simulated environment; When only needing the signal of verifying receiver to receiveSituation during such as sensitivity test, can only generate single pass Big Dipper satellite signal, and simulator does not just needWant large-scale information to calculate, and save most of design of hardware and software;
2, user only need change part defending asterisk and power, by serial ports complete big-dipper satellite selection andPower selection, just can separate outer PC afterwards with single-chip microcomputer, thereby can reduce the volume of equipment,Be easy to carry;
3, can decay to the big-dipper satellite analog signal of simulator output by signal attenuation module,To be various signal power settings.
Brief description of the drawings
Fig. 1 is the theory diagram of a kind of Big Dipper satellite signal simulator of the present invention.
Detailed description of the invention
Referring to Fig. 1, a kind of Big Dipper satellite signal simulator of the present invention, mainly by power module, clock mouldPiece, LCD MODULE, single-chip microcomputer, FPGA processing module, D/A converter module, up-converter module andSignal attenuation module composition. Wherein,
Power module completes the requirement of power supply according to the power output of simulator and the inner each module of simulatorSupply voltage conversion, for the each module in simulator inside provides linear stabilized power supply. In the present embodiment, electricitySource module is according to simulation system power output and each chip of system and the requirement of circuit part to power supply,Power module adopts the linear stabilized power supply little, that ripple is little and power quality is good that takes up room, to completeGeneral 220V civil power, to the conversion of 5V, is given the modular circuits such as single-chip microcomputer, D/A converter module, up-conversionPower supply. FPGA processing module supply voltage is 3.3V, by the power supply of the inner baseband board of FPGA processing moduleManaging chip is realized the voltage transitions of 5V to 3.3V.
Clock module provides stable clock to single-chip microcomputer, realizes the control to whole simulator; Give simultaneouslyFPGA processing module provides work reference clock and obtains corresponding stable system interrupt signals by phaselocked loopWith Channel Synchronous pulse, drive the work of the baseband board in FPGA processing module; Realize modulus is turned simultaneouslyThe active configuration of die change piece; The local oscillator clock of required standard is provided to up-converter module simultaneously.
Single-chip microcomputer is the control CPU of this simulator, is implemented as follows function:
(1) be connected with outer PC by serial ports, single-chip microcomputer communicates module controls, receives serial portsThat sends defends asterisk setting and power setting order, and then controls FPGA processing module and produce respective satelliteC/A code and navigation message and control up-conversion power. In order to simplify the operation of this simulator, connectThe outer PC being connected on single-chip microcomputer is common computer. The serial ports that connects single-chip microcomputer and outer PC isRS2322 serial ports. In addition,, in order to improve the portability of this simulator, described outer PC is without alwaysBe connected on the serial ports of single-chip microcomputer, ought defend asterisk setting and power setting and complete by outer PC settingAfterwards, this defends asterisk and power parameter can be stored in single-chip microcomputer inside, for follow-up same satellite number and meritThe use of rate test condition; Only have in the time defending asterisk setting and/or power setting and need to change, just need will outsidePortion's PC is connected on single-chip microcomputer.
(2) running parameter of the control simulation device (signal power of defending asterisk and output of simulating as currentDeng) on LCD MODULE, show. In the present embodiment, described LCD MODULE is modelIt is 12864 liquid crystal display.
(3) asterisk of defending receiving is sent to FPGA processing module, realize single-chip microcomputer FPGA is processedThe control of module.
(4) control signal that the up-converter module watt level receiving is changed into signal attenuation module is sent outDeliver to signal attenuation module, realize the decay of up-converter module output signal. Signal attenuation module decay widthDegree can be a fixing value, and pre-stored in the inside of single-chip microcomputer, and this time signal attenuation module onlyCan realize fixed attenuation. But in order to export the big-dipper satellite analog signal of different capacity, in this enforcementIn example, on described single-chip microcomputer, can receive the power parameter that arranges transmitting from serial ports, decay with control signalThe power output size of module, to realize the variable attenuation of signal attenuation module.
The inside of FPGA processing module always has 12 passages, is the Primary Component of simulator. While comprisingBase circuit, interface control circuit, C/A code generator, navigation message generator, code NCO(numerical control vibrationDevice), carrier wave NCO, BPSK modulator etc., general function be three kinds of compositions of Big Dipper signal generation andFinal modulation:
(1) FPGA processing module inside is received that single-chip microcomputer is sent out and is defended after asterisk, raw by the method for tabling look-upBecome the navigation message of respective satellite number, and carry out chnnel coding processing, to carry out band spectrum modulation;
(2) that sends according to single-chip microcomputer defends asterisk, code NCO under the control of symbol phases and code frequency word,Code shift register produces the spreading code of corresponding code phase and bit rate, generates corresponding big-dipper satellite letterNumber C/A code, produced navigation message numeric data code is carried out to DSSS modulation;
(3), according to set IF carrier, carrier wave NCO is at carrier phase and carrier frequency registerUnder control, produce the digital sine range value of required frequency and phase place, multiply each other with band spectrum modulation code, completeThe BPSK of carrier wave L1 modulation in pairs;
(4) the digital Big Dipper intermediate-freuqncy signal after BPSK modulation is sent to D/A converter module.
What D/A converter module adopted is the AD9857 chip of 14 of high speeds, and maximum sample rate is 200MHz,Simulation with I, Q two-way orthogonal signalling simultaneously, the parallel i/q signal of two-way carries out interpolation and up-conversion computing,Finally convert by D/A and analog filter output intermediate frequency simulation Big Dipper signal. D/A converter module is comingBe converted to simulation big-dipper satellite letter from the modulated digital intermediate frequency Big Dipper satellite signal of FPGA processing moduleNumber, intermediate frequency is output as 20.098MHz, exports to up-converter module.
Up-converter module receives the simulation Big Dipper satellite signal after D/A converter module conversion, by Low Medium FrequencySimulation Big Dipper satellite signal, through up-conversion, is converted to the nominal radiofrequency signal consistent with outdoor big-dipper satellite,Frequency is 1561.098MHz, and exports to user for big-dipper satellite by Big Dipper satellite signal delivery outletThe test of receiver.
In order to allow varying environment signal can normally be received and facilitate user's contrast test, up-converter module andBetween Big Dipper satellite signal delivery outlet, go back signal attenuation module. Signal attenuation module is exported up-converter moduleThe watt level of radiofrequency signal feed back to single-chip microcomputer, single-chip microcomputer is according to the output power signal size of settingAnd Internal Control Procedure, the attenuation amplitude of control signal attenuation module, to penetrating of up-converter module outputFrequently signal is decayed, large to adjust the power of emission of radio frequency signals of Big Dipper satellite signal delivery outlet outputLittle. In the present embodiment, the be initially-90dBm of Big Dipper satellite signal of up-converter module output, by adjustingJoint be connected to Attenuation adjustable knob on single-chip microcomputer can provide thick decay (± 10dB) and essence decay (±1dB)。
A kind of Big Dipper satellite signal simulation realizing method that above-mentioned simulator is realized, comprises the steps:
1. first single-chip microcomputer is connected with outer PC by serial ports, receive serial ports send defend asterisk setting andPower setting order, so control FPGA processing module produce the C/A code of respective satellite and navigation message withAnd control signal attenuation module; Then the asterisk of defending receiving is sent to FPGA processing module, realize singleThe control of sheet machine to FPGA processing module; The running parameter of control simulation device is on LCD MODULE simultaneouslyShow;
What 2. first FPGA processing module was sent according to single-chip microcomputer defends asterisk, generates phase by the method for tabling look-upShould defend the navigation message of asterisk; Then under the control of symbol phases and code frequency word, produce corresponding code phasePosition and the spreading code of bit rate, generate the C/A code of corresponding Big Dipper satellite signal, to produced leadingAvionics literary composition numeric data code carries out DSSS; Last according to set IF carrier, in carrier phaseUnder the control of carrier frequency register, produce the digital sine range value of required frequency and phase place, withBand spectrum modulation code multiplies each other, and completes the BPSK modulation to carrier wave, and the traffic spike of modulation is filtered through overmoldingRipple device, then, by output after each passage digital intermediate frequency Big Dipper signal stack, is sent to D/A converter module;
3. D/A converter module is the modulated digital intermediate frequency big-dipper satellite letter from FPGA processing moduleNumber be converted to simulation Big Dipper satellite signal, after by analog bandpass filtering device, export to up-converter module;
4. up-converter module receives the simulation Big Dipper satellite signal after D/A converter module conversion, by Low Medium FrequencySimulation Big Dipper satellite signal through up-conversion, be converted to the nominal consistent with outdoor Big Dipper satellite signal and penetrateFrequently signal, sends into signal attenuation module;
5. the watt level of the radiofrequency signal of up-converter module output is fed back to monolithic by signal attenuation moduleMachine, single-chip microcomputer is according to the output power signal size of setting, and control signal attenuation module is to up-converter moduleThe radiofrequency signal of output decays, to adjust the emission of radio frequency signals of Big Dipper satellite signal delivery outlet outputWatt level; Finally export to user for Beidou satellite receiver by Big Dipper satellite signal delivery outletTest.
Claims (2)
1. a Big Dipper satellite signal simulator, comprises simulator, it is characterized in that: described simulatorMainly by power module, clock module, LCD MODULE, single-chip microcomputer, FPGA processing module, numberMould modular converter, up-converter module composition and signal attenuation module; Wherein,
Single-chip microcomputer: be first connected with outer PC by serial ports, the asterisk of defending that reception serial ports is sent is establishedPut and power setting order, and then control the C/A code of FPGA processing module generation respective satellite and leadAvionics literary composition and control signal attenuation module; Then the asterisk of defending receiving is sent to FPGA processingModule, realizes the control of single-chip microcomputer to FPGA processing module; The running parameter of control simulation device simultaneouslyOn LCD MODULE, show;
FPGA processing module: that first sends according to single-chip microcomputer defends asterisk, generates by the method for tabling look-upThe navigation message of respective satellite number; Then under the control of symbol phases and code frequency word, produce correspondingThe spreading code of code phase and bit rate, generates the C/A code of corresponding Big Dipper satellite signal, to produceRaw navigation message numeric data code carries out DSSS; Last according to set IF carrier,Under the control of carrier phase and carrier frequency register, produce the digital sine of required frequency and phase placeRange value, multiplies each other with band spectrum modulation code, completes the BPSK modulation to carrier wave, by the data flow of modulationSignal, through formed filter, then, by output after each passage digital intermediate frequency Big Dipper signal stack, is sent intoTo D/A converter module;
D/A converter module: the modulated digital intermediate frequency big-dipper satellite from FPGA processing moduleSignal is converted to simulation Big Dipper satellite signal, after by analog bandpass filtering device, exports to up-conversion mouldPiece;
Up-converter module: receive the simulation Big Dipper satellite signal after D/A converter module conversion, in lowSimulation Big Dipper satellite signal frequently, through up-conversion, is converted to the mark consistent with outdoor Big Dipper satellite signalClaim radiofrequency signal, send into signal attenuation module;
Signal attenuation module; This signal attenuation module is serially connected in up-converter module and Big Dipper satellite signal is defeatedBetween outlet; Signal attenuation module feeds back to the watt level of the radiofrequency signal of up-converter module outputSingle-chip microcomputer, single-chip microcomputer is according to the output power signal size of setting, and control signal attenuation module is to upper changeThe radiofrequency signal of frequency module output decays, to adjust the radio frequency of Big Dipper satellite signal delivery outlet outputThe watt level of signal transmitting; Finally export to user for the Big Dipper by Big Dipper satellite signal delivery outletThe test of DVB.
2. a Big Dipper satellite signal simulation realizing method, is characterized in that comprising the steps:
1. first single-chip microcomputer is connected with outer PC by serial ports, and the asterisk of defending that reception serial ports is sent is establishedPut and power setting order, and then control the C/A code of FPGA processing module generation respective satellite and leadAvionics literary composition and control signal attenuation module; Then the asterisk of defending receiving is sent to FPGA processingModule, realizes the control of single-chip microcomputer to FPGA processing module; The running parameter of control simulation device simultaneouslyOn LCD MODULE, show;
What 2. first FPGA processing module was sent according to single-chip microcomputer defends asterisk, generates by the method for tabling look-upThe navigation message of respective satellite number; Then under the control of symbol phases and code frequency word, produce correspondingThe spreading code of code phase and bit rate, generates the C/A code of corresponding Big Dipper satellite signal, to produceRaw navigation message numeric data code carries out DSSS; Last according to set IF carrier,Under the control of carrier phase and carrier frequency register, produce the digital sine of required frequency and phase placeRange value, multiplies each other with band spectrum modulation code, completes the BPSK modulation to carrier wave, by the data flow of modulationSignal, through formed filter, then, by output after each passage digital intermediate frequency Big Dipper signal stack, is sent intoTo D/A converter module;
3. D/A converter module is the modulated digital intermediate frequency big-dipper satellite from FPGA processing moduleSignal is converted to simulation Big Dipper satellite signal, after by analog bandpass filtering device, exports to up-conversion mouldPiece;
4. up-converter module receives the simulation Big Dipper satellite signal after D/A converter module conversion, in lowSimulation Big Dipper satellite signal frequently, through up-conversion, is converted to the mark consistent with outdoor Big Dipper satellite signalClaim radiofrequency signal, send into signal attenuation module;
5. the watt level of the radiofrequency signal of up-converter module output is fed back to list by signal attenuation moduleSheet machine, single-chip microcomputer is according to the output power signal size of setting, and control signal attenuation module is to up-conversionThe radiofrequency signal of module output decays, to adjust the radio frequency letter of Big Dipper satellite signal delivery outlet outputNumber transmitting watt level; Finally exporting to user by Big Dipper satellite signal delivery outlet defends for the Big DipperThe test of star receiver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210280519.0A CN103576168B (en) | 2012-08-08 | 2012-08-08 | A kind of Big Dipper satellite signal simulator and its implementation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210280519.0A CN103576168B (en) | 2012-08-08 | 2012-08-08 | A kind of Big Dipper satellite signal simulator and its implementation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103576168A CN103576168A (en) | 2014-02-12 |
| CN103576168B true CN103576168B (en) | 2016-05-18 |
Family
ID=50048339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210280519.0A Active CN103576168B (en) | 2012-08-08 | 2012-08-08 | A kind of Big Dipper satellite signal simulator and its implementation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103576168B (en) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104237905B (en) * | 2014-09-12 | 2017-02-22 | 湖南北云科技有限公司 | Big Dipper detector |
| CN104316938B (en) * | 2014-09-25 | 2016-10-19 | 上海欧科微航天科技有限公司 | A kind of New Satellite simulator for the plesiochronous communication system of low orbit satellite |
| CN104459725A (en) * | 2014-11-24 | 2015-03-25 | 中国电子科技集团公司第二十研究所 | Satellite signal simulation generator applied to BeiDou communication system |
| CN104579826A (en) * | 2014-12-24 | 2015-04-29 | 福建星海通信科技有限公司 | Simulation method for Beidou terminal device software communication protocol in Beidou system |
| CN104635246A (en) * | 2015-02-27 | 2015-05-20 | 上海市计量测试技术研究院 | System and method for detecting dynamic range of satellite navigation signal |
| CN104898135B (en) * | 2015-06-18 | 2017-07-28 | 北京航空航天大学 | Satellite navigation signals analogy method and simulation system based on FPGA |
| CN105116424A (en) * | 2015-07-24 | 2015-12-02 | 南京航空航天大学 | Beidou satellite navigation signal simulation source based on file generation and playback |
| CN105607085B (en) * | 2015-12-11 | 2019-01-25 | 湖南中森通信科技有限公司 | A kind of general Beidou subscriber machine test macro and method |
| CN106338744A (en) * | 2015-12-25 | 2017-01-18 | 深圳艾科创新微电子有限公司 | Beidou signal simulation device, testing device for simulating Beidou signal, and debugging system |
| CN105974442B (en) * | 2016-05-04 | 2018-09-04 | 广东工业大学 | Satellite navigation system hardware-in-the-loop simulation test platform and its method |
| CN106199649A (en) * | 2016-07-22 | 2016-12-07 | 中国人民解放军63908部队 | Satellite navigation receiver test platform |
| CN106483534B (en) * | 2016-10-08 | 2019-02-15 | 西安电子科技大学 | A kind of Beidou satellite navigation emulation mode of distributed all digital |
| CN107202998B (en) * | 2017-06-19 | 2023-09-29 | 北京航天长征飞行器研究所 | Real-time satellite signal simulator and simulation method for power line communication |
| CN107907892A (en) * | 2017-09-15 | 2018-04-13 | 长光卫星技术有限公司 | A kind of navigation signal simulator based on PXI frameworks, closed loop controller and closed loop test method |
| CN107728125B (en) * | 2017-09-29 | 2020-03-10 | 桂林电子科技大学 | Ionosphere scintillation satellite signal simulation system and use method |
| CN109239738A (en) * | 2017-12-28 | 2019-01-18 | 中国电子科技集团公司第二十研究所 | Satellite-signal simulative generator applied to three signal communications system of Beidou |
| CN108594632B (en) * | 2018-04-25 | 2021-01-29 | 山东山大电力技术股份有限公司 | Satellite time service scene recording device and method based on satellite time service module |
| CN109358354B (en) * | 2018-11-20 | 2020-12-15 | 中国电子科技集团公司第五十四研究所 | Handheld navigation signal simulator |
| CN109444923A (en) * | 2018-12-03 | 2019-03-08 | 桂林电子科技大学 | A kind of Beidou three generations satellite-signal simulation system and analog signal generating method |
| CN110531384A (en) * | 2019-08-20 | 2019-12-03 | 桂林电子科技大学 | A kind of Galilean satellite signal imitation system and its analogy method |
| CN113820975A (en) * | 2021-08-28 | 2021-12-21 | 国营芜湖机械厂 | Combined programmable radio beacon simulator |
| CN114040487B (en) * | 2021-12-27 | 2022-08-12 | 扬州宇安电子科技有限公司 | Real-time attenuation control method for satellite uplink and downlink simulation equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101261317A (en) * | 2008-04-25 | 2008-09-10 | 浙江大学 | High dynamic state multi- mode satellite navigation signal source analogue method and its device |
| CN101770016A (en) * | 2008-12-31 | 2010-07-07 | 郑州威科姆科技股份有限公司 | GPS time service signal generator based on Beidou satellite |
-
2012
- 2012-08-08 CN CN201210280519.0A patent/CN103576168B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101261317A (en) * | 2008-04-25 | 2008-09-10 | 浙江大学 | High dynamic state multi- mode satellite navigation signal source analogue method and its device |
| CN101770016A (en) * | 2008-12-31 | 2010-07-07 | 郑州威科姆科技股份有限公司 | GPS time service signal generator based on Beidou satellite |
Non-Patent Citations (1)
| Title |
|---|
| 多模卫星信号模拟器的设计与实现;侯博 等;《计算机测量与控制》;20120131;第20卷(第1期);第170-172，176页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103576168A (en) | 2014-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103576168B (en) | A kind of Big Dipper satellite signal simulator and its implementation | |
| CN101349740B (en) | General-purpose satellite navigation signal interference source and method for generating signal thereof | |
| CN102932072B (en) | High dynamic satellite channel simulator | |
| CN102147473B (en) | Common-frequency multi-system satellite navigation signal generation system | |
| CN102565817B (en) | Roland-C timing signal simulator | |
| CN102176029B (en) | Global positioning system (GPS) direct and multipath signal simulator and simulation method | |
| CN109444923A (en) | A kind of Beidou three generations satellite-signal simulation system and analog signal generating method | |
| CN104730541A (en) | Real-time GNSS/INS (global navigation satellite system/inertial navigation system) combined navigation signal simulator based on PXI (PCI extensions for instrumentation) bus | |
| CN103792552A (en) | System and method for generating satellite navigation baseband signal | |
| CN110058268B (en) | Ionospheric scintillation closed-loop test system and method based on GNSS | |
| Pramod | GPS Based advanced soldier Tracking with emergency messages & communication system | |
| CN101770016B (en) | GPS time service signal generator based on Beidou satellite | |
| CN110133693A (en) | Big-dipper satellite positioning terminal and its localization method based on ARM Crotex-M4 and μ CGUI | |
| CN110531384A (en) | A kind of Galilean satellite signal imitation system and its analogy method | |
| CN206930781U (en) | A kind of digital demultiplexing satellite navigation signal simulator and detecting system | |
| CN103441811B (en) | A kind of AIS slot synchronization triggering system based on the UTC time | |
| CN206440829U (en) | One kind miniaturization satellite navigation signals generation board | |
| CN202904019U (en) | Beidou satellite signal simulator | |
| CN111638640B (en) | BPM shortwave time service signal simulator | |
| CN211453961U (en) | Indoor and outdoor combined positioning system | |
| CN106199649A (en) | Satellite navigation receiver test platform | |
| CN209446772U (en) | A kind of Beidou three generations satellite-signal simulation system | |
| CN103202090B (en) | Reduce method, device and the terminal device disturbed between communication module in terminal device | |
| JP2010183125A (en) | Gps signal transmitter and signal transmission method thereof | |
| CN109358354A (en) | A kind of handheld navigation signal simulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 518000 2001, block a, building 3, Liutang business building, No.21, Qianjin Second Road, Liutang community, Xixiang street, Bao'an District, Shenzhen City, Guangdong Province Patentee after: China Hebei tus Technology Group Co., Ltd Address before: 518020 main building of science and Technology Innovation Park, Xixiang the Peach Garden, Guangdong, Shenzhen, Baoan District 520 Patentee before: SHENZHEN TOJOIN UNITED TECHNOLOGY CO., LTD. |
|
| CP03 | Change of name, title or address | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210524 Address after: 518000 20 / F, block a, Liutang business building, 21 Qianjin 2nd Road, Xixiang street, Bao'an District, Shenzhen City, Guangdong Province Patentee after: SHENZHEN TOJOIN COMMUNICATION TECHNOLOGY Co.,Ltd. Address before: 518000 2001, block a, building 3, Liutang business building, 21 Qianjin 2nd Road, Liutang community, Xixiang street, Bao'an District, Shenzhen City, Guangdong Province Patentee before: China Hebei tus Technology Group Co.,Ltd. |
|
| TR01 | Transfer of patent right |