CN103559168A - Method and device for continuously calculating large point amplitude probability distribution - Google Patents

Abstract

The invention provides a method and a device for continuously calculating large point amplitude probability distribution. The device comprises a CPLD (complex programmable logic device) or FPGA (field programmable gate array) control unit, an A/D (analog-to-digital) sampling unit, a switch bus, an SRAM (static random access memory), a double-port RAM (random access memory) and a host CPU (central processing unit) which are mutually connected and communicated, the A/D sampling unit is used for acquiring intermediate frequency signals and transmitting the intermediate frequency signals to the switch bus, the frequency of the intermediate frequency signals is converted by a receiver or a frequency spectrograph, the intermediate frequency signals pass an anti-aliasing filter, the switch bus is used for transmitting the intermediate frequency signals to the SRAM, the SRAM is used for storing and updating the intermediate frequency signals in a preset mode, and the host CPU is used for reading data of the double-port RAM and the SRAM and simultaneously updating probability statistical values within the whole amplitude range on a screen. By the aid of the scheme, the average power of the signals can be accurately calculated in real time, and measurement of continuous APD (amplitude probability distribution) and calculation of the average power can be realized after the device is connected with the intermediate frequency of the receiver or the frequency spectrograph.

Description

Count the greatly method and apparatus of amplitude probability distribution of a kind of continuous calculating

Technical field

The invention belongs to amplitude probability distribution computing technique field, in particular a kind of continuous calculating method and apparatus of amplitude probability distribution of counting greatly.

Background technology

Current APD computing method are all that user sets after certain counting, instrument collection is enough counted, calculate one time APD result, if counting of needing is many, test result need to be waited for and refreshing for a long time once, be difficult to observe continuous variation and the characteristic rule of APD, and the signal of which kind of probability distribution has the greatest impact to communication system.

Therefore, there is defect in prior art, needs to improve.

Summary of the invention

Technical matters to be solved by this invention is for the deficiencies in the prior art, the method and apparatus that provides a kind of continuous calculating to count greatly amplitude probability distribution.

Technical scheme of the present invention is as follows:

Count the greatly device of amplitude probability distribution of continuous calculating, wherein, by CPLD or FPGA control module, A/D sampling unit, bus switches, static memory SRAM, dual port RAM and host CPU interconnects and mutually communication form; Described A/D sampling unit for after gathering receiver or frequency spectrograph frequency conversion and the intermediate-freuqncy signal after frequency overlapped-resistable filter send to bus switches; Described bus switches is for sending to static memory SRAM by described intermediate-freuqncy signal; Described static memory SRAM is used for adopting predetermined way to store and upgrades described intermediate-freuqncy signal; Described dual port RAM is for storing the instantaneous result of calculation of all amplitude probability distribution and making host CPU and the conflict free access of CPLD; Described CPLD or FPGA control module are for the read-write of described static memory SRAM and described dual port RAM, and the statistical computation of the interior amplitude probability distribution of whole amplitude range; Described host CPU, for reading the data of described dual port RAM and described static memory SRAM, upgrades the probability statistics value in whole amplitude range simultaneously, and according to preordering method, calculates the average power of the probability in whole amplitude range.

Count the greatly device of amplitude probability distribution of described continuous calculating, wherein, the predetermined way that described static memory SRAM adopts, for often depositing data in, will deposit time data deletion the earliest in data in.

Count the greatly device of amplitude probability distribution of described continuous calculating, wherein, the 6-12 that the processing clock in described CPLD or FPGA control module is sampling clock doubly.

Count the greatly device of amplitude probability distribution of described continuous calculating, wherein, described CPLD or FPGA control module are comprised of worker state machine and register, and what described register comprised total some number register, intermediate value register, SRAM circle queue reads address pointer register and write address pointer register, described worker state machine for completing the conversion between the first state and the second state under the driving of processing clock, described the first state, the address pointer using current new sampled data as described dual port RAM, reads the data of address location in described dual port RAM and adds 1 and write address location in described dual port RAM again, if the value initial value 0 of address pointer register and the value of write address pointer register are read in judgement, add 1 whether identical with the value of always putting number register, it is the read operation of not reading read-write operation and the SRAM circle queue of address pointer register, otherwise read in static memory SRAM, read address pointer register indication value in intermediate value register, by reading address pointer register value, add 1 and the value complementation of total some number register is given and read address pointer register again, write address pointer adds the complementation of 1 pair of total some number register simultaneously, and complementation value is assigned to write address pointer register, new sampled data is write in the unit of static memory SRAM of write address pointer register indication, described the second state, whether the value that address pointer register is read in judgement is greater than 0, otherwise without operation, is the value of intermediate value register to be outputed on the address bus of dual port RAM, reads the value of dual port RAM, and subtracts 1 and be then written in dual port RAM.

Count the greatly device of amplitude probability distribution of described continuous calculating, wherein, the working method of described static memory SRAM and dual port RAM is write-after-read, the calculating that completes a point can be controlled in 3 processing clock within the cycle.

Count the greatly device of amplitude probability distribution of described continuous calculating, wherein, the computing formula of the preordering method of the average power of the probability in the whole amplitude range of described calculating is:

$\mathrm{Pav}=\underset{i=0}{\overset{2^m-1}{\mathrm{\Σ}}}(i^2*\frac{C_i}{n})$ Or $\mathrm{Pav}=\underset{i=0}{\overset{2^m-1}{\mathrm{\Σ}}}(10\log (i^2/50)*\frac{C_i}{n});$ Wherein, average power is Pav; N is that total statistics is counted; Ci is the statistics number that i is ordered; I is the index of counting.

A kind of count the greatly method of amplitude probability distribution of continuous calculating, wherein, comprise the following steps: set and always count as n, new sampled value is Ai, and when number of samples surpasses after n, Ai value indication internal storage location statistics number adds 1, A (i+n) value indication internal storage location statistics number subtracts 1, obtained the corresponding statistics number of range value of a continuous n sampled point, the statistics number that host CPU reads each Ai amplitude point from dual port RAM is again divided by the n that always counts, and just obtains the value of the amplitude probability distribution that continuous n orders.

Count the greatly method of amplitude probability distribution of described continuous calculating, wherein, calculates the average power of continuous amplitude probability distribution according to count the greatly value of amplitude probability distribution of continuous calculating.

Count the greatly method of amplitude probability distribution of described continuous calculating, wherein, the computing formula of described average power is:

$\mathrm{Pav}=\underset{i=0}{\overset{2^m-1}{\mathrm{\Σ}}}(i^2*\frac{C_i}{n})$ Or $\mathrm{Pav}=\underset{i=0}{\overset{2^m-1}{\mathrm{\Σ}}}(10\log (i^2/50)*\frac{C_i}{n});$ Wherein, average power is Pav; N is that total statistics is counted; Ci is the statistics number that i is ordered; I is the index of counting.

Adopt such scheme, 1, can realize continuously the measurement of amplitude probability distribution is calculated, gather number of samples and reach after user's set point number, point of every sampling, just can complete whole user's set point number amplitude probability distribution statistics calculating and upgrade to show.Even if user is unfamiliar with the relevant Changing Pattern of signal like this, enough large user also can be set and counts, thereby observe the statistics of continous-stable.2, the average power that accurately calculates signal that method of the present invention can be real-time, this device is connected to after the intermediate frequency of receiver or frequency spectrograph, can realize the measurement of continuous APD and the calculating of average power.3, can be applied in spectrum analyzer or receiver, realize the calculating of continuous fast amplitude probability distribution, and the real-time average power of measuring-signal, the impact of the harassing and wrecking source that is very suitable for observing different qualities on the digital communication system of different systems, the relation of setting up the indexs such as amplitude probability distribution and the bit error rate, realizes with low cost.

Accompanying drawing explanation

Fig. 1 is count the greatly structural representation of device of amplitude probability distribution of the continuous calculating of the present invention.

Fig. 2 is the circle queue access schematic diagram of SRAM in the present invention.

Fig. 3 is count greatly a kind of embodiment structural representation of device of amplitude probability distribution of the continuous calculating of the present invention.

Embodiment

Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.

Embodiment 1

As shown in Figure 1, this contrive equipment is comprised of as control computing unit 104, A/D sampling unit 101, bus switch 102, static memory SRAM103, dual port RAM 105 CPLD (or FPGA).Intermediate-freuqncy signal after receiver or frequency spectrograph frequency conversion is after frequency overlapped-resistable filter, enter A/D sampling unit 101, the data of sampling enter the memory cell in the SRAM103 of FPGA104 controller appointment, and SRAM103 often deposits data in, read and lose the oldest data.FPGA104 is usingd the allocation index of current new sampled data as dual port RAM 105, data reading in dual port RAM 105 is also added on this basis and write again and again in this address, using the data of reading in SRAM103 as dual port RAM 105 allocation indexs, the data reading in dual port RAM 105 is also subtracted on this basis and write again and again in dual port RAM 105 addresses again.Each range value of intermediate-freuqncy signal has a statistics like this, has completed and specify the probability statistics of counting in the time of an intermediate-freuqncy signal of every sampling, and host CPU 106 can from dual port RAM 105, sequentially reading all amplitude numerical value carries out display update.

The sampling clock of A/D sampling unit 101 and the processing clock of module are inputted by the clock generating module of instrument or equipment.Reset signal is controlled by master cpu 106, for amplitude probability distribution, starts to calculate the whole device of front reset.

For guaranteeing the real-time processing of sampled data of A/D sampling unit 101 outputs, processing clock is generally the more than 6 times of sampling clock, because the accessing time sequence of SRAM103 generally needs 2 to 3 clock period just can complete, the read and write access of dual port RAM 105 also needs 2-3 cycle.CPLD104 inside is comprised of worker state machine and register, comprise the read-write of SRAM static memory 103 and the read-write of DRAM dual port RAM 105, and the statistical computation of the interior amplitude probability distribution of whole amplitude range, main register comprises total some number register, intermediate value register, SRAM circle queue as shown in Figure 2, and the position of reading address pointer register and write address pointer register has been shown in Fig. 2.CPLD internal work flow process is mainly completed the conversion of two main states under the driving of processing clock by internal state machine:

When state 1, the address pointer using current new sampled data as dual port RAM, reads the content of this address location in dual port RAM and adds 1 and write this unit again, if reading value initial value 0 and the write address pointer of address pointer register, judgement adds 1 value being not equal to total some number register, do not read the operation of address pointer register and the read operation of SRAM, otherwise read in SRAM, read address pointer register indication value in the intermediate value register of FPGA, reading address pointer register value, add 1 and the value complementation of total some number register is given and read address pointer register again, write address pointer adds the complementation of 1 pair of total some number register simultaneously, and complementation value is assigned to write address pointer register, the data of new sampling are write in the sram cell of write address pointer register indication.

When state 2, whether the value that address pointer register is read in judgement is greater than 0, if 0 this state that is less than is without other subsequent operation, otherwise, the value of intermediate value register is outputed on the address bus of DRAM dual port RAM, read the value of dual port RAM, and this value is subtracted to 1 be then written in this address of dual port RAM.

All RAM operations, owing to being write-after-read, can be controlled in 3 cycles and be completed by FPGA.

Host CPU can be by reading DRAM dual port RAM content, on screen, upgrade the probability statistics value in whole amplitude range, and the relevant trigger condition based on statistical probability can be set on main frame, because this device is to calculate continuously amplitude probability distribution, therefore can trigger in real time.Can calculate the average power based on probability simultaneously.

The method of calculating amplitude probability distribution is continuously: set and always count as n, new sampled value is Ai, when number of samples surpasses after n, Ai value indication internal storage location statistics number adds 1, A (i+n) value indication internal storage location statistics number subtracts 1, obtained so the corresponding statistics number of range value of a continuous n sampled point, the statistics number that industrial computer module CPU reads each Ai amplitude point from dual port RAM is again divided by the n that always counts, and just obtained the value of the amplitude probability distribution that continuous n orders.

The computing method of two kinds of average powers of statistics: from 0 address location of dual port RAM, what be m up to AD bit wide is the highest by 2 ^m-1 unit, location superlatively, linear averaging power is

n is that total statistics is counted, and Ci is the statistics number that i is ordered, and i is the index of counting.Logarithmic mean performance number is

calculate.

User changes after the hardware parameters such as centre frequency, directly sends reset signal, by all statistical content zero clearings of SRAM and dual port RAM by controlling FPGA.

Embodiment bis-

On the basis of above-described embodiment, as in certain model microwave spectrometer, original amplitude probability distribution need to, by calculating amplitude probability distribution value after continuous sampling n point one time, realize continuous amplitude probability distribution calculating and the calculating of average power again after this invention.

Specific design as shown in Figure 3, for example, if sampling clock and if sampling data rate are 4MHz, the converter AD9647 (16) that AD sampling unit 201 use is 16, intermediate frequency process clock is 40MHz, according to user's request maximum, complete 1,000,000 amplitude probability distribution, therefore 1M word cell of SRAM203 capacity just can, so adopted CY7C1061AV33 (1M*16), AD sampling unit 201 is 16, need the counting unit of 64K 32, so DRAM205 1 IDT70V659 (128K*36), CPLD204 EPM1270F256C3 have been adopted.Bus switches 202 is controlled by CPLD204, bus switches 202 is connected and new sampled data is sent into SRAM203, bus switches 202 disconnects, read the data of SRAM203 and carry out writing SRAM203 after computing again, bus switches 202 is mainly used in preventing that the data bus of sampled data and the data bus of SRAM203 from competing or disturbing.

It is 10000 that user counts by instrument panel input probability statistics.Instrument software arranges inner each status register of CPLD204, inner each register zero clearing, and reset SRAM203 and DRAM205.After a sampled value of AD sampling unit 201 outputs, the inner total some number register of CPLD204 adds 1, suppose that this value is for 0x7724, CPLD204 internal state machine gets the hang of 1, reads the value of 0x7724 indication address location in dual port RAM 205 and this value is added to 1 to write back this unit again, if reading value initial value 0 and the write address pointer of address pointer register, judgement adds 1 value 10000 being not equal to total some number register, do not read the operation of address pointer register and the read operation of SRAM203, otherwise read in SRAM203, read address pointer register indication value in the intermediate value register of FPGA204, reading address pointer register value, add 1 and the value complementation of total some number register is given and read address pointer register again, write address pointer adds the complementation of 1 pair of total some number register simultaneously, and complementation value is assigned to write address pointer register, new sampled data 0x7724 is write in the sram cell of write address pointer register indication.

When state 2, whether the value that address pointer register is read in judgement is greater than 0, if 0 this state that is less than is without other subsequent operation, otherwise, the value of intermediate value register is outputed on the address bus of DRAM dual port RAM, read the value of dual port RAM, and this value is subtracted to 1 be then written in this address of dual port RAM.

Utilize formula $\mathrm{Pav}=\underset{i=0}{\overset{2^m-1}{\mathrm{\Σ}}}(i^2*\frac{C_i}{n})$ Or $\mathrm{Pav}=\underset{i=0}{\overset{2^m-1}{\mathrm{\Σ}}}(10\log (i^2/50)*\frac{C_i}{n})$ Can calculate in real time average power.

Host CPU 206 is for ETX industrial computer module CPU is by reading DRAM dual port RAM address 0 content to address 0xFFFF, on screen, upgrade the probability statistics value in whole amplitude range, and the relevant trigger condition based on statistical probability can be set on main frame, because this device is to calculate continuously amplitude probability distribution, therefore can be for real-time triggering.

The algorithm of calculating amplitude probability distribution statement continuously: set and always count as n, new sampled value is Ai, when number of samples surpasses after n, Ai value indication internal storage location statistics number adds 1, A (i+n) value indication internal storage location statistics number subtracts 1, in the time of calculating amplitude probability distribution, as long as the corresponding statistics number of each Ai value is to the amplitude probability distribution that this range value is corresponding divided by the n that always counts.

User changes after the hardware parameters such as centre frequency, directly sends reset signal, by all statistical content zero clearings of SRAM and dual port RAM by controlling FPGA.

Embodiment tri-

On the basis of above-described embodiment, count the greatly device of amplitude probability distribution of a kind of continuous calculating of the present invention, as shown in Figure 1, wherein, by CPLD or FPGA control module 104, A/D sampling unit 101, bus switches 102, static memory SRAM103, dual port RAM 105 and host CPU 106, interconnected and mutually communication form; Described A/D sampling unit 101 sends to bus switches 102 for the intermediate-freuqncy signal after gathering receiver or frequency spectrograph frequency conversion and after frequency overlapped-resistable filter; Described bus switches 102 is for sending to static memory SRAM103 by described intermediate-freuqncy signal; Described static memory SRAM103 is used for adopting predetermined way to store and upgrades described intermediate-freuqncy signal; Described dual port RAM 105 is for storing the instantaneous result of calculation of all amplitude probability distribution and making host CPU 106 and CPLD or the conflict free access of FPGA control module 104; Described CPLD or FPGA control module 104 are for the read-write of described static memory SRAM103 and described dual port RAM 105, and the statistical computation of the interior amplitude probability distribution of whole amplitude range; Described host CPU 106, for reading the data of described dual port RAM 105 and described static memory SRAM103, upgrades the probability statistics value in whole amplitude range simultaneously, and according to preordering method, calculates the average power of the probability in whole amplitude range.

Furthermore, the predetermined way that described static memory SRAM103 adopts, for often depositing data in, is deleted depositing time data the earliest in data in.

Furthermore, the 6-12 that the processing clock in described CPLD or FPGA control module 104 is sampling clock doubly.

Furthermore, described CPLD or FPGA control module 104 are comprised of worker state machine and register, and what described register comprised total some number register, intermediate value register, SRAM circle queue reads address pointer register and write address pointer register, described worker state machine for completing the conversion between the first state and the second state under the driving of processing clock, described the first state, the address pointer using current new sampled data as described dual port RAM, reads the data of address location in described dual port RAM 105 and adds 1 and write address location in described dual port RAM 105 again, if the value initial value 0 of address pointer register and the value of write address pointer register are read in judgement, add 1 whether identical with the value of always putting number register, it is the read operation of not reading read-write operation and the SRAM circle queue of address pointer register, otherwise read in static memory SRAM, read address pointer register indication value in intermediate value register, by reading address pointer register value, add 1 and the value complementation of total some number register is given and read address pointer register again, write address pointer adds the complementation of 1 pair of total some number register simultaneously, and complementation value is assigned to write address pointer register, new sampled data is write in the unit of static memory SRAM103 of write address pointer register indication, described the second state, whether the value that address pointer register is read in judgement is greater than 0, otherwise without operation, is the value of intermediate value register to be outputed on the address bus of dual port RAM, reads the value of dual port RAM, and subtracts 1 and be then written in dual port RAM.

Furthermore, the working method of described static memory SRAM103 and dual port RAM 105 is write-after-read, and the calculating that completes a point can be controlled in 3 processing clock within the cycle.

Furthermore, the computing formula of the preordering method of the average power of the probability in the whole amplitude range of described calculating is:

$\mathrm{Pav}=\underset{i=0}{\overset{2^m-1}{\mathrm{\Σ}}}(i^2*\frac{C_i}{n})$ Or $\mathrm{Pav}=\underset{i=0}{\overset{2^m-1}{\mathrm{\Σ}}}(10\log (i^2/50)*\frac{C_i}{n});$ Wherein, average power is Pav; N is that total statistics is counted; Ci is the statistics number that i is ordered; I is the index of counting.

Embodiment tetra-

On the basis of above-described embodiment, a kind of count the greatly method of amplitude probability distribution of continuous calculating, wherein, comprise the following steps: set and always count as n, new sampled value is Ai, when number of samples surpasses after n, Ai value indication internal storage location statistics number adds 1, A (i+n) value indication internal storage location statistics number subtracts 1, obtained the corresponding statistics number of range value of a continuous n sampled point, the statistics number that host CPU reads each Ai amplitude point from dual port RAM is again divided by the n that always counts, and just obtains the value of the amplitude probability distribution that continuous n orders.

Count the greatly method of amplitude probability distribution of described continuous calculating, wherein, calculates the average power of continuous amplitude probability distribution according to count the greatly value of amplitude probability distribution of continuous calculating.

Count the greatly method of amplitude probability distribution of described continuous calculating, wherein, the computing formula of described average power is:

$\mathrm{Pav}=\underset{i=0}{\overset{2^m-1}{\mathrm{\Σ}}}(i^2*\frac{C_i}{n})$ Or $\mathrm{Pav}=\underset{i=0}{\overset{2^m-1}{\mathrm{\Σ}}}(10\log (i^2/50)*\frac{C_i}{n});$ Wherein, average power is Pav; N is that total statistics is counted; Ci is the statistics number that i is ordered; I is the index of counting.

Adopt such scheme, 1, can realize continuously the measurement of amplitude probability distribution is calculated, gather number of samples and reach after user's set point number, point of every sampling, just can complete whole user's set point number amplitude probability distribution statistics calculating and upgrade to show.Even if user is unfamiliar with the relevant Changing Pattern of signal like this, enough large user also can be set and counts, thereby observe the statistics of continous-stable.2, the average power that accurately calculates signal that method of the present invention can be real-time, this device is connected to after the intermediate frequency of receiver or frequency spectrograph, can realize the measurement of continuous APD and the calculating of average power.3, can be applied in spectrum analyzer or receiver, realize the calculating of continuous fast amplitude probability distribution, and the real-time average power of measuring-signal, the impact of the harassing and wrecking source that is very suitable for observing different qualities on the digital communication system of different systems, the relation of setting up the indexs such as amplitude probability distribution and the bit error rate, realizes with low cost.

Should be understood that, for those of ordinary skills, can be improved according to the above description or convert, and all these improvement and conversion all should belong to the protection domain of claims of the present invention.

Claims (9)

1. the continuous calculating device for amplitude probability distribution of counting greatly, is characterized in that, by CPLD or FPGA control module, A/D sampling unit, bus switches, static memory SRAM, dual port RAM and host CPU interconnects and mutually communication form; Described A/D sampling unit for after gathering receiver or frequency spectrograph frequency conversion and the intermediate-freuqncy signal after frequency overlapped-resistable filter send to bus switches; Described bus switches is for sending to static memory SRAM by described intermediate-freuqncy signal; Described static memory SRAM is used for adopting predetermined way to store and upgrades described intermediate-freuqncy signal; Described dual port RAM is for storing the instantaneous result of calculation of all amplitude probability distribution and making host CPU and the conflict free access of CPLD; Described CPLD or FPGA control module are for the read-write of described static memory SRAM and described dual port RAM, and the statistical computation of the interior amplitude probability distribution of whole amplitude range; Described host CPU, for reading the data of described dual port RAM and described static memory SRAM, upgrades the probability statistics value in whole amplitude range simultaneously, and according to preordering method, calculates the average power of the probability in whole amplitude range.

2. the continuous calculating as claimed in claim 1 device of amplitude probability distribution of counting greatly, is characterized in that, the predetermined way that described static memory SRAM adopts, for often depositing data in, will deposit time data deletion the earliest in data in.

3. the continuous calculating as claimed in claim 1 device of amplitude probability distribution of counting greatly, is characterized in that, the 6-12 that the processing clock in described CPLD or FPGA control module is sampling clock doubly.

4. the continuous calculating as claimed in claim 3 device of amplitude probability distribution of counting greatly, it is characterized in that, described CPLD or FPGA control module are comprised of worker state machine and register, and what described register comprised total some number register, intermediate value register, SRAM circle queue reads address pointer register and write address pointer register, described worker state machine for completing the conversion between the first state and the second state under the driving of processing clock, described the first state, the address pointer using current new sampled data as described dual port RAM, reads the data of address location in described dual port RAM and adds 1 and write address location in described dual port RAM again, if the value initial value 0 of address pointer register and the value of write address pointer register are read in judgement, add 1 whether identical with the value of always putting number register, it is the read operation of not reading read-write operation and the SRAM circle queue of address pointer register, otherwise read in static memory SRAM, read address pointer register indication value in intermediate value register, by reading address pointer register value, add 1 and the value complementation of total some number register is given and read address pointer register again, write address pointer adds the complementation of 1 pair of total some number register simultaneously, and complementation value is assigned to write address pointer register, new sampled data is write in the unit of static memory SRAM of write address pointer register indication, described the second state, whether the value that address pointer register is read in judgement is greater than 0, otherwise without operation, is the value of intermediate value register to be outputed on the address bus of dual port RAM, reads the value of dual port RAM, and subtracts 1 and be then written in dual port RAM.

5. the continuous calculating as claimed in claim 1 device of amplitude probability distribution of counting greatly, is characterized in that, the working method of described static memory SRAM and dual port RAM is write-after-read, and the calculating that completes a point can be controlled in 3 processing clock within the cycle.

6. the continuous calculating as claimed in claim 1 device of amplitude probability distribution of counting greatly, is characterized in that, the computing formula of the preordering method of the average power of the probability in the whole amplitude range of described calculating is:

$\mathrm{Pav}=\underset{i=0}{\overset{2^m-1}{\mathrm{\Σ}}}(i^2*\frac{C_i}{n})$ Or $\mathrm{Pav}=\underset{i=0}{\overset{2^m-1}{\mathrm{\Σ}}}(10\log (i^2/50)*\frac{C_i}{n});$ Wherein, average power is Pav; N is that total statistics is counted; C _ithe statistics number of ordering for i; I is the index of counting.

7. the continuous calculating method of amplitude probability distribution of counting greatly, it is characterized in that, comprise the following steps: set and always count as n, new sampled value is Ai, when number of samples surpasses after n, Ai value indication internal storage location statistics number adds 1, A (i+n) value indication internal storage location statistics number subtracts 1, obtained the corresponding statistics number of range value of a continuous n sampled point, the statistics number that host CPU reads each Ai amplitude point from dual port RAM is again divided by the n that always counts, and just obtains the value of the amplitude probability distribution that continuous n orders.

8. the continuous calculating as claimed in claim 7 method of amplitude probability distribution of counting greatly, is characterized in that, according to count the greatly value of amplitude probability distribution of continuous calculating, calculates the average power of continuous amplitude probability distribution.

9. the continuous calculating as claimed in claim 8 method of amplitude probability distribution of counting greatly, is characterized in that, the computing formula of described average power is:

$\mathrm{Pav}=\underset{i=0}{\overset{2^m-1}{\mathrm{\Σ}}}(i^2*\frac{C_i}{n})$ Or $\mathrm{Pav}=\underset{i=0}{\overset{2^m-1}{\mathrm{\Σ}}}(10\log (i^2/50)*\frac{C_i}{n});$ Wherein, average power is Pav; N is that total statistics is counted; C _ithe statistics number of ordering for i; I is the index of counting.

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