CN103546154A - Bit extending system and bit extending method for analog-to-digital conversion - Google Patents
Bit extending system and bit extending method for analog-to-digital conversion Download PDFInfo
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- CN103546154A CN103546154A CN201210247948.8A CN201210247948A CN103546154A CN 103546154 A CN103546154 A CN 103546154A CN 201210247948 A CN201210247948 A CN 201210247948A CN 103546154 A CN103546154 A CN 103546154A
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Abstract
The invention relates to a bit extending system and a bit extending method for analog-to-digital conversion. The bit extending method mainly comprises the following steps that a signal amplification module amplifies inputted analog signals into various analog amplification signals with gain ratios, a comparator judges whether the various analog amplification signals with the gain ratios exceed a preset voltage range or not; an analog amplification signal which has the highest gain ratio and does not exceed the voltage range is selected to be inputted in an analog-to-digital converter so as to be sampled and quantified into digital data, and the digital data are transferred rightwards according to the corresponding gain ratio. The gain ratio of an amplifier is not required to be adjusted, so that the noise is avoided, and sampling, quantification and judgment on the level of voltage are not required to be finished by the amplifier and can be finished by the comparator of which the cost is much lower than that of the analog-to-digital converter.
Description
Technical field
The present invention is about a kind of bit expanding system of analog digital conversion, and espespecially a kind of overall system architecture is simplified and lower-cost analog digital conversion bit expanding system.
Background technology
Intermediate-freuqncy signal (Intermediate frequency, IF) mainly refer to a signal source through with local oscillator signal smear (mixing) after institute produce, it is mainly for by this signal source raising frequency or be downconverted to specific frequency.After receiving terminal receives, the signal source that must just receive adopts the mode of frequency reducing to be down to after intermediate-freuqncy signal, then carries out signal analysis work.
The electronic installation with information extraction function, as spectrum analyzer etc., in the transmitting procedure of intermediate-freuqncy signal, most likely use an analog-digital converter (Analog to Digital Converter, ADC) by the voltage transitions of analog if signal, be output digital data after power is also quantized, and the crest voltage of input string formula (sinusoidal) waveform for the conversion formula of power is: this formula of P=20 * log (V)+10(is with relative 50ohm system, and V is crest voltage), therefore, the performance number that input voltage value quantizes out with analog-digital converter can become logarithm (logarithm) relation, as shown in Figure 6, in logarithmic curve in figure, can find out, the slope of logarithmic curve reduces with magnitude of voltage and increases, so less signal of magnitude of voltage, its identical voltage difference is after power quantization, the power difference corresponding to is larger, as shown in following form:
| Magnitude of voltage (volt) | Performance number (dBm) |
| V=1 | P=10 |
| V=2 | P=16 |
| V=3 | P=19.5 |
| V=4 | P=22 |
When magnitude of voltage rises to 2 volts by 1 volt, power value difference is 6dB; When magnitude of voltage rises to volt by 2 volts, power difference is 3.5dB; Therefore, if will reduce by linear voltage, be converted to the transformed error that the power of logarithmic axis produces, best mode is exactly on voltage axis, to do the finest and the smoothest quantification, this means that the bit number of analog-digital converter must improve; In addition, avoid using the several values of minimum of voltage Xiang Huahou, because serving as reasons, upper form is known as far as possible, and minimum several magnitudes of voltage can cause larger power difference.
Because the bit number of analog-digital converter output digital data is limited to the height of its sampling frequency, in existing technology, sampling frequency is high to enough analog-digital converters for intermediate frequency sample of signal is quantized, can only export the numerical data of 12 bit to 16 bits at most, and price is all quite expensive.Analog-digital converter with 16 bits, the approximately dynamic range of 16 * 6.02=96.32dB (dynamic range can be provided in theory, and maximum numeral and the minimum digital scope of showing that can tabular form), for the spectrum analyzer that meets 100dB dynamic range for a design, this bit number seems enough, but contrast aforementioned mentioned, the scope of this 96.32dB must all be used, just can provide the dynamic range that approaches 100dB, so must use minimum several voltage quantized value, just can produce larger power difference value at this place, and we can calculate, if maximum power transfer error is set as 0.22dB, must one there is the analog-digital converter of 23 bits just can realize.Therefore proposed a kind of bit expanding system of analog digital conversion now, its cardinal principle is that the little analog signal of magnitude of voltage is first amplified and inputed in analog-digital converter again, four kinds of different multiplying as shown in Figure 6, by analog-digital converter sampling, quantized again, and according to the enlargement ratio several bits of numerical data that move to right, to reach expansion bit, improve precision of measurement.
Refer to Fig. 7, U.S. Patent number the 5th, 844, No. 512 patents of invention (hereinafter to be referred as 512 patents) are an example, this 512 patent is that an analog signal is inputed to an analog-digital converter 82 after amplifier 81 amplifications with a gain adjustable multiplying power, after sampling with the analog signal before the 831 pairs of amplifications of peak detector that are set with a plurality of electric pressures again and quantizing, then with a gain controller 832, according to the electric pressure under quantized value, adjust the gain multiplying power of this amplifier 81; The low person of quantized value grade, increase the gain multiplying power of amplifier 81, the high person of quantized value grade, reduce the gain multiplying power of amplifier 81, please refer to Fig. 8, peak detector 831 and gain controller 832 in the quantized value of analog signal sampling point lower than grade 1(level 1) magnitude of voltage time, the gain multiplying power of this amplifier is adjusted into 8(2
3), when the quantized value of analog signal sampling point is between grade 1 and 2, the gain multiplying power of this amplifier is adjusted into 4(2
2), by that analogy, and by the numerical data of analog-digital converter 82 outputs, the multiplying power according to its corresponding analog input signal amplification moves to right with a bit correction module 84, as amplifies 8 times of persons, 84 of bit correction modules are by numerical data 3 bits that move to right, to record the quantized value before amplify position; So, due to maximum movable 3 bits of numerical data, make numerical data can be used to represent total bit number of quantized value, than the numerical data bit number of in fact analog-digital converter 82 outputs many 3 bits, reach bit expansion and refine and measure the object of precision; But because the bit expanding system of above-mentioned analog digital conversion need be used the amplifier 81 of adjustable gain multiplying power, and the gain multiplying power of amplifier 81 is when change, can produce noise (as whisker-like noise), therefore can reduce the measurement precision of analog-digital converter 82.
For this reason, United States Patent (USP) the 7th, 030, No. 800 patents of invention propose the bit expanding system (hereinafter to be referred as 800 patents) of the analog digital conversion of a kind of multi-channel type as shown in Figure 9, this 800 patent is not used the amplifier of adjustable gain multiplying power, and by analog input signal first after the amplifier 91 of a plurality of fixed gain multiplying powers, input respectively a plurality of analog-digital converters 92 with same interpretation degree bit, with a message selector 93, be connected to the analog-digital converter 92 that overflow (over float) do not occur in bit correction module 94 these message selector 93 judgements again, therefrom select again the corresponding numerical data that is connected to analog-digital converter 92 outputs of the highest amplifier 91 of enlargement ratio, bit number corresponding to the corresponding enlargement ratio of analog-digital converter 92 that 94 foundations of this bit correction module are selected, by these several bit numbers of numerical data gt, so can not use the amplifier of adjustable gain multiplying power, to exempt, adjust the gain noise that multiplying power was caused, but this system needs to use a plurality of analog-digital converters 92, and analog-digital converter 92 always cost of manufacture is high, and there is certain response delay time, therefore when overflow occurs analog-digital converter 92, need could continue to receive analog signal after one period of reaction time of wait, so will make input signal leakage.
The another kind of embodiment of this 800 patent as shown in figure 10 again, its amplifier 95 with a plurality of different gains multiplying powers amplifies an analog signal, and sample and quantize with the analog signal before 96 pairs of amplifications of an analog-digital converter, and, according to the electric pressure (take four kinds of electric pressures as example) under analog-digital converter 96 sampling quantized values, first switch a diverter switch 98 and the amplified analog signal of amplifier 98 outputs of one of them gain multiplying power is inputed to another be used for the analog-digital converter 99 quantizing with an on-off controller 97; Thus, when the magnitude of voltage of this analog signal hour, this diverter switch 98 is switched by the larger analog signal of enlargement ratio and is inputted; When analog signal voltage value is larger, switch by the less analog signal of enlargement ratio and input, can avoid equally the noise that uses adjustable gain multiplying power switched amplifier person to cause because adjusting gain multiplying power, but because this embodiment still needs sampling, quantizes and judge electric pressure, therefore still need to use at least two analog- digital converters 96,99, overall system architecture is also not very simplified, and cost cannot more reduce.
Moreover, above-mentioned peak value detects and gain controller 83, analog- digital converter 82, 96, 99 and the sampling that all needs of on-off controller 97, quantize, the sampling point that makes to answer enlargement ratio for judgement except meeting from be used for the analog-digital converter sampling point of output digital data different, sampling, quantize and the required burst length of diverter switch, more can make two analog-digital converters 96 in analog signal input peak value detection and gain controller 83 and analog-digital converter 82(or 800 patents, 99) time cannot be synchronous, make to postpone judgement cause the displacement number of part numerical data and actual sampling value enlargement ratio inconsistent.
In addition, because amplifier has the restriction of gain duty-cycle, the higher person that gain, its frequency range is generally lower, and as mentioned previously all, if precision will be accurate to 0.22dB person, needs 23 bits, and the bit expanding system that above-mentioned analog digital is changed needs to use 2
9amplifier is doubly expanded 9 bits, and the frequency range of the amplifier of this gain multiplying power does not apply and is used in intermediate-freuqncy signal, therefore the bit expanding system accuracy of above-mentioned analog digital conversion is limited.
In sum, the bit expanding system of early stage analog digital conversion can cause noise to affect measuring accuracy because setting amplifier multiplying power, and still can have because of the analog-digital converter reaction time problem of spillover with the bit expanding system that the mode that multichannel amplifies improves analog digital conversion, and cost increases; And the signal before amplifying is carried out to sample quantification, determine again to gain multiplying power person, still at least need two analog-digital converters, therefore existing bit expanding system than digital translation still needs improvement.
Summary of the invention
Because the technological deficiency that the bit expanding system of above-mentioned analog digital conversion can produce noise, spillover and raise the cost, main purpose of the present invention is for proposing a kind of bit expanding system and bit extended method thereof of analog digital conversion.
Wanting to reach the technical way that above-mentioned purpose used is the bit expanding system that makes this analog digital conversion, and includes:
One signal amplification module, it has an input end of analog signal and a plurality of simulation amplifying signal output, and after the analog signal of this input end of analog signal input is amplified according to multiple different gain multiplying power, by the plurality of simulation amplifying signal output, exported respectively;
One channel diverter switch, it has a plurality of inputs, an output and switches control end, and a plurality of inputs of this channel diverter switch are connected with a plurality of simulation amplifying signal outputs of this signal amplification module respectively, and the wherein input and this output conducting that supply switching channels diverter switch;
One analog-digital converter, it has an input and an output, and the input of this analog-digital converter is connected with the output of this channel diverter switch, and the output of this analog-digital converter is exported a numerical data;
One bit correction module, it is connected with the output of this analog-digital converter, and by the numerical data of this analog-digital converter output a plurality of bit numbers that move to right;
One channel selector, it is connected with a plurality of simulation amplifying signal outputs of this signal amplification module and the switching controls end of this channel diverter switch, and be set with a voltage range, with the more the plurality of simulation amplifying signal of comparator output output voltage, whether surpass this voltage range, and switch the switching controls end of this channel diverter switch, the highest and the output voltage of the multiplying power that makes to gain is no more than simulation amplifying signal output and this analog-digital converter conducting of this voltage range, and sets according to selected gain multiplying power the bit number that this bit correction module moves to right.
Because the present invention does not use the adjustable signal amplification module of gain multiplying power, therefore can not cause noise because adjusting gain multiplying power, and whether the present invention judges the multiplying power that should gain over voltage range with the output voltage of the analog signal after relatively amplifying, do not need to set a plurality of electric pressures, do not need sampling yet, quantize and computing judgement electric pressure, be able to cost and compare the comparison that the cheap a lot of comparator of analog-digital converter completes voltage range, therefore the present invention is able to do not adding under the prerequisite of cost of manufacture, improve the bit expanding system erroneous judgement of existing analog digital conversion and the defect of spillover.
Again, in view of be subject to the gaining restriction of duty-cycle of the expansion bit number (being available amplifier maximum gain multiplying power) of the bit expanding system of above-mentioned analog digital conversion, another object of the present invention is in order further to improve the restriction of the bit expanding system expansion bit number of analog digital conversion, therefore make above-mentioned signal amplification module include the amplifier of a plurality of grades of serial connections, and connect this input end of analog signal with the input of first order amplifier, and using the output of amplifiers at different levels as the plurality of simulation amplifying signal output, make the amplifier of a plurality of grades of low gain multiplying powers of analog signal process amplify to reach high-gain multiplying power, to improve the highest-gain multiplying power (expanding bit number) of system under the prerequisite in taking into account amplifier frequency range, to improve precision of measurement.
Another object of the present invention, for the judgement time of channel selector and the effect of the actual arrival of analog signal analog-digital converter time synchronized are further provided, and a delay filter is set respectively between each simulation amplifying signal output and input corresponding to this channel diverter switch, and each delay filter transfers to this channel selector required time by simulation amplifying signal from this signal amplification module and is set as transmission line time of delay, and by channel selector comparative voltage scope and complete and switch this channel diverter switch required time and be set as an operating time, and inputted simulation amplifying signal is postponed to export after this transmission line time of delay and this operating time, so can guarantee the judged result of this channel selector and the time synchronized of the actual input of simulation amplifying signal analog-digital converter, further reduce the erroneous judgement causing because postponing judgement.
Wanting to reach the technical way that above-mentioned purpose used is to make the bit extended method of the bit expanding system of this analog digital conversion include following steps:
Receive an analog signal;
This analog signal is zoomed into a plurality of simulation amplifying signals through different gains multiplying power;
Whether the voltage of more the plurality of simulation amplifying signal surpasses a default voltage range;
Select gain multiplying power maximum and voltage to be no more than the simulation amplifying signal input analog-digital converter of this predeterminated voltage scope, and sample and quantize rear output one numerical data;
According to the corresponding bit number of enlargement ratio of simulation amplifying signal of input analog-digital converter, and by this numerical data this bit number that moves to right.
So be able to the gain multiplying power that mode that whether comparison output voltage surpass predeterminated voltage scope determines analog digital data, except not needing to adjust gain multiplying power, to avoid noise to produce, also can remove the step of sampling, quantification and electric pressure judgement from, and be able to cost and compare the cheap a lot of comparator of analog-digital converter and reach, reduce cost of manufacture.
Accompanying drawing explanation
Fig. 1 is circuit box schematic diagram of the present invention.
Fig. 2 is the circuit diagram of Fig. 1 channel selector.
Fig. 3 is the circuit diagram of Fig. 1 delay filter.
Fig. 4 is the flow chart of steps of bit extended method of the present invention.
Fig. 5 is the bit displacement diagram of Fig. 1 bit correction module.
Fig. 6 is the curve chart of digital analog converter changing voltage and power.
Fig. 7 is the circuit box schematic diagram of the bit expanding system of existing a kind of analog digital conversion.
Fig. 8 is the detection of Fig. 7 peak value and gain controller and the schematic diagram of analog-digital converter to the sampling point of analog signal.
Fig. 9 is the circuit box schematic diagram of the bit expanding system of existing another kind of analog digital conversion.
Figure 10 is the circuit box schematic diagram of the bit expanding system of existing another analog digital conversion.
Embodiment
Below coordinate preferred embodiment graphic and of the present invention, further setting forth the present invention is to reach the technological means that predetermined goal of the invention is taked.
Refer to Fig. 1, the bit expanding system of analog digital conversion of the present invention includes:
One signal amplification module 10, it has an input end of analog signal and a plurality of simulation amplifying signal output 11, and after the analog signal of this input end of analog signal input is amplified according to multiple different gain multiplying power, by the plurality of simulation amplifying signal output, exported respectively, in the present embodiment, this signal amplification module 10 includes the amplifier 12 of a plurality of grades of fixed gain multiplying powers and serial connection, input with first order amplifier connects this input end of analog signal, and usings the output of amplifiers at different levels as the plurality of simulation amplifying signal output 11;
One channel diverter switch 20, it has a plurality of inputs, an output and switches control end 21, and a plurality of inputs of this channel diverter switch 20 are connected with a plurality of simulation amplifying signal outputs 11 of this signal amplification module 10 respectively, this switching controls end 21 is for a wherein input and this output conducting of switching channels diverter switch;
One analog-digital converter 30, it has an input and an output, and the input of this analog-digital converter 30 is connected with the output of this channel diverter switch 20, and the output of this analog-digital converter 30 is exported a numerical data;
One bit correction module 40, it is connected with the output of this analog-digital converter 30, with a plurality of bit numbers that the numerical data of these analog-digital converter 30 outputs is moved to right, in the present embodiment, this bit correction module 40 has a checking linearity unit 41 and a bit displacement unit 42, this checking linearity unit 41 is according to the quantized value of (Look-up table) interpretation analog-digital converter 30 output digital data representatives of tabling look-up on, and 42 of this bit displacement units are by the numerical data output after a plurality of bits (dwindling quantized value according to gain multiplying power) that moves to right;
One channel selector 50, it is connected with a plurality of simulation amplifying signal outputs 11 of this signal amplification module 10 and the switching controls end 21 of this channel diverter switch, and be set with a voltage range, and whether surpass this voltage range with the more the plurality of simulation amplifying signal of comparator output output voltage, and switch the switching controls end 21 of this channel diverter switch 20, the highest and the output voltage of the multiplying power that makes to gain is no more than the simulation amplifying signal output 11 and these analog-digital converter 30 conductings of this voltage range, and set the move to right bit number of numerical data of this bit correction module 40 according to selected gain multiplying power:
A plurality of delay filters 70, it is connected between the input that the plurality of simulation amplifying signal output 11 is corresponding with channel diverter switch 20, and simulation amplifying signal is transferred to these channel selector 50 required times from this signal amplification module 10 and be set as transmission line time of delay, and by channel selector 50 comparative voltage scopes and complete and switch these channel diverter switch 20 required times and be set as an operating time, and inputted simulation amplifying signal is postponed to export after this transmission line time of delay and this operating time, please further coordinate and consult Fig. 3, because above-mentioned transmission line time of delay and operating time can be estimated go out, therefore each delay filter 70 can a plurality of inductance 71 and electric capacity 72 connection in series-parallel form, be its time of delay
Please further coordinate and consult Fig. 2, this channel selector 50 includes a plurality of voltage range identifying units 51 and an encoder 52, the plurality of voltage range identifying unit 51 is connected to a reference voltage source 60 that provides high and low critical voltage value, and be connected to respectively the plurality of simulation amplifying signal output 11, and include two comparators 53 and a NOR gate 54(NOR Gate), the output of this two comparator 53 is connected to this NOR gate 54, and wherein the backward end of a comparator 53 is connected to the high critical voltage V that this reference voltage source 60 provides
h, and forward end is connected to corresponding simulation amplifying signal output 11, another comparator 53 is connected to forward end the low critical voltage V that this reference voltage source 60 provides
l, and backward end is connected to corresponding simulation amplifying signal output 11, the output of this NOR gate 54 is connected to this encoder 52, in corresponding simulation amplifying signal output 11 output voltages between this high and low critical voltage V
h, V
lset voltage range time, make this NOR gate 54 output high potentials, higher than this high critical voltage V
hor lower than this low critical voltage V
ltime, make this NOR gate 54 output 0 current potentials, this encoder 52 is after the high potential or 0 current potential of 51 outputs of receiver voltage scope identifying unit, the digital coding that output one represent that corresponding gain multiplying power is the highest and exports high-potential voltage scope identifying unit 51 is given this switching controls end 21, to switch the output of this channel diverter switch 20 and this gain multiplying power is the highest and be no more than high and low critical voltage V through voltage range identifying unit 51
h, V
lthe conducting of simulation amplifying signal output, in the present embodiment, be that to take three voltage range identifying units 51 be example, and the voltage range identifying unit 51 that is 1 by corresponding amplifier gain multiplying power is set as " 01 " digital coding; The 4 power persons that gain multiplying power is 2 are set as " 10 "; 5 powers (multiplying power that in fact gains has been 2 the 9 powers) person that gain multiplying power is 2 is set as " 11 "; When three voltage range identifying units 51 are all exported high potential, this encoder 52 can output " 11 " control simulation amplifying signal and the output conducting of 9 powers that channel diverter switch 20 handoff gain multiplying powers are 2; If voltage range identifying unit 51 output 0 current potentials of 5 powers that corresponding gain multiplying power is 2 gain, multiplying power is the voltage range identifying unit 51 output high potentials of 24 powers, encoder 52 outputs " 10 ", make to amplify the simulation amplifying signal output 11 and the 20 output conductings of channel diverter switch of 24 powers, the rest may be inferred, therefore this encoder 52 uses gate to reach.
Again, the amplifier 12 that this signal amplification module 10 of the present embodiment comprises three serial connections, is used the amplifier serial connection of low range to reach the effect of high magnification, and make, the gain multiplying power of first order amplifier is wherein 1, the gain multiplying power of second level amplifier is 2
4, the third level is 2
5person, the amplifier 12 gain multiplying powers of last progression can reach 2
9doubly, expanded 9 bits, be used in conjunction with the analog-digital converter of exportable 14 to 16 bit numerical datas, total bit number just can arrive 23 to 25 bits, so that the measurement precision of low-voltage analog signal is accurate to 0.22dB, has high precision.
Please further coordinate and consult Fig. 4, the bit extended method of the bit expanding system of analog digital conversion of the present invention includes following steps:
Receive an analog signal S11;
This analog signal is zoomed into a plurality of simulation amplifying signal S12 through different gains multiplying power;
Whether the voltage of more the plurality of simulation amplifying signal surpasses a default voltage range S13, and in the present embodiment, this voltage range comprises a high critical voltage value and a low critical voltage value, and analog signal and the defeated V of a high critical voltage
henter a comparator 53, and relatively this analog signal whether higher than this high critical voltage value; And this analog signal and a low critical voltage V
linput another comparator 53, and relatively this analog signal whether lower than this low critical voltage value;
Select gain multiplying power maximum and voltage to be no more than the simulation amplifying signal input analog-digital converter 30 of this predeterminated voltage scope, and sample and quantize rear output one numerical data S14;
According to the corresponding bit number of enlargement ratio of input analog-digital converter 30 simulation amplifying signals, and this numerical data this bit that moves to right is counted to S15.
Please further consult again Fig. 5, it is example that the present embodiment be take the numerical data that the analog digital data of 14 bits is expanded to 23bit, when to switch by gain multiplying power be the analog signal input analog-digital converter 30 of 1 times, the analog signal voltage value of representative input is at present enough large, and the numerical data of 14 bits enough precise quantification input at present analog signal, therefore amplified analog signal not, this bit correction module 40 does not also carry out displacement to the numerical data of these analog-digital converter 30 outputs, and its numerical data is filled into 0 bit of 9 bits, fill the binary bit quantized value of 23 bit numbers, in like manner, when switching by gain multiplying power, be 2
4when analog signal is doubly inputted analog-digital converter 30, represent that the analog signal voltage value of input need to amplify 2 at present
4doubly, be just enough to this analog signal of numerical data precise quantification of 14 bits, therefore analog signal is amplified to 2
4doubly, and by bit correction module 40 numerical data 4 bits of analog-digital converter 30 outputs that move to right, and fill into 0 bit of 5 bits, in like manner, when switching by gain multiplying power, be 2
5doubly (actually amplify totally 2
9during analog signal input analog-digital converter 30 doubly), represent that analog signal need amplify 2
9doubly, and the move to right numerical data 9 bit numbers of analog-digital converter 30 outputs of this bit correction module 40, reach the effect that the analog-digital converter of output 14 bit numerical datas is expanded to 23 bits.
In sum, the present invention does not use the adjustable amplifier of gain multiplying power, avoid beyond noise generation, again with the voltage that judges the simulation amplifying signal after multiple gain multiplying power is amplified whether within the scope of predeterminated voltage, therefore can directly make comparisons and so reach with height critical voltage by the low comparator of cost again, integral body is only used an analog-digital converter, more without the expensive defect that again still can spillover of the bit expanding system of multi-channel type analog digital conversion; And the present invention also makes channel selector judge the time of result and the time synchronized of the actual arrival of simulation amplifying signal analog-digital converter, further got rid of again and postponed the erroneous judgement that judgement causes, moreover, the present invention makes again overall gain multiplying power not be subject to the restriction of the gain duty-cycle of amplifier, make the bit expanding system of analog digital conversion can extend to 23 to 25 bits, there is pinpoint accuracy.
The above is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, yet not in order to limit the present invention, any those skilled in the art, within not departing from the scope of technical solution of the present invention, when can utilizing the technology contents of above-mentioned announcement to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be the content that does not depart from technical solution of the present invention, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (8)
1. a bit expanding system for analog digital conversion, is characterized in that, this bit expanding system includes:
One signal amplification module, it has an input end of analog signal and a plurality of simulation amplifying signal output, and after the analog signal of this input end of analog signal input is amplified according to multiple different gain multiplying power, by the plurality of simulation amplifying signal output, exported respectively;
One channel diverter switch, it has a plurality of inputs, an output and switches control end, and a plurality of inputs of this channel diverter switch are connected with a plurality of simulation amplifying signal outputs of this signal amplification module respectively, this switching controls end is for a wherein input and the output conducting of switching channels diverter switch;
One analog-digital converter, it has an input and an output, and the input of this analog-digital converter is connected with the output of this channel diverter switch, and the output of this analog-digital converter is exported a numerical data;
One bit correction module, it is connected with the output of this analog-digital converter, and by the numerical data of this analog-digital converter output a plurality of bit numbers that move to right;
One channel selector, it is connected with a plurality of simulation amplifying signal outputs of this signal amplification module and the switching controls end of this channel diverter switch, and be set with a voltage range, with the more the plurality of simulation amplifying signal of comparator output output voltage, whether surpass this voltage range, and switch the switching controls end of this channel diverter switch, the highest and the output voltage of the multiplying power that makes to gain is no more than simulation amplifying signal output and this analog-digital converter conducting of this voltage range, and sets according to selected gain multiplying power the bit number that this bit correction module moves to right.
2. the bit expanding system that analog digital according to claim 1 is changed, it is characterized in that, this signal amplification module includes the amplifier of a plurality of grades of fixed gain multiplying powers and serial connection, and connect this input end of analog signal with the input of first order amplifier, and using the output of amplifiers at different levels as the plurality of simulation amplifying signal output.
3. the bit expanding system that analog digital according to claim 1 and 2 is changed, it is characterized in that, the bit expanding system of this analog digital conversion arranges respectively a delay filter between each simulation amplifying signal output and input corresponding to this channel diverter switch, and each delay filter transfers to this channel selector required time by simulation amplifying signal from this signal amplification module and is set as transmission line time of delay, and by channel selector comparative voltage scope and complete and switch this channel diverter switch required time and be set as an operating time, and inputted simulation amplifying signal is postponed to export after this transmission line time of delay and this operating time.
4. the bit expanding system of analog digital conversion according to claim 1 and 2, is characterized in that, this channel selector includes:
A plurality of voltage range identifying units, it is connected to one and provides high, the reference voltage source of low critical voltage value, and be connected to respectively the plurality of simulation amplifying signal output, and include two comparators and a NOR gate, the output of this two comparator is connected to this NOR gate, and wherein the backward end of a comparator is connected to the high critical voltage that this reference voltage source provides, and forward end is connected to corresponding simulation amplifying signal output, another comparator is connected to forward end the low critical voltage that this reference voltage source provides, and backward end is connected to corresponding simulation amplifying signal output, with the simulation amplifying signal output output voltage in corresponding between this height, during voltage range that low critical voltage sets, make this NOR gate output high potential, during higher than this high critical voltage or lower than this low critical voltage, make this NOR gate export 0 current potential, and
One encoder, it is connected with the output of the plurality of voltage range identifying unit NOR gate, and after the high potential or 0 current potential of the output of receiver voltage scope identifying unit, the digital coding that output one represent that corresponding gain multiplying power is the highest and exports high-potential voltage scope identifying unit is given this switching controls end, to switch the output of this channel diverter switch and this gain multiplying power is the highest and be no more than the simulation amplifying signal output conducting of high and low critical voltage through voltage range identifying unit.
5. the bit expanding system of analog digital conversion according to claim 3, is characterized in that, this channel selector includes:
A plurality of voltage range identifying units, it is connected to one and provides high, the reference voltage source of low critical voltage value, and be connected to respectively the plurality of simulation amplifying signal output, and include two comparators and a NOR gate, the output of this two comparator is connected to this NOR gate, and wherein the backward end of a comparator is connected to the high critical voltage that this reference voltage source provides, and forward end is connected to corresponding simulation amplifying signal output, another comparator is connected to forward end the low critical voltage that this reference voltage source provides, and backward end is connected to corresponding simulation amplifying signal output, the output of this NOR gate is connected to this encoder, in corresponding simulation amplifying signal output output voltage between this height, during voltage range that low critical voltage sets, make this NOR gate output high potential, during higher than this high critical voltage or lower than this low critical voltage, make this NOR gate export 0 current potential, and
One encoder, it is connected with the output of the plurality of voltage range identifying unit NOR gate, and after the high potential or 0 current potential of the output of receiver voltage scope identifying unit, the digital coding that output one represent that corresponding gain multiplying power is the highest and exports high-potential voltage scope identifying unit is given this switching controls end, to switch the output of this channel diverter switch and this gain multiplying power is the highest and be no more than the simulation amplifying signal output conducting of high and low critical voltage through voltage range identifying unit.
6. the bit expanding system of analog digital conversion according to claim 5, is characterized in that, each delay filter comprises a plurality of inductance and electric capacity connection in series-parallel.
7. a bit extended method for the bit expanding system of analog digital conversion, is characterized in that, comprises following steps:
Receive an analog signal;
This analog signal is zoomed into a plurality of simulation amplifying signals through different gains multiplying power;
Whether the voltage of more the plurality of simulation amplifying signal surpasses a default voltage range;
Select gain multiplying power maximum and voltage to be no more than the simulation amplifying signal input analog-digital converter of this predeterminated voltage scope, and sample and quantize rear output one numerical data;
According to the corresponding bit number of enlargement ratio of input analog-digital converter simulation amplifying signal, and by this numerical data this bit number that moves to right.
8. the bit extended method of the bit expanding system that analog digital according to claim 7 is changed, it is characterized in that, whether the voltage of aforementioned more the plurality of simulation amplifying signal surpasses in the step of this voltage range, this voltage range comprises a high critical voltage value and a low critical voltage value, and analog signal and a high critical voltage are inputted a comparator, and relatively this analog signal whether higher than this high critical voltage value; And this analog signal and a low critical voltage are inputted another comparator, and relatively this analog signal whether lower than this low critical voltage value.
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