CN103545416A - Substrate of light-emitting diode and die bonding method of light-emitting diode - Google Patents
Substrate of light-emitting diode and die bonding method of light-emitting diode Download PDFInfo
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- CN103545416A CN103545416A CN201210258117.0A CN201210258117A CN103545416A CN 103545416 A CN103545416 A CN 103545416A CN 201210258117 A CN201210258117 A CN 201210258117A CN 103545416 A CN103545416 A CN 103545416A
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- emitting diode
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- backlight unit
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- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000000919 ceramic Substances 0.000 claims abstract description 36
- 239000000463 material Substances 0.000 claims abstract description 35
- 230000005496 eutectics Effects 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000004642 Polyimide Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 4
- 239000007769 metal material Substances 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 24
- 238000012545 processing Methods 0.000 description 6
- 238000012797 qualification Methods 0.000 description 6
- 230000003139 buffering effect Effects 0.000 description 4
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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- Led Device Packages (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
Abstract
The invention discloses a substrate of a light-emitting diode and a die bonding method of the light-emitting diode. The substrate of the light emitting diode comprises a first ceramic plate, a buffer material layer, a conductive layer and a second ceramic plate. The buffer material layer is located on the first ceramic plate. The conductive layer is located on the buffer material layer and has a die bonding region of a light emitting diode. The second ceramic plate is positioned on the conducting layer and is provided with an opening region for exposing the die bonding region of the conducting layer. The substrate of the light emitting diode can be applied to a die bonding method of the light emitting diode using a eutectic layer.
Description
Technical field
The invention relates to a kind of die-bonding method of light-emitting diode, and particularly relevant for a kind of die-bonding method of light-emitting diode and substrate of use thereof that uses Eutectic Layer.
Background technology
By light-emitting diode chip for backlight unit die bond, the method on substrate is a lot of at present, and more common mode is to use some glue mode by after the bottom surface gluing of light-emitting diode chip for backlight unit, then is adhered to the die bond region on substrate.Even if this kind of mode applied the production equipment of automation, after light-emitting diode chip for backlight unit is adhered on substrate, just can descend one step after also needing to wait for adhesive curing, so the production capacity of die bond step promotes and is difficult for.The method of other a large amount of light-emitting diode chip for backlight unit of die bond, what have is not yet ripe, and some qualification rates are too low, therefore all not yet become the main way of a large amount of light-emitting diode chip for backlight unit of die bond.In view of this, how light-emitting diode production technology is badly in need of the excellent process of a large amount of light-emitting diode chip for backlight unit of die bond, to promote the overall throughput of light-emitting diode.
Summary of the invention
Therefore, an object of the present invention is that a kind of die-bonding method of improveing the substrate of light-emitting diode and using this substrate is being provided.
According to the object of the invention described above, a kind of substrate of light-emitting diode is provided, it comprises the first ceramic wafer, cushioned material layer, conductive layer and the second ceramic wafer.Cushioned material layer is positioned on the first ceramic wafer.Conductive layer is positioned in cushioned material layer, and conductive layer has the die bond region of a light-emitting diode.The second ceramic wafer is positioned on conductive layer, and it has an open area so as to exposing the die bond region of conductive layer.
According to another embodiment of the present invention, the flush that die bond region does not contact with conductive layer with the second ceramic wafer in fact.
According to another embodiment of the present invention, the material of conductive layer is metal material.
According to another embodiment of the present invention, cushioned material layer is a polyimide layer.
According to the object of the invention described above, a kind of die-bonding method of light-emitting diode is provided, it comprises following steps.One substrate is provided, and it from bottom to top sequentially comprises one first ceramic wafer, a cushioned material layer, a conductive layer and one second ceramic wafer, and the second ceramic wafer has a plurality of open areas so as to exposing a plurality of die bonds region of conductive layer.Place a plurality of light-emitting diode chip for backlight unit respectively at those die bond regions on conductive layer, wherein the bottom surface of each light-emitting diode chip for backlight unit has an Eutectic Layer to contact with each die bond region.Cut the second ceramic wafer and conductive layer between wantonly two adjacent light-emitting diode chip for backlight unit, to leave a plurality of Cutting Roads in cushioned material layer.Use a heat block to be pressed on those light-emitting diode chip for backlight unit down simultaneously, each Eutectic Layer of those light-emitting diode chip for backlight unit is solidified respectively on those die bond regions of conductive layer.
According to another embodiment of the present invention, the temperature of heat block is greater than the eutectic temperature of Eutectic Layer.
According to another embodiment of the present invention, Eutectic Layer is a pair of metal mixed layer.
According to another embodiment of the present invention, Eutectic Layer is a gold medal, tin mixed layer.
According to another embodiment of the present invention, the material of conductive layer is metal material.
According to another embodiment of the present invention, cushioned material layer is a polyimide layer.
From the above, apply the buffer capacity substrate that has of the present invention, when using heat block to apply pressure to many light-emitting diode chip for backlight unit simultaneously, cushioned material layer in substrate provides the stressed buffering of required stress or position when excessive, and avoid excessive the caused chip of lower compression damaged or other cause the situation of the low qualification rate of eutectic processing procedure, make the qualification rate of the die bond processing procedure of a large amount of light-emitting diode chip for backlight unit can promote many.
Accompanying drawing explanation
For above and other object of the present invention, feature, advantage and embodiment can be become apparent, appended graphic being described as follows:
Fig. 1 illustrates a kind of light-emitting diode die bond according to one embodiment of the invention profile on substrate;
Fig. 2 illustrates a kind of light-emitting diode die bond according to another embodiment of the present invention profile on substrate;
Fig. 3 illustrates a kind of light-emitting diode die bond according to further embodiment of this invention profile on substrate;
Fig. 4 A～4D is each step generalized section illustrating according to a kind of crystal solidifying method of light-emitting diode of one embodiment of the invention.
[main element symbol description]
100 substrates
102 first ceramic wafers
104 cushioned material layer
106 conductive layers
106a die bond region
106b region
106c region
108 second ceramic wafers
108a open area
108b surface
110 light-emitting diode chip for backlight unit
110a Eutectic Layer
110 ' light-emitting diode chip for backlight unit
110 " light-emitting diode chip for backlight unit
200 substrates
202 second ceramic wafers
204 cushioned material layer
206 conductive layers
206a die bond region
208 second ceramic wafers
208a open area
210 light-emitting diode chip for backlight unit
210a Eutectic Layer
212 Cutting Roads
220 heat blocks
Embodiment
Please refer to Fig. 1, it illustrates a kind of light-emitting diode chip for backlight unit die bond according to one embodiment of the invention profile on substrate.Substrate 100 comprises the first ceramic wafer 102, cushioned material layer 104, conductive layer 106 and the second ceramic wafer 108, and utilizes laminated mode of burning altogether by above-mentioned each layer, the plate formation substrate that is fixed together.Cushioned material layer 104 is positioned on the first ceramic wafer 102, required stress or the buffering of position when light-emitting diode chip for backlight unit 110 die bond to be provided.In the present embodiment, cushioned material layer 104 can be the padded coaming of polyimide layer or other materials.Conductive layer 106 is positioned in cushioned material layer 104, and has the die bond region 106a of a light-emitting diode chip for backlight unit 110.In the present embodiment, conductive layer 106 is preferably a metal level, can be adhered on the conductive layer 106 of metal for the Eutectic Layer 110a of light-emitting diode chip for backlight unit 110 bottom surfaces.If light-emitting diode chip for backlight unit is not adhered on conductive layer 106 in eutectic mode, conductive layer 106 can be just nonmetallic conductive layer.In the present embodiment, die bond region 106a is the region of a protrusion conductive layer 106, and the surperficial 108b not contacting with conductive layer 106 with the second ceramic wafer 108 in fact flushes.The second ceramic wafer 108 being positioned on conductive layer 106 need have an open area 108a, so as to exposing the die bond region 106a of conductive layer 106.In other embodiments, die bond region also can flat site, and does not flush with the surperficial 108b of the second ceramic wafer 108.In addition, die bond region 106a is divided into two region (106b insulated from each other; 106c), two electrodes for light-emitting diode chip for backlight unit 110 are electrically connected respectively.In the present embodiment, a wherein electrode of light-emitting diode chip for backlight unit 110 is directly connected in the region 106b of die bond region 106a, and another electrode is connected in another region 106c of die bond region 106a with wire.
Please refer to Fig. 2, it illustrates a kind of light-emitting diode chip for backlight unit die bond according to another embodiment of the present invention profile on substrate.The embodiment that the embodiment of Fig. 2 is different from Fig. 1 is the kind of light-emitting diode chip for backlight unit.In the embodiment of Fig. 2, light-emitting diode chip for backlight unit 110 ' is to cover brilliant mode to be adhered to die bond region 106a upper, and in other words, two electrodes of light-emitting diode chip for backlight unit 110 ' are directly connected in the two region (106b insulated from each other of die bond region 106a; 106c).
Please refer to Fig. 3, it illustrates a kind of light-emitting diode chip for backlight unit die bond according to further embodiment of this invention profile on substrate.The embodiment that the embodiment of Fig. 3 is different from Fig. 1, Fig. 2 is also the kind of light-emitting diode chip for backlight unit.In the embodiments of figure 3, light-emitting diode chip for backlight unit 110 " two electrodes be with wire, to be connected to respectively the two region (106b insulated from each other of die bond region 106a; 106c).
Please refer to Fig. 4 A～4D, it illustrates each step generalized section according to a kind of crystal solidifying method of light-emitting diode of one embodiment of the invention.
In the step of Fig. 4 A, one substrate 200 is provided, it from bottom to top sequentially comprises the first ceramic wafer 202, cushioned material layer 204, conductive layer 206 and the second ceramic wafer 208, and the second ceramic wafer 208 has a plurality of open area 208a so as to exposing a plurality of die bonds region 206a of conductive layer 206.Substrate 200 is not yet cut apart before light-emitting diode chip for backlight unit 210 die bonds, so as to for many light-emitting diode chip for backlight unit 210 together die bond on substrate 200.In the present embodiment, the Eutectic Layer 210a that has of light-emitting diode chip for backlight unit 210 bottom surfaces is adhered on conductive layer 206.Eutectic Layer 210a is the layer of metal mixed more than (being generally bimetallic mixed layer), for example, can be a gold medal, tin mixed layer.When Eutectic Layer 210a is heated higher than its eutectic temperature, Eutectic Layer 210a can melt and solidify rapidly, to reach, light-emitting diode chip for backlight unit 210 is adhered to rapidly to the object on conductive layer 206.In the present embodiment, conductive layer 206 is preferably a metal level, can be adhered on the conductive layer 206 of metal for the Eutectic Layer 210a of light-emitting diode chip for backlight unit 210 bottoms.
In the step of Fig. 4 B, a plurality of light-emitting diode chip for backlight unit 210 are positioned on corresponding die bond region 206a.The Eutectic Layer 210a contact die bond region 206a of each light-emitting diode chip for backlight unit 210.
In the step of Fig. 4 C, cut the second ceramic wafer 208 and conductive layer 206 between wantonly two adjacent light-emitting diode chip for backlight unit 210, to leave a plurality of Cutting Roads 212 in cushioned material layer 204.In other words, the cushioned material layer 204 of substrate is that maintenance is connected and is not cut with the first ceramic wafer 202.
In the step of Fig. 4 D, use a heat block 220 to be pressed on light-emitting diode chip for backlight unit 210 down simultaneously, make the Eutectic Layer 210a of those light-emitting diode chip for backlight unit 210 melt and solidify on the corresponding die bond region 206a of conductive layer 206.In this step, the temperature of heat block 220 should be greater than the eutectic temperature of Eutectic Layer 210a, just can make Eutectic Layer 210a reach the object of fusing.When heat block 220 is pressed on down on light-emitting diode chip for backlight unit 210 simultaneously, because of the lower surface tolerance of heat block 220, the factors such as variable thickness of light-emitting diode chip for backlight unit 210, when being pressed down, may cause heat block 220 some light-emitting diode chip for backlight unit 210 to press down unbalanced stress or the situation such as heat block is contactless.Now, cushioned material layer 204 just can provide light-emitting diode chip for backlight unit 210 the stressed buffering of required stress or position when excessive, and avoid chip that lower compression is excessive caused damaged or other cause the situation of the low qualification rate of eutectic processing procedure.In the present embodiment, cushioned material layer 204 can be the padded coaming of polyimide layer or other materials.
This case is because being conceived to the die bond improved process for making of light-emitting diode chip for backlight unit, and the successive process steps after die bond (steps such as substrate cut, routing or encapsulation) is to use known processing procedure, at this, just repeats no more.
From the invention described above execution mode, apply the substrate with buffer capacity of the present invention, when using heat block to apply pressure to many light-emitting diode chip for backlight unit simultaneously, cushioned material layer in substrate provides the stressed buffering of required stress or position when excessive, and avoid excessive the caused chip of lower compression damaged or other cause the situation of the low qualification rate of eutectic processing procedure, make the qualification rate of the die bond processing procedure of a large amount of light-emitting diode chip for backlight unit can promote many.
Although the present invention discloses as above with execution mode; so it is not in order to limit the present invention; anyly be familiar with this skill person; without departing from the spirit and scope of the present invention; when being used for a variety of modifications and variations, so the scope that protection scope of the present invention ought define depending on appending claims is as the criterion.
Claims (10)
1. a substrate for light-emitting diode, is characterized in that, comprises:
One first ceramic wafer;
One cushioned material layer, is positioned on this first ceramic wafer;
One conductive layer, is positioned in this cushioned material layer, and this conductive layer has the die bond region of a light-emitting diode; And
One second ceramic wafer, is positioned on this conductive layer, and it has an open area so as to exposing this die bond region of this conductive layer.
2. the substrate of light-emitting diode according to claim 1, is characterized in that, the flush that this die bond region does not contact with this conductive layer with this second ceramic wafer.
3. the substrate of light-emitting diode according to claim 1, is characterized in that, the material of this conductive layer is metal material.
4. the substrate of light-emitting diode according to claim 1, is characterized in that, this cushioned material layer is a polyimide layer.
5. a die-bonding method for light-emitting diode, is characterized in that, comprises:
One substrate is provided, and it from bottom to top sequentially comprises one first ceramic wafer, a cushioned material layer, a conductive layer and one second ceramic wafer, and this second ceramic wafer has a plurality of open areas so as to exposing a plurality of die bonds region of this conductive layer;
Place a plurality of light-emitting diode chip for backlight unit respectively at those die bond regions on this conductive layer, wherein the bottom surface of each this light-emitting diode chip for backlight unit has an Eutectic Layer to contact with each this die bond region;
Cut this second ceramic wafer and this conductive layer between wantonly two adjacent these light-emitting diode chip for backlight unit, to leave a plurality of Cutting Roads in this cushioned material layer; And
Use a heat block to be pressed on those light-emitting diode chip for backlight unit down simultaneously, respectively this Eutectic Layer of those light-emitting diode chip for backlight unit is solidified respectively on those die bond regions of this conductive layer.
6. the die-bonding method of light-emitting diode according to claim 5, is characterized in that, the temperature of this heat block is greater than the eutectic temperature of this Eutectic Layer.
7. the die-bonding method of light-emitting diode according to claim 5, is characterized in that, this Eutectic Layer is a pair of metal mixed layer.
8. the die-bonding method of light-emitting diode according to claim 7, is characterized in that, this Eutectic Layer is a gold medal, tin mixed layer.
9. the die-bonding method of light-emitting diode according to claim 5, is characterized in that, the material of this conductive layer is a metal material.
10. the die-bonding method of light-emitting diode according to claim 5, is characterized in that, this cushioned material layer is a polyimide layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101124791A TW201403892A (en) | 2012-07-10 | 2012-07-10 | LED substrate and LED die-bonding method using the substrate |
| TW101124791 | 2012-07-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103545416A true CN103545416A (en) | 2014-01-29 |
| CN103545416B CN103545416B (en) | 2016-12-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210258117.0A Active CN103545416B (en) | 2012-07-10 | 2012-07-24 | Die bonding method of light emitting diode |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103545416B (en) |
| TW (1) | TW201403892A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101097978A (en) * | 2007-06-26 | 2008-01-02 | 上海大学 | Copper inter-linkage flip-chip LED and its preparing process |
| US20090017566A1 (en) * | 2007-07-09 | 2009-01-15 | Philips Lumileds Lighting Company Llc | Substrate Removal During LED Formation |
| CN101414652A (en) * | 2007-10-17 | 2009-04-22 | 叶秀慧 | Package structure for LED and preparation method thereof |
| TW201025670A (en) * | 2008-12-29 | 2010-07-01 | Denki Kagaku Kogyo Kk | Manufacturing process of a substrate for packaging light-emitting device and light-emitting device packaging |
| US20110204408A1 (en) * | 2007-08-22 | 2011-08-25 | Photonstar Led Limited | High thermal performance packaging for optoelectronics devices |
-
2012
- 2012-07-10 TW TW101124791A patent/TW201403892A/en unknown
- 2012-07-24 CN CN201210258117.0A patent/CN103545416B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101097978A (en) * | 2007-06-26 | 2008-01-02 | 上海大学 | Copper inter-linkage flip-chip LED and its preparing process |
| US20090017566A1 (en) * | 2007-07-09 | 2009-01-15 | Philips Lumileds Lighting Company Llc | Substrate Removal During LED Formation |
| US20110204408A1 (en) * | 2007-08-22 | 2011-08-25 | Photonstar Led Limited | High thermal performance packaging for optoelectronics devices |
| CN101414652A (en) * | 2007-10-17 | 2009-04-22 | 叶秀慧 | Package structure for LED and preparation method thereof |
| TW201025670A (en) * | 2008-12-29 | 2010-07-01 | Denki Kagaku Kogyo Kk | Manufacturing process of a substrate for packaging light-emitting device and light-emitting device packaging |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103545416B (en) | 2016-12-21 |
| TW201403892A (en) | 2014-01-16 |
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