CN103545353A - Electrode heating pole and processing technique thereof - Google Patents
Electrode heating pole and processing technique thereof Download PDFInfo
- Publication number
- CN103545353A CN103545353A CN201310491824.9A CN201310491824A CN103545353A CN 103545353 A CN103545353 A CN 103545353A CN 201310491824 A CN201310491824 A CN 201310491824A CN 103545353 A CN103545353 A CN 103545353A
- Authority
- CN
- China
- Prior art keywords
- layer
- etching
- separator
- thermoae
- electrode layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012545 processing Methods 0.000 title claims abstract description 13
- 238000010438 heat treatment Methods 0.000 title abstract description 15
- 238000000034 method Methods 0.000 title abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 54
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 20
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 20
- 230000008021 deposition Effects 0.000 claims abstract description 12
- 239000010408 film Substances 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 7
- 238000000427 thin-film deposition Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 abstract description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 238000002955 isolation Methods 0.000 abstract 5
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 238000006116 polymerization reaction Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 208000034189 Sclerosis Diseases 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000002894 chemical waste Substances 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000035800 maturation Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910000029 sodium carbonate Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
The invention relates to an electrode heating pole and a processing technique thereof. The electrode heating pole comprises a base, a heating pole layer, an isolation layer and an electrode layer. The heating pole layer covers the base by means of deposition. A silicon dioxide isolation layer is further deposited on the heating pole layer. A metal electrode layer covers the heating pole layer and the isolation layer by means of deposition. The electrode layer on the top of the isolation layer is removed by etching. According to the principle that etching rate of silicon dioxide and rate of metal etching have a large difference, the silicon dioxide isolation layer is added between the electrode layer and the heating pole layer and can well protect the electrode layer during etching of the electrode layer; the heating pole layer is effectively prevented from being etched; completeness of the heating pole layer is guaranteed; difficulty in controlling etching time precision is reduced greatly; heating pole performance in products is improved.
Description
Technical field
The present invention relates to a kind of chip electrode, relate in particular to a kind of heated by electrodes utmost point and processing technology thereof.
Background technology
The electrode layer of current chip is normally covered with the electrode layer of thin film shape at substrate surface, then adopt the mode of etching to remove unnecessary electrode layer, forms the electrode layer of final required circuit.
Thin film deposition is a kind of processing mode conventional in chip manufacture process, by depositing technics, can on base material, be grown and be led various conductive membrane layers, insulating thin layer or semiconductor film layer.Why very thin electrode layer is is because thin thickness can have temperature coefficient of resistance very uniformly, dielectric constant is low, can allow like this signal transmission loss less, thin electrode layer is less by temperature rise under large current conditions, and this all has very large benefit for heat radiation and component life.Then be that the monoblock electrode layer that deposit need to be become is etched into required circuit.The line design of chip is printed as to film with mask aligner, then photosensitive dry film a kind of main component is responsive to special spectrum and generation chemical reaction covers on substrate, dry film divides two kinds, photo-polymerization type and light breakdown type, photo-polymerization type dry film can harden under the irradiation of special spectrum, becomes water-insoluble light breakdown type just in time contrary from water-soluble substances.With photo-polymerization type photosensitive dry film, first cover on substrate, lid layer circuit film exposes by it more above, and it is light tight that the place of exposure is black, otherwise is transparent (circuit pack).Light is irradiated on photosensitive dry film by film; on every film, the local dry film of transparent logical light darkens and starts sclerosis; tightly wrap the electrode layer of substrate surface; just as line map is imprinted on substrate; next pass through development step (using sodium carbonate liquor to wash away unhardened dry film); allow and do not need the electrode layer of dry film protection to expose, this is called demoulding operation.
Then be to adopt the mode of etching to remove useless electrode layer part, conventional etching mode is dry etching and wet etching at present.Wet etching is a pure chemical reaction process, refers to that the chemical reaction utilizing between solution and pre-etching material removes the part that not masked membrane material shelters and reaches etching object.Dry etching kind is a lot, comprises photoablation, gaseous corrosion, plasma etching etc.The anisotropy of dry etching is good, selects than high, and controllability, flexibility, reproducible, hachure handling safety, easily realizes automation, and without chemical waste fluid, processing procedure is not introduced pollution, and cleanliness factor is high.
In optical branching device device, on base material, be covered with double-layer films, electrode layer and add thermoae layer, electrode layer is made with the metal that adds thermoae layer employing unlike material, traditional mode is elder generation's deposit one deck zone of heating on base material, deposit one deck electrode layer thereon again, and then electrode layer is implemented to etching form required conducting wire.When etching electrode layer, because the etch rate of metal material is close, and electrode layer and to add thermoae layer adjacent, therefore add and thermoaely also can be etched, electrode layer and add thermoae layer thickness as thin as a wafer, the difficulty of controlling etching precision is excessive, once control bad, can cause and add thermoae being etched, cause damage, have a strong impact on device performance.
Summary of the invention
The technical assignment of technical problem to be solved by this invention and proposition is that prior art is improved, a kind of heated by electrodes utmost point and processing technology thereof are provided, solving in current technology electrode layer etching precision, to control difficulty excessive, very easily cause to add thermoae layer and be etched, have a strong impact on the problem of device performance.
For solving above technical problem, technical scheme of the present invention is:
A kind of heated by electrodes utmost point, comprise base material, add thermoae layer, separator and electrode layer, it is characterized in that, adding thermoae layer overlays on base material by deposit mode, add on thermoae layer and be also deposited with separator, electrode layer is coated on and is added on thermoae layer and separator by deposit mode, and the electrode layer on separator top is removed by etching.There is separator protection the top that adds thermoae layer; when carrying out electrode layer etching, can guarantee to add thermoae layer and not be subject to etching; guarantee its integrality; thereby guaranteed that product adds thermoae performance; and electrode layer and the electric property that adds thermoae layer can not be affected yet, and can realize normally safely electric and heating function.
Further; described separator adopts silicon dioxide to make; the etch rate of silicon dioxide and the etch rate of metal differ greatly; when carrying out metal electrode layer etching, separator silicon dioxide can be by quick etching; thereby will add thermoae layer is hedged off from the outer world; thereby play good protection effect, guarantee to add the integrality of thermoae layer.
Further, the deposition thickness of described separator is 2000～30000 dusts, is guaranteeing that reaching insulation blocking adds the deposition thickness that as far as possible reduces separator in thermoae layer effect, reduces the cost of manufacture of product.
Make the processing technology of the heated by electrodes utmost point, comprise the steps: thin film deposition and etching, it is characterized in that, on base material, deposit one deck adds thermoae layer, then after adding thermoae layer to be etched into required circuit pattern, adding thermoae layer deposit layer of silicon dioxide separator again, then carry out separator etching, removal is coated on the end face that the separator that adds thermoae layer dual-side place is only covered in separator to add thermoae layer, when carrying out separator etching, due to silicon dioxide etching gas etching metal material not substantially, after etching silicon dioxide, add thermoae maintenance complete, deposition of electrode layer more on this basis, the electrode layer of removing separator end face by etching forms required circuit.When carrying out electrode layer etching, due to the protection of separator silicon dioxide, add and thermoaely can not sustain damage; thereby greatly reduce etching and control difficulty; reduced the difficulty of controlling the accurate etching time, made production summary, and raising product adds thermoae performance.
Further, described etching adopts dry etching.Dry etching physical property etching directivity is very strong, can accomplish anisotropic etching, but can not carry out selective etch; Chemistry etching is utilized the chemism atomic group in plasma and the material generation chemical reaction that is etched, thereby realizes etching object.Due to core or the chemical reaction (gaseous state that does not just relate to solution) of etching, so the effect of etching is a bit close with wet etching, have good selectivity, but anisotropy is poor.Adopt dry etching to have anisotropy and the good advantage of selectivity concurrently simultaneously, guarantee the effect of etching.
Further, described thin film deposition adopts chemical vapor deposition to guarantee film thickness uniformity.Chemical vapor deposition is the gaseous reactant introducing reative cell that forms film element containing, and at crystal column surface generation chemical reaction, thereby generates required solid film and is deposited on its surface.The deposition temperature of CVD (Chemical Vapor Deposition) method is low, and thin film composition and thickness are easily controlled, and film thickness is directly proportional to deposition time, uniformity and reproducible, and step coverage is good, easy to operate.
Compared with prior art, the invention has the advantages that:
The heated by electrodes utmost point of the present invention and processing technology thereof are utilized the etch rate of silicon dioxide and principle that metal etch speed differs greatly at electrode layer and added between thermoae layer increases layer of silicon dioxide separator, when carrying out the etching of electrode layer, played good protective effect, effectively avoid adding thermoae layer and suffer etching, guaranteed to add the integrality of thermoae layer, greatly reduce the difficulty of controlling etch period precision, effectively reduce production difficulty, improved the heating polarity energy of product; The present invention is simple in structure, and manufacturing process technology maturation is easy and simple to handle, and cost of manufacture is low, is easy to volume production.
Accompanying drawing explanation
Fig. 1 is the structural representation of deposit separator of the present invention;
Fig. 2 is the structural representation of etching separator of the present invention;
Fig. 3 is the structural representation of deposition of electrode layer of the present invention;
Fig. 4 is the structural representation of etching electrode layer of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The disclosed a kind of heated by electrodes utmost point of the embodiment of the present invention and processing technology thereof, control difficulty to reduce electrode layer etching, and protection adds thermoae layer, and improving product heating polarity can be object.
As shown in Fig. 1～4, a kind of heated by electrodes utmost point, comprise base material 1, add thermoae layer 2, separator 3 and electrode layer 4, separator 3 selects silicon dioxide material to make, the thermoae layer 2 that adds of metal material overlays on base material 1 by deposit mode, the separator 3 that adds on thermoae layer 2 silicon dioxide material in deposit again, the deposition thickness of separator 3 is 2000～30000 dusts, electrode layer 4 is coated on and is added on thermoae layer 2 and separator 3 by deposit mode, the electrode layer 4 on separator 3 tops is removed by etching, when carrying out electrode layer etching, protection due to separator silicon dioxide, adding thermoae layer can not sustain damage.
On base material 1, adopt CVD (Chemical Vapor Deposition) method deposit one deck to add thermoae layer 2, adopt reactive ion etching will add thermoae layer 2 and be etched into required circuit pattern, as shown in Figure 1, adding thermoae layer 2 deposit layer of silicon dioxide separator 3, again as shown in Figure 2, carry out the etching of separator 3, removal is coated on the end face that the separator 3 that adds thermoae layer 2 dual-side place is covered in 3 of separators to add thermoae layer 2, due to silicon dioxide etching gas etching metal not substantially, after etching silicon dioxide, add thermoae metal and keep complete, as shown in Figure 3, adding deposition of electrode layer 4 on thermoae layer 2 and separator 3 more on this basis, the dual-side that makes to add thermoae layer 2 is connected with electrode layer and guarantees that electric UNICOM and heat conducts, as shown in Figure 4 finally, the electrode layer 4 of removing separator 3 end faces by etching makes it to form required circuit.
Below be only the preferred embodiment of the present invention, it should be pointed out that above-mentioned preferred implementation should not be considered as limitation of the present invention, protection scope of the present invention should be as the criterion with claim limited range.For those skilled in the art, without departing from the spirit and scope of the present invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1. the heated by electrodes utmost point, comprise base material (1), add thermoae layer (2), separator (3) and electrode layer (4), it is characterized in that, adding thermoae layer (2) overlays on base material (1) by deposit mode, add on thermoae layer (2) and be also deposited with separator (3), electrode layer (4) is coated on and is added on thermoae layer (2) and separator (3) by deposit mode, and the electrode layer (4) on separator (3) top is removed by etching.
2. the heated by electrodes utmost point according to claim 1, is characterized in that, described separator (3) adopts silicon dioxide to make.
3. the heated by electrodes utmost point according to claim 2, is characterized in that, the deposition thickness of described separator (3) is between 2000～30000 dusts.
4. make the processing technology of the heated by electrodes utmost point, comprise the steps: thin film deposition and etching, it is characterized in that, at the upper deposit one deck of base material (1), add thermoae layer (2), then after adding thermoae layer (2) to be etched into required circuit pattern, adding thermoae layer (2) deposit layer of silicon dioxide separator (3) again, then carry out separator (3) etching, removal is coated on the end face that the separator (3) that adds thermoae layer (2) dual-side place is only covered in separator (3) to add thermoae layer (2), deposition of electrode layer (4) more on this basis, the electrode layer (4) of removing separator (3) end face by etching forms required circuit.
5. heated by electrodes utmost point processing technology according to claim 5, is characterized in that, described etching adopts dry etching.
6. heated by electrodes utmost point processing technology according to claim 5, is characterized in that, described thin film deposition adopts chemical vapor deposition to guarantee film thickness uniformity.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310491824.9A CN103545353B (en) | 2013-10-18 | 2013-10-18 | A kind of heated by electrodes utmost point and processing technology thereof |
| PCT/CN2014/088620 WO2015055118A1 (en) | 2013-10-18 | 2014-10-15 | Electrode heating pole and processing technique thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310491824.9A CN103545353B (en) | 2013-10-18 | 2013-10-18 | A kind of heated by electrodes utmost point and processing technology thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103545353A true CN103545353A (en) | 2014-01-29 |
| CN103545353B CN103545353B (en) | 2016-05-11 |
Family
ID=49968633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310491824.9A Active CN103545353B (en) | 2013-10-18 | 2013-10-18 | A kind of heated by electrodes utmost point and processing technology thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103545353B (en) |
| WO (1) | WO2015055118A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015055118A1 (en) * | 2013-10-18 | 2015-04-23 | 四川飞阳科技有限公司 | Electrode heating pole and processing technique thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100012915A1 (en) * | 2008-07-17 | 2010-01-21 | Electronics And Telecommunications Research Institute | Phase-change memory device and method of fabricating the same |
| CN102053112A (en) * | 2009-10-29 | 2011-05-11 | 比亚迪股份有限公司 | Plate oxygen sensor and preparation method thereof |
| CN102095766A (en) * | 2010-12-02 | 2011-06-15 | 西安交通大学 | Miniature integrated temperature control type CO2 gas sensor and manufacturing method thereof |
| KR101124341B1 (en) * | 2011-01-07 | 2012-03-16 | 주식회사 하이닉스반도체 | Phase change random access memory and method for fabricating the same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005268430A (en) * | 2004-03-17 | 2005-09-29 | Nissan Motor Co Ltd | Ohmic electrode structural body and method for manufacturing the same |
| JP2009158745A (en) * | 2007-12-27 | 2009-07-16 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device |
| JP5799663B2 (en) * | 2011-08-23 | 2015-10-28 | 株式会社豊田中央研究所 | Ohmic electrode and method for forming the same |
| CN103545353B (en) * | 2013-10-18 | 2016-05-11 | 四川飞阳科技有限公司 | A kind of heated by electrodes utmost point and processing technology thereof |
-
2013
- 2013-10-18 CN CN201310491824.9A patent/CN103545353B/en active Active
-
2014
- 2014-10-15 WO PCT/CN2014/088620 patent/WO2015055118A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100012915A1 (en) * | 2008-07-17 | 2010-01-21 | Electronics And Telecommunications Research Institute | Phase-change memory device and method of fabricating the same |
| CN102053112A (en) * | 2009-10-29 | 2011-05-11 | 比亚迪股份有限公司 | Plate oxygen sensor and preparation method thereof |
| CN102095766A (en) * | 2010-12-02 | 2011-06-15 | 西安交通大学 | Miniature integrated temperature control type CO2 gas sensor and manufacturing method thereof |
| KR101124341B1 (en) * | 2011-01-07 | 2012-03-16 | 주식회사 하이닉스반도체 | Phase change random access memory and method for fabricating the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015055118A1 (en) * | 2013-10-18 | 2015-04-23 | 四川飞阳科技有限公司 | Electrode heating pole and processing technique thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2015055118A1 (en) | 2015-04-23 |
| CN103545353B (en) | 2016-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104134870B (en) | A kind of Graphene microstrip antenna and preparation method thereof | |
| JP6092260B2 (en) | Array substrate manufacturing method, array substrate, and display | |
| CN101937945A (en) | Preparation method of solar cell | |
| CN109755209A (en) | A kind of highly reliable photoresist glassivation chip and its processing method | |
| CN102222723A (en) | Solar cell manufacturing method and solar cell manufactured by the method | |
| CN101694012B (en) | Wet etching method of barium-strontium titanate and bismuth zinc niobate composite films | |
| CN103337476A (en) | Method for reducing critical size of copper interconnection groove | |
| CN106340543B (en) | Thin film transistor (TFT), array base palte extremely manufacture method and display panel | |
| CN104393346A (en) | Lithium microbattery fabrication method | |
| CN103545353B (en) | A kind of heated by electrodes utmost point and processing technology thereof | |
| CN103996618A (en) | Manufacturing method for TFT electrode lead | |
| KR101161807B1 (en) | Method of manufacturing Back junction solar cell by using plasma doping and diffusion and the solar cell | |
| CN108054167B (en) | The production method of embedded flash memory | |
| CN103832968B (en) | The manufacture method of MEMS | |
| US20190371954A1 (en) | Solar cell and preparation method thereof | |
| CN109768116A (en) | Preparation method of gallium arsenide solar cell | |
| CN101452873A (en) | Shallow trench isolation process | |
| CN116053332A (en) | Back contact type silicon heterojunction solar cell and preparation method thereof | |
| CN102420124B (en) | Etching method of dielectric layer | |
| CN106505042A (en) | The preparation method of semiconductor devices | |
| CN105826184B (en) | The method for removing the silicon nitride layer on pattern wafer | |
| KR100689861B1 (en) | Semiconductor device manufacturing apparatus using plasma and method for manufacturing the same | |
| CN103137455B (en) | Have the manufacturing method of chip of Low-Voltage Logic Devices and high tension apparatus | |
| CN114512400B (en) | Manufacturing method of semiconductor structure | |
| CN109545803A (en) | Array substrate and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |