CN103545179A - Semiconductor device and forming method thereof - Google Patents

Semiconductor device and forming method thereof Download PDF

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Publication number
CN103545179A
CN103545179A CN201210238596.XA CN201210238596A CN103545179A CN 103545179 A CN103545179 A CN 103545179A CN 201210238596 A CN201210238596 A CN 201210238596A CN 103545179 A CN103545179 A CN 103545179A
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layer
semiconductor device
semiconductor substrate
aluminium
aluminium lamination
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CN103545179B (en
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洪中山
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement

Abstract

Disclosed are a semiconductor device and a forming method thereof. The forming method of the semiconductor device includes the steps: providing a semiconductor substrate, forming an insulating layer on the surface of the semiconductor substrate, forming an opening penetrating the thickness of the insulating layer in the insulating layer and forming a polycrystalline silicon electrode layer flush with the surface of the insulating layer in the opening; forming an aluminum film covering the semiconductor substrate and the surface of the polycrystalline silicon electrode layer; forming a metal layer covering the aluminum film; annealing the structure with the metal layer, enabling aluminum in the aluminum film to enter the bottom of the opening and replace the polycrystalline silicon electrode layer, forming an aluminum layer positioned on the surface of the semiconductor substrate, transferring polycrystalline silicon in the polycrystalline silicon electrode layer to the top of the opening, and reacting the polycrystalline silicon with the metal layer to form a metal silicide layer positioned on the surface of the aluminum layer; chemically and mechanically polishing the metal layer, the aluminum film and the metal silicide layer positioned on the surface of the semiconductor substrate until the metal layer, the aluminum film and the metal silicide layer are exposed to the surface of the insulating layer. The formed semiconductor device is stable in performance.

Description

Semiconductor device and forming method thereof
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of semiconductor device and forming method thereof.
Background technology
Fast development along with ic manufacturing technology, impel the semiconductor device in integrated circuit, especially MOS(Metal Oxide Semiconductor, Metal-oxide-semicondutor) size of device is constantly dwindled, and with this, meets the miniaturization of integrated circuit development and integrated requirement.In the process that the size of MOS transistor device continues to dwindle, existing technique is usingd silica or silicon oxynitride and has been subject to challenge as the technique of gate dielectric layer.Usining silica or silicon oxynitride there are some problems as the formed transistor of gate dielectric layer, comprises that leakage current increases and the diffusion of impurity, thereby affects transistorized threshold voltage, and then affect the performance of semiconductor device.
For overcoming the above problems, adopt metal to be suggested as the transistor of grid.The described transistor with metal gates adopts high K(dielectric constant) material replaces conventional silica or silicon oxynitride gate dielectric material, and when can make transistor size dwindle, reduce the generation of leakage current, and improve transistorized performance.
Prior art forms the transistorized method with metal gates, comprising:
Please refer to Fig. 1, Semiconductor substrate 10 is provided; On described Semiconductor substrate 10 surfaces, form oxide layer 11; On described oxide layer 11 surfaces, form high K dielectric layer 12; On described high K dielectric layer 12 surface, form protective layer 13, the material of described protective layer 13 is titanium nitride or tantalum nitride; On described protective layer 13 surfaces, form dummy gate layer 14.
Please refer to Fig. 2, take described dummy gate layer 14 as protective layer described in mask etching 13, high K dielectric layer 12 and oxide layer 11, form protective layer 13a, high K dielectric layer 12a and oxide layer 11a.
Please refer to Fig. 3, on Semiconductor substrate 10 surfaces of described dummy gate layer 14 both sides, form side wall 15.
Please refer to Fig. 4, at described dummy gate layer 14(as Fig. 3) and the interior formation of the Semiconductor substrate 10 source/drain region 16 of side wall 15 both sides; Behind formation source/drain region 16, on Semiconductor substrate 10 surfaces, form mask layer 18, described mask layer 18 upper surfaces flush with dummy gate layer 14 tops; The described mask layer 18 of take is mask, removes described dummy gate layer 14, forms opening 17.
It should be noted that, behind formation source/drain region 16, carry out thermal annealing, activate described source/drain region 16.Please refer to Fig. 5, at described opening 17(as Fig. 4) in fill full metal, form metal gate electrode layer 19, described metal gate electrode layer 19 upper surfaces flush with the top of described mask layer 18.
Yet the performance of the semiconductor device that prior art forms is still stable not, the formation methods with semiconductor device please refer to the U.S. patent documents that publication number is US 2009/0142899A1 more.
Summary of the invention
The problem that the present invention solves is to provide semiconductor device of a kind of stable performance and forming method thereof.For addressing the above problem, embodiments of the invention provide a kind of formation method of semiconductor device, comprise: Semiconductor substrate is provided, described semiconductor substrate surface is formed with insulating barrier, in described insulating barrier, there is the opening that runs through its thickness, in described opening, be formed with the polysilicon electrode layer flushing with described surface of insulating layer; Form the aluminium film that covers described Semiconductor substrate and polysilicon electrode layer surface; Form the metal level that covers described aluminium film; The said structure forming after metal level is carried out to annealing in process, make the aluminium in described aluminium film enter the alternative polysilicon electrode layer of open bottom, formation is positioned at the aluminium lamination of described semiconductor substrate surface, and polysilicon in polysilicon electrode layer is transferred to open top, and reacts and form the metal silicide layer that is positioned at described aluminium lamination surface with metal level; Chemico-mechanical polishing is positioned at metal level, aluminium film, the metal silicide layer of described semiconductor substrate surface, until expose described surface of insulating layer.
Alternatively, the process parameters range of described annealing in process is: annealing temperature is 400 degrees Celsius-600 degrees Celsius, and annealing time is 30 minutes-450 minutes.
Alternatively, annealing temperature during described annealing in process is 480 degrees Celsius-520 degrees Celsius.
Alternatively, the material of described metal level is titanium, cobalt or nickel.
Alternatively, the thickness of described aluminium film is 100 dust-500 dusts.
Alternatively, the formation technique of described aluminium film is physical gas-phase deposition, and its process parameters range is: the pressure of deposition chambers is 1 millitorr-10 millitorr, and depositing temperature is 400 degrees Celsius-600 degrees Celsius.
Alternatively, the material of described metal silicide layer is titanizing silicon, cobalt SiClx or nickel SiClx.
Alternatively, after chemico-mechanical polishing, the thickness of the metal silicide layer in described opening is 10 dust-300 dusts.
Alternatively, the depth-to-width ratio of described opening is greater than 8, and the formation technique of described polysilicon electrode layer is chemical vapor deposition method.
Alternatively, be also formed with high-K gate dielectric layer in described opening, described polysilicon electrode layer covers described high-K gate dielectric layer surface.
Alternatively, be also formed with functional layer in described opening, described functional layer is formed at described high-K gate dielectric layer and polysilicon electrode interlayer.
Accordingly, inventor also provides a kind of semiconductor device, comprising: Semiconductor substrate; Be positioned at the insulating barrier of described semiconductor substrate surface; The opening that runs through described thickness of insulating layer; The semiconductor substrate surface of described open bottom has aluminium lamination; Described aluminium lamination surface is formed with metal silicide layer, and described metal silicified layer surface flushes with described surface of insulating layer.
Alternatively, the material of described metal silicide layer is titanizing silicon, cobalt SiClx or nickel SiClx.
Alternatively, the thickness of described metal silicide layer is 10 dust-300 dusts.
Alternatively, also comprise: the semiconductor substrate surface high-K gate dielectric layer that is positioned at described open bottom.
Alternatively, also comprise: the functional layer between described high-K gate dielectric layer and aluminium lamination.
Compared with prior art, technical scheme of the present invention has the following advantages:
First form the aluminium film that covers described polysilicon layer surface and the metal level that covers described aluminium film, follow-up while carrying out annealing in process, aluminium in described aluminium film enters open bottom, formation is positioned at the aluminium lamination of described semiconductor substrate surface, the quality of described aluminium lamination is good, inside does not have hole, and is mono-crystalline structures, and mechanical endurance is good.Polysilicon in polysilicon electrode layer upwards shifts simultaneously; with the metal level formation metal silicide layer that reacts; saved processing step; and the follow-up aluminium on aluminium lamination surface of can protecting of metal silicide layer forming is not oxidized; and in subsequent technique, avoided aluminium lamination to be damaged, the stable performance of the semiconductor device of formation.
Because the aluminium lamination surface coverage of semiconductor device has metal silicide layer, described aluminium lamination is difficult for oxidized, and has avoided aluminium lamination to damage in subsequent technique, the quality of described aluminium lamination is good, and described aluminium lamination is mono-crystalline structures, and its durability and mechanical strength are high, the stable performance of semiconductor device.
Accompanying drawing explanation
Fig. 1-Fig. 5 is the cross-sectional view of the forming process of prior art semiconductor device;
Fig. 6-Figure 10 is the cross-sectional view of forming process of the semiconductor device of first embodiment of the invention;
Figure 11-Figure 17 is the cross-sectional view of forming process of the semiconductor device of second embodiment of the invention.
Embodiment
The performance of the semiconductor device that as described in background, prior art forms is stable not.
Through research, find, along with the size of semiconductor device is constantly dwindled, form in the process of described semiconductor device, please refer to Fig. 4, the depth-to-width ratio of removing the opening 17 forming after dummy gate layer increases gradually, during to the interior filling metal material of described opening 17, can meet difficulty, especially, when the depth-to-width ratio of described opening 17 is greater than 7, the metal gate electrode layer 19(of formation is as shown in Figure 5) there is more defect in inside.The interior hole that exists of metal gate electrode layer 19 for example, has had a strong impact on the performance of semiconductor device.
After further research, inventor finds that a kind of employing aluminium substitutes the technology of polysilicon (polysilicon-auluminum substitute).Under annealing process, the aluminium that is positioned at polysilicon electrode layer surface can enter into open bottom, the polysilicon electrode layer that is originally positioned at described opening is transferred to open top, after described annealing process, be formed on the content few (being less than or equal to 0.4%) of polysilicon in the aluminium lamination of open bottom, can not destroy the performance of semiconductor device.And, after annealing process, in described aluminium lamination, have hardly hole, and described aluminium lamination being mono-crystalline structures, its mechanical endurance can be better, contribute to the semiconductor device of follow-up formation superior performance.
Further; inventor finds; the aluminium that is used as the aluminium lamination surface of grid after annealing process is exposed in air very easily oxidized; and easily destroyed in follow-up glossing; need to form layer protective layer at described aluminium film surface; to avoid aluminium lamination surface oxidized, and protect aluminium lamination not damaged.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
The first embodiment
In the first embodiment of the present invention, the forming process of metal gates of semiconductor device of take is carried out exemplary illustrated as example.
Please refer to Fig. 6, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 surface coverage have interfacial film 101, described interfacial film 101 surface coverage have high K dielectric film 103, described high K dielectric film 103 surface coverage have polysilicon membrane 105, described polysilicon membrane 105 surfaces are formed with photoresist layer 107, and described photoresist layer 107 has the figure (not indicating) that defines grid.
Described Semiconductor substrate 100 is used to subsequent technique that workbench is provided.Described Semiconductor substrate 100 is body silicon or silicon-on-insulator (SOI), and the material of described Semiconductor substrate 100 is monocrystalline silicon, SiGe, silicon-carbon or III-V compounds of group (such as gallium arsenic, indium phosphide and gallium nitride etc.).In embodiments of the invention, in described Semiconductor substrate 100, be also formed with fleet plough groove isolation structure 102, for the adjacent metal-oxide-semiconductor of follow-up isolation.
The material of described interfacial film 101 is silica, for follow-up formation boundary layer, reduces the interface resistance between the first high K dielectric layer and Semiconductor substrate 100.The formation technique of described interfacial film 101 is depositing operation, for example physics or chemical vapor deposition method.
Described high K dielectric film 103 is for follow-up formation high K dielectric layer, isolation of semiconductor substrate 100 and metal gate electrode layer.The material of described high K dielectric film 103 is HfO 2, HfSiO, HfSiNO or ZrO 2deng.The formation technique of described high K dielectric film 103 is depositing operation, for example physics or chemical vapor deposition method.
Described polysilicon membrane 105 is the polysilicon electrode layer as pseudo-grid for follow-up formation.The formation technique of described polysilicon membrane 105 is depositing operation, for example physics or chemical vapor deposition method.In an embodiment of the present invention, the thickness of described polysilicon membrane 105 is 400 dust-800 dusts.
Described photoresist layer 107 is for as mask, successively polysilicon membrane 105, high K dielectric film 103, interfacial film 101 described in etching.Owing to forming the technique of described photoresist layer 107, be well known to those skilled in the art, do not repeat them here.
It should be noted that, in other embodiments of the invention, described Semiconductor substrate 100 surfaces can only be formed with high-K medium film 103; Or the function film (not shown) that is formed with interfacial film 101 in described Semiconductor substrate 100, is positioned at the high-K medium film 103 on described interfacial film 101 surfaces and is positioned at described high-K medium film 103 surfaces, described function film, for the functional layer of follow-up formation semiconductor device, is adjusted the work function of described semiconductor device.
Please refer to Fig. 7, take described photoresist layer 107(as shown in Figure 6) be mask, described in etching, polysilicon membrane 105(is as shown in Figure 6 successively), high K dielectric film 103(as shown in Figure 6), interfacial film 101(as shown in Figure 6), form polysilicon electrode layer 105a, high K dielectric layer 103a, boundary layer 101a; After forming polysilicon electrode layer 105a, high K dielectric layer 103a, boundary layer 101a, on described Semiconductor substrate 100 surfaces, form the insulating barrier 109 with described polysilicon electrode layer 105a flush.
Described in etching, the technique of polysilicon membrane 105, high K dielectric film 103, interfacial film 101 is anisotropic etching technics, for example dry etch process.Because the technique of polysilicon membrane 105, high K dielectric film 103, interfacial film 101 described in described etching is well known to those skilled in the art, do not repeat them here.
Described polysilicon electrode layer 105a forms after by described polysilicon electrode film 105 etchings, and the thickness of described polysilicon electrode layer 105a is identical with the thickness of described polysilicon electrode film 105.In an embodiment of the present invention, the thickness of described polysilicon electrode layer 105a is 300 dust-700 dusts.
Described insulating barrier 109 is for isolating the grid of adjacent semiconductor device.The material of described insulating barrier 109 is silica, silicon nitride or silicon oxynitride.The formation technique of described insulating barrier 109 is depositing operation, for example physics or chemical vapor deposition method.In an embodiment of the present invention, the material of described insulating barrier 109 is silica, and its formation method is: adopt tetraethoxysilane (TEOS) and ozone to react.
In an embodiment of the present invention, for Semiconductor substrate 100 in subsequent chemical-mechanical polishing technique or etching technics is not destroyed, also comprise: before forming insulating barrier 109, form the etching barrier layer 111 that covers described polysilicon layer 105a and Semiconductor substrate 100.The material of described etching barrier layer 111 is silicon nitride, and it forms technique is chemical vapor deposition method.
It should be noted that, when the insulating barrier 109 of chemical polishing formation and described polysilicon electrode layer 105a flush, etching barrier layer 111 and the photoresist layer 107 at described polysilicon electrode layer 105a top also can be removed.
Please refer to Fig. 8, form the aluminium film 113 that covers described insulating barrier 109 and polysilicon electrode layer 105a surface; Form the metal level 115 that covers described aluminium film 113 surfaces.
Inventor finds, adopt aluminium to substitute the technology of polysilicon (polysilicon-auluminum substitute), under annealing process, the aluminium that is arranged in polysilicon electrode layer 105a surface can enter into opening, and (the present embodiment is corresponding to the position of polysilicon electrode layer 105a, do not indicate) bottom, and the polysilicon electrode layer 105a that is positioned at described high K medium layer 103a surface is originally transferred to open top.
Described aluminium film 113 is replaced the polysilicon electrode layer 105a that is positioned at described high K medium layer 103a surface for subsequent technique.For the aluminium lamination that makes to form after subsequent anneal technique opening described in filling part only, the thinner thickness of the described aluminium film 113 of formation, preferably, the thickness of described aluminium film 113 is 300 dust-700 dusts of the thickness of polysilicon electrode layer 105a.In an embodiment of the present invention, the thickness of described aluminium film 113 is 100 dust-500 dusts.
The formation technique of described aluminium film 113 is physical gas-phase deposition, and its process parameters range is: the pressure of deposition chambers is 1 millitorr-10 millitorr, and depositing temperature is 400 degrees Celsius-600 degrees Celsius.Technological parameter while in an embodiment of the present invention, adopting gas-phase deposition to form described aluminium film 113 is: the pressure of deposition chambers is 8 millitorrs, and depositing temperature is 500 degrees Celsius.
Inventor's discovery, after subsequent anneal technique, the aluminium that is used as the aluminium lamination surface of grid is exposed in air very easily oxidized; and easily destroyed in follow-up glossing; need to form layer protective layer at described aluminium film surface, to avoid aluminium lamination surface oxidized, and protect aluminium lamination not damaged.
Further; inventor also finds; polysilicon during subsequent anneal technique in polysilicon layer is constantly transferred to top by bottom; the described polysilicon that is transferred to top just in time can react with metal level 115 in annealing temperature; generate metal silicide layer, using as the not oxidized protective layer of protection aluminium lamination.Therefore, can in the time of follow-up formation aluminium lamination, also form the metal silicide layer that covers described aluminium lamination surface first at aluminium film 113 forming metal layer on surfaces 115, effectively save processing step.
Described metal level 115 reacts with the polysilicon layer that is transferred to open top during for subsequent anneal technique, forms metal silicide layer.Find after deliberation, when the material of described metal level 115 is titanium (Ti), cobalt (Co) or nickel (Ni), the better effects if of the metal silicide layer protection aluminium lamination of follow-up formation.In an embodiment of the present invention, the material of described metal level 115 is titanium, and the formation technique that forms described metal level 115 is physical gas-phase deposition.
Please refer to Fig. 9, the said structure forming after metal level 115 is carried out to annealing in process, make the aluminium in described aluminium film 113 enter the alternative polysilicon electrode layer 105a(of open bottom as shown in Figure 8), formation is positioned at the aluminium lamination 113a on described Semiconductor substrate 100 surfaces, and polysilicon in polysilicon electrode layer 105a is transferred to open top, and reacts and form the metal silicide layer 117 that is positioned at described aluminium lamination 113a surface with metal level 115.
Described annealing in process is used to form aluminium lamination 113a and metal silicide layer 117.The process parameters range of described annealing in process is: annealing temperature is 400 degrees Celsius-600 degrees Celsius, and annealing time is 30 minutes-450 minutes.In an embodiment of the present invention, the technological parameter of described annealing in process is: annealing temperature is 480 degrees Celsius-520 degrees Celsius, is preferably 500 degrees Celsius, and annealing time is 60 minutes.Under this technological parameter, the better quality of the aluminium lamination 113a of formation, described aluminium lamination 113a inside does not almost have defect, and polysilicon electrode layer 105a is almost all transferred to open top, and the polysilicon content in aluminium lamination 113a is minimum, and its mass percent is less than 0.4%.
Due to the thickness of aluminium film 113 thickness lower than polysilicon electrode layer 105a, the aluminium lamination 113a surface of formation is lower than described open surfaces.In embodiments of the invention, the thickness of the aluminium lamination 113a of formation is 300 dust-700 dusts.
Described metal silicide layer 117 is follow-up for the protective layer as aluminium lamination 113a, protects the aluminium on aluminium lamination 113a surface not oxidized on the one hand, protects on the other hand aluminium lamination 113a in subsequent etching or CMP (Chemical Mechanical Polishing) process to avoid destroying.Due to described metal silicide layer 117 for the polysilicon in polysilicon electrode layer 105a is transferred to open top, react with metal level 115 after formation, the material of described metal silicide layer 117 is titanizing silicon, cobalt SiClx or nickel SiClx.In an embodiment of the present invention, the material of described metal silicide layer 117 is titanizing silicon.
Please refer to Figure 10, the metal level 115(that chemico-mechanical polishing is positioned at described Semiconductor substrate 100 surfaces is as shown in Figure 9), aluminium film 113(as shown in Figure 9) and metal silicide layer 117(as shown in Figure 9), until expose described insulating barrier 109 surfaces.
The speed when speed while considering chemico-mechanical polishing metal level 115 and aluminium film 113 is greater than chemico-mechanical polishing metal silicide layer 117.In an example of the present invention, first adopt H 2o 2remove metal level 115 and aluminium film 113 with the chemical reagent wet etching of HCl, then adopt the method for chemico-mechanical polishing to remove described metal silicide layer 117.In another example of the present invention, also can be divided into two step chemico-mechanical polishings, first step chemico-mechanical polishing adopts and comprises H 2o 2grinding reagent with HCl, remove the metal silicide layer of metal level 115 and aluminium film 113 and segment thickness, while then adopting etching metal silicide layer 117, speed is ground faster reagent and is carried out second step chemico-mechanical polishing, until expose insulating barrier 109 surfaces.
Because described aluminium lamination 113a surface is lower than described open surfaces, lower than described insulating barrier 111 surfaces.Therefore after chemico-mechanical polishing, described aluminium lamination 113a surface also has metal silicide layer 117a, and the thickness of described remaining metal silicide layer 117a is 10 dust-300 dusts, can play the effect of protection aluminium lamination 113a.
It should be noted that, in other embodiments of the invention, except being used to form grid structure, due to larger for filling the depth-to-width ratio of the jack that forms conductive plunger, also can first adopt the technique of chemical vapour deposition (CVD) first in jack, to form polysilicon layer; Then form the aluminium film that covers insulating barrier and polysilicon layer; Form the metal level that covers described aluminium film surface; Then carry out annealing in process, aluminium and the polysilicon in jack in described aluminium film are replaced, finally form the conductive plunger of aluminium material.Because the conductive plunger inside of described aluminium material does not almost have cavity, and be mono-crystalline structures, the quality of the conductive plunger of described aluminium material is good, stable performance.
After above-mentioned steps completes, the completing of the semiconductor device of first embodiment of the invention.First form the aluminium film that covers described polysilicon layer surface and the metal level that covers described aluminium film, follow-up while carrying out annealing in process, aluminium in described aluminium film enters open bottom, formation is positioned at the aluminium lamination of described semiconductor substrate surface, the quality of described aluminium lamination is good, inside does not have hole, and is mono-crystalline structures, and mechanical endurance is good.Polysilicon in polysilicon electrode layer upwards shifts simultaneously; with the metal level formation metal silicide layer that reacts; saved processing step; and the follow-up aluminium on aluminium lamination surface of can protecting of metal silicide layer forming is not oxidized; and in subsequent technique, avoided aluminium lamination to be damaged, the stable performance of the semiconductor device of formation.
Accordingly, please continue to refer to Figure 10, inventor also provides a kind of semiconductor device, comprising:
Semiconductor substrate 100;
Be positioned at the insulating barrier 109 on described Semiconductor substrate 100 surfaces;
The opening (not indicating) that runs through described insulating barrier 109 thickness;
Semiconductor substrate 100 surfaces of described open bottom have aluminium lamination 113a;
Described aluminium lamination 113a surface is formed with metal silicide layer 117a, described metal silicified layer 117a surface and described insulating barrier 109 flush.
Wherein, described Semiconductor substrate 100 is for the workbench as subsequent technique.Described Semiconductor substrate 100 is body silicon or silicon-on-insulator (SOI), and the material of described Semiconductor substrate 100 is monocrystalline silicon, SiGe, silicon-carbon or III-V compounds of group (such as gallium arsenic, indium phosphide and gallium nitride etc.).In embodiments of the invention, in described Semiconductor substrate 100, be also formed with fleet plough groove isolation structure 102, for the adjacent metal-oxide-semiconductor of follow-up isolation.
Described insulating barrier 109 is for isolating the grid of adjacent semiconductor device.The material of described insulating barrier 109 is silica, silicon nitride or silicon oxynitride.In an embodiment of the present invention, the material of described insulating barrier 109 is oxygen silica.
Described opening forms the conductive plunger of metal gate electrode layer or interconnection structure for filling aluminium lamination 113a.Even if the depth-to-width ratio of described opening is greater than at 7 o'clock, described aluminium lamination 113a is still mono-crystalline structures, excellent in durability, and mechanical strength is high, and internal defects is few, and quality is good.For described aluminium lamination 113a is not destroyed in subsequent technique, follow-uply also can form protective layer on described aluminium lamination 113a surface, therefore the thickness of described aluminium lamination 113a is little compared with the degree of depth of described opening, and described aluminium lamination 113a surface is lower than described insulating barrier 111 surfaces.
It should be noted that, when described aluminium lamination 113a is used as formation metal gate electrode layer, described semiconductor device also comprises: the surperficial high K medium layer of Semiconductor substrate 100 103a that is positioned at described opening.And in order to reduce the interface resistance between described high K dielectric layer 103a and Semiconductor substrate 100, described semiconductor device also comprises: the boundary layer 101a between described high K medium layer 103a and Semiconductor substrate.
It should be noted that, the forming process of described aluminium lamination 113a please refer to the formation method of aforesaid semiconductor device, does not repeat them here.
Described metal silicide layer 117a, for the protective layer as aluminium lamination 113a, protects the aluminium on aluminium lamination 113a surface not oxidized on the one hand, protects on the other hand aluminium lamination 113a in subsequent etching or CMP (Chemical Mechanical Polishing) process to avoid destroying.The material of described metal silicide layer 117a is titanizing silicon, cobalt SiClx or nickel SiClx.In an embodiment of the present invention, the material of described metal silicide layer 117a is titanizing silicon, and the thickness of described metal silicide layer 117a is 10 dust-300 dusts, can play the effect of protection aluminium lamination 113a.
The structure of the aluminium lamination of the semiconductor device of first embodiment of the invention is mono-crystalline structures, and the aluminium lamination durability of described mono-crystalline structures is stronger, and the mechanical strength of the semiconductor device of formation is high, and the stability of semiconductor device is provided.And, because the aluminium on described aluminium lamination surface has metal silicide layer protection, avoided its surfaces of aluminum oxidized, also protected aluminium lamination in subsequent etching or CMP (Chemical Mechanical Polishing) process to avoid destroying, the performance of semiconductor device is more stable.
The second embodiment
Slightly different from the first embodiment of the present invention, in second embodiment of the invention, take and form CMOS pipe and carry out exemplary illustrated as example, and be formed with functional layer between described high K medium layer and polysilicon electrode layer, for the work function of subsequent adjustment semiconductor device.
Please refer to Figure 11, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 comprises first area I and adjacent second area II with it, Semiconductor substrate 200 surfaces of described first area I are formed with the first boundary layer 201a successively, be positioned at the first high K medium layer 203a on described the first boundary layer 201a surface, be positioned at the first pseudo-gate electrode layer 205a on described the first high K medium layer 203a surface, Semiconductor substrate 200 surfaces of described second area II are formed with second contact surface layer 201b successively, be positioned at the second high K medium layer 203b on described second contact surface layer 201b surface, be positioned at the second pseudo-gate electrode layer 205b on described the second high K medium layer 203b surface, and described Semiconductor substrate 200 surfaces are also formed with insulating barrier 207, described insulating barrier 207 surfaces and described the first pseudo-gate electrode layer 205a and the second pseudo-gate electrode layer 205b flush.
Wherein, described Semiconductor substrate 200 is used to subsequent technique that workbench is provided.Described Semiconductor substrate 200 is body silicon or silicon-on-insulator (SOI), and the material of described Semiconductor substrate 200 is monocrystalline silicon, SiGe, silicon-carbon or III-V compounds of group (such as gallium arsenic, indium phosphide and gallium nitride etc.).In embodiments of the invention, in described Semiconductor substrate 200, be also formed with fleet plough groove isolation structure 202, for the region of follow-up isolation.
In an embodiment of the present invention, first area I is used to form NMOS pipe, and described second area II is used to form PMOS pipe.
It should be noted that, in other embodiments of the invention, can also be: described first area I is used to form PMOS pipe, described second area II be for NMOS pipe.
Described the first boundary layer 201a is for reducing the interface resistance between the first high K dielectric layer 203a and Semiconductor substrate 200, and described second contact surface layer 201b is for reducing the interface resistance between the second high K dielectric layer 203b and Semiconductor substrate 200.In an embodiment of the present invention, described the first boundary layer 201a is identical with the material of second contact surface layer 201b, is silica.More formation technology and steps about the first boundary layer 201a and boundary layer 201b please refer to the associated description of first embodiment of the invention median surface layer, do not repeat them here.
Described the first high K medium layer 203a is for isolating Semiconductor substrate 200 and the first pseudo-gate electrode layer 205a of first area I, and the material of described the first high K medium layer 203a is HfO 2, HfSiO, HfSiNO or ZrO 2deng.Described the second high K medium layer 203b is for isolating Semiconductor substrate 200 and the second pseudo-gate electrode layer 205b of second area II, and the material of described the second high K medium layer 203b is HfO 2, HfSiO, HfSiNO or ZrO 2deng.In an embodiment of the present invention, described the first high K medium layer 203a is identical with the material of the second high K medium layer 203b, is ZrO 2.More associated description about the first high K medium layer 203a and the second high K medium layer 203b please refer to the associated description of high K medium layer in first embodiment of the invention, do not repeat them here.
Described the first pseudo-gate electrode layer 205a forms the first opening for follow-up being removed, and described the second pseudo-gate electrode layer 205b forms the second opening for follow-up being removed.In the second embodiment of the present invention, the material of described the first pseudo-gate electrode layer 205a and described the second pseudo-gate electrode layer 205b is polysilicon.
It should be noted that, the material of described the first pseudo-gate electrode layer 205a and the second pseudo-gate electrode layer 205b can also be other materials, as long as follow-up, easily removes.
Described insulating barrier 207 is for isolating the grid in adjacent two regions.The material of described insulating barrier 207 is silica, silicon nitride or silicon oxynitride.In an embodiment of the present invention, described insulating barrier 207 is for isolating the first metal gate electrode of first area I and the second metal gate electrode of second area II, and the material of described insulating barrier 207 is silica.More associated description about described insulating barrier 207 please refer to the first embodiment of the present invention.
It should be noted that; for in subsequent technique; protect described insulating barrier 207 and Semiconductor substrate 200; also comprise: before forming insulating barrier 207; form the etching barrier layer 209 that covers described the first pseudo-gate electrode layer 205a, the second pseudo-gate electrode layer 205b and Semiconductor substrate 200; the material of described etching barrier layer 209 is silicon nitride, and it forms technique is chemical vapor deposition method.In the processing step of chemico-mechanical polishing insulating barrier 207, described etching barrier layer 209 also can be polished, and only residue is positioned at the part on the first pseudo-gate electrode layer 205a sidewall, the second pseudo-gate electrode layer 205b sidewall and Semiconductor substrate 200 surfaces.
Please refer to Figure 12, remove the first pseudo-gate electrode layer 205a(of first area I as shown in figure 11), form the first opening 211a.
Described the first opening 211a is for follow-up filling the first function film.The formation step of described the first opening 211a comprises: form the first photoresist layer (not shown) that covers described insulating barrier 207, etching barrier layer 209 and the second pseudo-gate electrode layer 205b; Take described the first photoresist layer as the first pseudo-gate electrode layer 205a described in mask etching, until expose the first high K medium layer 203a.Wherein, the technique of the first pseudo-gate electrode layer 205a is anisotropic dry etch process described in etching, because this technique is well known to those skilled in the art, does not repeat them here.
Please refer to Figure 13, form to cover described the first opening 211a(as shown in figure 12) the first functional layer 213a of bottom and sidewall, form the first polysilicon electrode layer 215a that covers described the first functional layer 213a, described the first polysilicon electrode layer 215a surface and described insulating barrier 207 flush.
Described the first functional layer 213a is for regulating the work function of the semiconductor device of first area I.The formation step of described the first functional layer 213a comprises: form the bottom and the sidewall that cover described the first opening 211a, and the first function film of described insulating barrier 207; The first function film described in chemico-mechanical polishing, pointer exposes insulating barrier 207.In the second embodiment of the present invention, the material of described the first functional layer 213a is one or more combinations in titanium nitride, tantalum nitride, titanium aluminide or tantalum, for regulating the work function of NMOS pipe.
The material of described the first polysilicon electrode layer 215a is polysilicon, during for subsequent anneal, by the aluminium of the aluminium film on described the first polysilicon electrode layer 215a surface, is replaced, and the first functional layer 213a surface in described the first opening 211a forms aluminium lamination.The formation step of described the first polysilicon electrode layer 215a comprises: form the first polysilicon electrode film (not shown) that covers described the first functional layer 213a; The first polysilicon electrode film described in chemico-mechanical polishing, until expose insulating barrier 207.
In an embodiment of the present invention, described the first polysilicon electrode film covers described the first function film, and the first polysilicon electrode film described in chemico-mechanical polishing, forms after the first polysilicon electrode layer 215a, and then the first function film described in chemico-mechanical polishing, forms the first functional layer 213a.
Please refer to Figure 14, remove described the second pseudo-gate electrode layer 205b(as shown in figure 13), form the second opening 211b that exposes described the second high K medium layer 203b.
Described the second opening 211b is for follow-up filling the second function film.The formation step of described the second opening 211b can be with reference to the first opening 211a(as shown in figure 12) formation step, do not repeat them here.
Please refer to Figure 15, form the second functional layer 213b that covers described the second opening 211b bottom and sidewall, form the second polysilicon electrode layer 215b that covers described the second functional layer 213b, described the second polysilicon electrode layer 215b surface and described insulating barrier 207 flush.
Described the second functional layer 213b is for regulating the work function of the semiconductor device of second area II.In an embodiment of the present invention, the material of described the second functional layer 213b is one or more combinations in titanium nitride, tantalum nitride, titanium aluminide or tantalum, but the material of described the second functional layer 213b is different from the material of described the first functional layer 213a, for regulating the work function of PMOS pipe.The formation step of described the second functional layer 213b and technique please refer to the first functional layer 213a(above as shown in figure 13) associated description, do not repeat them here.
The material of described the second polysilicon electrode layer 215b is polysilicon, during for subsequent anneal, by the aluminium of the aluminium film on described the second polysilicon electrode layer 215b surface, is replaced, and the second functional layer 213b surface in described the second opening 211b forms aluminium lamination.More descriptions about described the second polysilicon electrode layer 215b please refer to above in the first polysilicon electrode layer 215a(as shown in figure 13) associated description, do not repeat them here.
Please refer to Figure 16, form the aluminium film 217 that covers described insulating barrier 207, the first polysilicon electrode layer 215a and the second polysilicon electrode layer 215b; Form the metal level 219 that covers described aluminium film 217 surfaces.
Described aluminium film 217 is replaced the first polysilicon electrode layer 215a and the second polysilicon electrode layer 215b for follow-up and technique.In an embodiment of the present invention, the thickness of described aluminium film 113 is 100 dust-500 dusts, and it forms technique is physical gas-phase deposition, and process parameters range is: the pressure of deposition chambers is 1 millitorr-10 millitorr, and depositing temperature is 400 degrees Celsius-600 degrees Celsius.
Described metal level 219 reacts with the polysilicon layer that is transferred to open top during for subsequent anneal technique, forms metal silicide layer.The material of described metal level 219 is titanium (Ti), cobalt (Co) or nickel (Ni).
More associated description about aluminium film 217 and metal level 219 please refer to the associated description in first embodiment of the invention, do not repeat them here.
Please refer to Figure 17, to forming the said structure of metal level 219, carry out annealing in process, make described aluminium film 217(as shown in figure 16) in aluminium enter the first opening 211a(as shown in figure 13) bottom, substitute the first polysilicon electrode layer 215a(as shown in figure 16), formation is positioned at the first aluminium lamination 217a on the first functional layer 213a surface of described the first opening 211a, aluminium in described aluminium film enters the second opening 211b(as shown in figure 13) bottom, substitute the second polysilicon electrode layer 215b(as shown in figure 16), formation is positioned at the second aluminium lamination 217b on the second functional layer 213b surface of described the second opening 211b, polysilicon in the first polysilicon electrode layer 215a and the second polysilicon electrode layer 215b is transferred to respectively the first opening 211a and the second opening 211b top simultaneously, react with metal level 219 respectively, formation is positioned at the first metal silicide layer 221a on the first aluminium lamination 217a surface, formation is positioned at the second metal silicide layer 221b on the second aluminium lamination 217b surface.
The process parameters range of described annealing in process is: annealing temperature is 400 degrees Celsius-600 degrees Celsius, and annealing time is 30 minutes-450 minutes.In an embodiment of the present invention, the technological parameter of described annealing in process is: annealing temperature is 480 degrees Celsius-520 degrees Celsius, is preferably 500 degrees Celsius, and annealing time is 60 minutes.Under this technological parameter, the the first aluminium lamination 217a forming and the better quality of the second aluminium lamination 217b, described the first aluminium lamination 217a and the second aluminium lamination 217b inside almost do not have defect, and the polysilicon in the first polysilicon electrode layer 215a, the second polysilicon electrode layer 215b is almost all transferred to corresponding open top, polysilicon content in the first aluminium lamination 217a and the second aluminium lamination 217b is minimum, and its mass percent is less than 0.4%.
More formation Method and process that form the first aluminium lamination 217a, the second aluminium lamination 217b, the first metal silicide layer 221a and the second metal silicide layer 221b about annealing in process please refer to first embodiment of the invention, do not repeat them here.
It should be noted that, after annealing in process, also comprise: the aluminium film 217(on chemico-mechanical polishing insulating barrier 207 surfaces is as shown in figure 16), metal level 219(as shown in figure 16), the first metal silicide layer 221a of segment thickness and the second metal silicide layer 221b of segment thickness.Specifically please refer to the associated description in first embodiment of the invention, do not repeat them here.
The formation method of the semiconductor device of second embodiment of the invention, on the first high K medium layer surface of first area, form the first functional layer respectively, the second high K medium layer surface at second area forms the second functional layer, for regulating the work function of semiconductor device, strengthen the performance of semiconductor device.Then form the first polysilicon electrode layer that covers the first functional layer, cover the second polysilicon electrode layer of the second functional layer, and formation covers described the first polycrystalline electrodes layer, the aluminium film of the second polysilicon electrode layer and insulating barrier, and the metal level that covers described aluminium film surface, following adopted annealing process, make the aluminium in aluminium film replace the first polycrystalline electrodes layer, formation is positioned at first aluminium lamination on the first functional layer surface, make the aluminium in aluminium film replace the second polycrystalline electrodes layer, formation is positioned at second aluminium lamination on the second functional layer surface, polysilicon in while the first polysilicon electrode layer and the second polysilicon electrode layer is transferred to top and metal level reacts, form respectively the first metal silicide layer and the second metal silicide layer.Because the quality of the first aluminium lamination and the second aluminium lamination is good, inside does not almost have defect, and is mono-crystalline structures, the stable performance of the semiconductor device of formation.
Accordingly, please continue to refer to Figure 17, inventor provides a kind of semiconductor device, comprising:
Semiconductor substrate 200, described Semiconductor substrate 200 comprises first area I and second area II;
Be positioned at the insulating barrier 207 on described Semiconductor substrate 200 surfaces;
The first opening (do not indicate) that runs through described insulating barrier 207 thickness of first area I, runs through second opening (not indicating) of insulating barrier 207 thickness of second area II;
Semiconductor substrate 200 surfaces of described the first open bottom are formed with the first high K medium layer 203a, described the first high K medium layer 203a surface and the first opening sidewalls are formed with the first functional layer 213a, described the first functional layer 213a surface coverage has the first aluminium lamination 217a, described the first aluminium lamination 217a surface is formed with the first metal silicide layer 221a, described the first metal silicide layer 221a surface and described insulating barrier 207 flush;
Semiconductor substrate 200 surfaces of described the second open bottom are formed with the second high K medium layer 203b, described the second high K medium layer 203b surface and the second opening sidewalls are formed with the second functional layer 213b, described the second functional layer 213b surface coverage has the second aluminium lamination 217b, described the second aluminium lamination 217b surface is formed with the second metal silicide layer 221b, described the second metal silicide layer 221b surface and described insulating barrier 207 flush.
Wherein, described Semiconductor substrate 200 is for the workbench as subsequent technique.Described Semiconductor substrate 200 is body silicon or silicon-on-insulator (SOI), and the material of described Semiconductor substrate 200 is monocrystalline silicon, SiGe, silicon-carbon or III-V compounds of group (such as gallium arsenic, indium phosphide and gallium nitride etc.).In embodiments of the invention, described Semiconductor substrate 200 comprises first area I and second area II, described first area I is used to form NMOS pipe, and described second area II is used to form PMOS pipe, and described first area I and second area II isolate by fleet plough groove isolation structure 202.
Described insulating barrier 207 is for isolating the first aluminium lamination 217a and the second aluminium lamination 217b of first area I and second area II.The material of described insulating barrier 207 is silica, silicon nitride or silicon oxynitride.In an embodiment of the present invention, the material of described insulating barrier 207 is silica.
The material of described the first high K medium layer 203a is HfO 2, HfSiO, HfSiNO or ZrO 2deng, for isolating the first aluminium lamination 217a and Semiconductor substrate 200.The material of described the second high K medium layer 203b is HfO 2, HfSiO, HfSiNO or ZrO 2deng, for isolating the second aluminium lamination 217b and Semiconductor substrate 200.In an embodiment of the present invention, described the first high K medium layer 203a is identical with the material of the second high K medium layer 203b, is ZrO 2.
The material of described the first functional layer 213a is one or more combinations in titanium nitride, tantalum nitride, titanium aluminide or tantalum, for regulating the work function of the semiconductor device of first area I.The material of described the second functional layer 213b is one or more combinations in titanium nitride, tantalum nitride, titanium aluminide or tantalum, but the material of described the second functional layer 213b is different from the material of described the first functional layer 213a, for regulating the work function of the semiconductor device of second area II.In an embodiment of the present invention, the material of described the first functional layer 213a is titanium nitride, and for regulating the work function of NMOS pipe, the material of described the second functional layer 213b is the combination of titanium aluminide and tantalum, for regulating the work function of PMOS pipe.
Described the first aluminium lamination 217a is used to form the metal gates of the semiconductor device of first area I, and described the second aluminium lamination 217b is used to form the metal gates of the semiconductor device of second area II.For protecting the first aluminium lamination 217a and the second aluminium lamination 217b not oxidized; and it is not damaged in subsequent technique; thickness difference the first opening of described the first aluminium lamination 217a and the second aluminium lamination 217b and the degree of depth of the second opening; be described the first aluminium lamination 217a and the second aluminium lamination 217b surface lower than described insulating barrier 207 surfaces, be beneficial to follow-up formation the first metal silicide layer 221a and the second metal silicide layer 221b.Described the first aluminium lamination 217a and the second aluminium lamination 217b are mono-crystalline structures, and durability and mechanical strength are high.More associated description about the first aluminium lamination 217a and the second aluminium lamination 217b please refer to the description of relevant aluminium lamination in the first embodiment.
Described the first metal silicide layer 221a is not oxidized for the protection of the aluminium on the first aluminium lamination 217a surface, and in subsequent technique, protects the first aluminium lamination 217a not damaged.Described the second metal silicide layer 221b is not oxidized for the protection of the aluminium on the second aluminium lamination 217b surface, and in subsequent technique, protects the second aluminium lamination 217b not damaged.In an embodiment of the present invention, for better protecting the first aluminium lamination 217a and the second aluminium lamination 217b, the thickness of described the first metal silicide layer 221a and the second metal silicide layer 221b is 10 dust-300 dusts.
The semiconductor device that the embodiment of the present invention forms, owing to thering is the first functional layer and the second functional layer, not only can effectively regulate the work function of the semiconductor device of regional, and the quality of the metal gates of the aluminum of each region semiconductor device is good, inside does not almost have defect, and be mono-crystalline structures, good endurance, mechanical strength is high.And owing to there being the protection of metal silicide layer, the aluminium on the metal gates surface of described aluminum is difficult for oxidized, and subsequent technique metal gates is not fragile yet, and the performance of semiconductor device is more stable.
To sum up, first form the aluminium film that covers described polysilicon layer surface and the metal level that covers described aluminium film, follow-up while carrying out annealing in process, aluminium in described aluminium film enters open bottom, formation is positioned at the aluminium lamination of described semiconductor substrate surface, and the quality of described aluminium lamination is good, and inside does not have hole, and be mono-crystalline structures, mechanical endurance is good.Polysilicon in polysilicon electrode layer upwards shifts simultaneously; with the metal level formation metal silicide layer that reacts; saved processing step; and the follow-up aluminium on aluminium lamination surface of can protecting of metal silicide layer forming is not oxidized; and in subsequent technique, avoided aluminium lamination to be damaged, the stable performance of the semiconductor device of formation.
Because the aluminium lamination surface coverage of semiconductor device has metal silicide layer, described aluminium lamination is difficult for oxidized, and has avoided aluminium lamination to damage in subsequent technique, the quality of described aluminium lamination is good, and described aluminium lamination is mono-crystalline structures, and its durability and mechanical strength are high, the stable performance of semiconductor device.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.

Claims (16)

1. a formation method for semiconductor device, is characterized in that, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface is formed with insulating barrier, has the opening that runs through its thickness in described insulating barrier, is formed with the polysilicon electrode layer flushing with described surface of insulating layer in described opening;
Form the aluminium film that covers described Semiconductor substrate and polysilicon electrode layer surface;
Form the metal level that covers described aluminium film;
The said structure forming after metal level is carried out to annealing in process, make the aluminium in described aluminium film enter the alternative polysilicon electrode layer of open bottom, formation is positioned at the aluminium lamination of described semiconductor substrate surface, and polysilicon in polysilicon electrode layer is transferred to open top, and reacts and form the metal silicide layer that is positioned at described aluminium lamination surface with metal level;
Chemico-mechanical polishing is positioned at metal level, aluminium film, the metal silicide layer of described semiconductor substrate surface, until expose described surface of insulating layer.
2. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the process parameters range of described annealing in process is: annealing temperature is 400 degrees Celsius-600 degrees Celsius, and annealing time is 30 minutes-450 minutes.
3. the formation method of semiconductor device as claimed in claim 2, is characterized in that, annealing temperature during described annealing in process is 480 degrees Celsius-520 degrees Celsius.
4. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the material of described metal level is titanium, cobalt or nickel.
5. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the thickness of described aluminium film is 100 dust-500 dusts.
6. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the formation technique of described aluminium film is physical gas-phase deposition, and its process parameters range is: the pressure of deposition chambers is 1 millitorr-10 millitorr, and depositing temperature is 400 degrees Celsius-600 degrees Celsius.
7. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the material of described metal silicide layer is titanizing silicon, cobalt SiClx or nickel SiClx.
8. the formation method of semiconductor device as claimed in claim 1, is characterized in that, after chemico-mechanical polishing, the thickness of the metal silicide layer in described opening is 10 dust-300 dusts.
9. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the depth-to-width ratio of described opening is greater than 8, and the formation technique of described polysilicon electrode layer is chemical vapor deposition method.
10. the formation method of semiconductor device as claimed in claim 1, is characterized in that, is also formed with high-K gate dielectric layer in described opening, and described polysilicon electrode layer covers described high-K gate dielectric layer surface.
The formation method of 11. semiconductor device as claimed in claim 10, is characterized in that, is also formed with functional layer in described opening, and described functional layer is formed at described high K dielectric layer and polysilicon electrode interlayer.
12. 1 kinds of semiconductor device, is characterized in that, comprising:
Semiconductor substrate;
Be positioned at the insulating barrier of described semiconductor substrate surface;
The opening that runs through described thickness of insulating layer;
The semiconductor substrate surface of described open bottom has aluminium lamination;
Described aluminium lamination surface is formed with metal silicide layer, and described metal silicified layer surface flushes with described surface of insulating layer.
13. semiconductor device as claimed in claim 12, is characterized in that, the material of described metal silicide layer is titanizing silicon, cobalt SiClx or nickel SiClx.
14. semiconductor device as claimed in claim 12, is characterized in that, the thickness of described metal silicide layer is 10 dust-300 dusts.
15. semiconductor device as claimed in claim 12, is characterized in that, also comprise: the semiconductor substrate surface high-K gate dielectric layer that is positioned at described open bottom.
16. semiconductor device as claimed in claim 12, is characterized in that, also comprise: the functional layer between described high-K gate dielectric layer and aluminium lamination.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11261063A (en) * 1998-03-16 1999-09-24 Toshiba Corp Manufacture of semiconductor device
US6103559A (en) * 1999-03-30 2000-08-15 Amd, Inc. (Advanced Micro Devices) Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication
US20090174003A1 (en) * 2007-11-13 2009-07-09 Interuniversitair Microelektronica Centrum Vzw (Imec) Dual work function device with stressor layer and method for manufacturing the same
US20110171820A1 (en) * 2010-01-14 2011-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a metal gate
CN102214608A (en) * 2010-04-09 2011-10-12 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11261063A (en) * 1998-03-16 1999-09-24 Toshiba Corp Manufacture of semiconductor device
US6103559A (en) * 1999-03-30 2000-08-15 Amd, Inc. (Advanced Micro Devices) Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication
US20090174003A1 (en) * 2007-11-13 2009-07-09 Interuniversitair Microelektronica Centrum Vzw (Imec) Dual work function device with stressor layer and method for manufacturing the same
US20110171820A1 (en) * 2010-01-14 2011-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a metal gate
CN102214608A (en) * 2010-04-09 2011-10-12 中国科学院微电子研究所 Semiconductor device and manufacturing method thereof

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