CN103545179B - Semiconductor devices and forming method thereof - Google Patents

Semiconductor devices and forming method thereof Download PDF

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Publication number
CN103545179B
CN103545179B CN201210238596.XA CN201210238596A CN103545179B CN 103545179 B CN103545179 B CN 103545179B CN 201210238596 A CN201210238596 A CN 201210238596A CN 103545179 B CN103545179 B CN 103545179B
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layer
aluminium
semiconductor devices
electrode layer
semiconductor substrate
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CN103545179A (en
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洪中山
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement

Abstract

A kind of semiconductor devices and forming method thereof, wherein, the formation method of semiconductor devices, comprise: Semiconductor substrate is provided, semiconductor substrate surface is formed with insulating barrier, has the opening that runs through its thickness in insulating barrier, is formed with the polysilicon electrode layer flushing with surface of insulating layer in opening; Form the aluminium film that covers Semiconductor substrate and polysilicon electrode layer surface; Form the metal level of aluminium coating film; The said structure forming after metal level is carried out to annealing in process, make the aluminium in aluminium film enter the alternative polysilicon electrode layer of open bottom, formation is positioned at the aluminium lamination of semiconductor substrate surface, and polysilicon in polysilicon electrode layer is transferred to open top, and reacts and form the metal silicide layer that is positioned at aluminium lamination surface with metal level; Chemically mechanical polishing is positioned at metal level, aluminium film, the metal silicide layer of described semiconductor substrate surface, until expose described surface of insulating layer. The stable performance of the semiconductor devices forming.

Description

Semiconductor devices and forming method thereof
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of semiconductor devices and formation side thereofMethod.
Background technology
Along with the fast development of ic manufacturing technology, impel the semiconductor devices in integrated circuit, outstandingIt is MOS(MetalOxideSemiconductor, Metal-oxide-semicondutor) size of device is notDwindle disconnectedly, meet the miniaturization of integrated circuit development and integrated requirement with this. At MOS transistorIn the process that the size of device continues to dwindle, existing technique is using silica or silicon oxynitride as gate dielectric layerTechnique be subject to challenge. Occur as the transistor that gate dielectric layer was formed using silica or silicon oxynitrideSome problems, comprise that leakage current increases and the diffusion of impurity, thereby affect transistorized threshold voltage,And then affect the performance of semiconductor devices.
For overcoming the above problems, adopt metal to be suggested as the transistor of grid. Described have a metal gateThe transistor of the utmost point adopts high K(dielectric constant) material replaces conventional silica or silicon oxynitride gate medium materialMaterial, when can making transistor size dwindle, reduces the generation of leakage current, and improves transistorized propertyEnergy.
Prior art forms the transistorized method with metal gates, comprising:
Please refer to Fig. 1, Semiconductor substrate 10 is provided; Form oxide layer 11 on described Semiconductor substrate 10 surfaces; ?Described oxide layer 11 surfaces form high K dielectric layer 12; Form protective layer on described high K dielectric layer 12 surface13, the material of described protective layer 13 is titanium nitride or tantalum nitride; Form pseudo-grid on described protective layer 13 surfacesUtmost point layer 14.
Please refer to Fig. 2, taking described dummy gate layer 14 as protective layer described in mask etching 13, high K dielectric layer 12With oxide layer 11, form protective layer 13a, high K dielectric layer 12a and oxide layer 11a.
Please refer to Fig. 3, form side wall 15 on Semiconductor substrate 10 surfaces of described dummy gate layer 14 both sides.
Please refer to Fig. 4, at described dummy gate layer 14(as Fig. 3) and the Semiconductor substrate 10 of side wall 15 both sidesInterior formation source/drain region 16; Forming behind source/drain region 16, forming mask layer 18 on Semiconductor substrate 10 surfaces,Described mask layer 18 upper surfaces flush with dummy gate layer 14 tops; Taking described mask layer 18 as mask, removeDescribed dummy gate layer 14, forms opening 17.
It should be noted that, behind formation source/drain region 16, carry out thermal annealing, activate described source/drain region 16.Please refer to Fig. 5, at described opening 17(as Fig. 4) in fill full metal, form metal gate electrode layer 19,Described metal gate electrode layer 19 upper surfaces flush with the top of described mask layer 18.
But the performance of semiconductor devices that prior art forms is still stable not, have partly leadThe formation method of body device please refer to the U.S. patent documents that publication number is US2009/0142899A1.
Summary of the invention
The problem that the present invention solves is to provide semiconductor devices of a kind of stable performance and forming method thereof.For addressing the above problem, embodiments of the invention provide a kind of formation method of semiconductor devices, comprising:Semiconductor substrate is provided, and described semiconductor substrate surface is formed with insulating barrier, in described insulating barrier, has and passes throughWear the opening of its thickness, in described opening, be formed with the polysilicon electrode layer flushing with described surface of insulating layer;Form the aluminium film that covers described Semiconductor substrate and polysilicon electrode layer surface; Form the described aluminium of covering thinThe metal level of film; The said structure forming after metal level is carried out to annealing in process, make in described aluminium filmAluminium enters open bottom and substitutes polysilicon electrode layer, forms the aluminium lamination that is positioned at described semiconductor substrate surface,And polysilicon in polysilicon electrode layer is transferred to open top, and reacts to form with metal level and be positioned atThe metal silicide layer on described aluminium lamination surface; Chemically mechanical polishing is positioned at the gold of described semiconductor substrate surfaceBelong to layer, aluminium film, metal silicide layer, until expose described surface of insulating layer.
Alternatively, the process parameters range of described annealing in process is: annealing temperature is 400 degrees Celsius-600Degree Celsius, annealing time is 30 minutes-450 minutes.
Alternatively, annealing temperature when described annealing in process is 480 degrees Celsius-520 degrees Celsius.
Alternatively, the material of described metal level is titanium, cobalt or nickel.
Alternatively, the thickness of described aluminium film is 100 dust-500 dusts.
Alternatively, the formation technique of described aluminium film is physical gas-phase deposition, its process parameters rangeFor: the pressure of deposition chambers is 1 millitorr-10 millitorr, and depositing temperature is 400 degrees Celsius-600 degrees Celsius.
Alternatively, the material of described metal silicide layer is titanizing silicon, cobalt SiClx or nickel SiClx.
Alternatively, after chemically mechanical polishing, the thickness of the metal silicide layer in described opening is 10 dust-300Dust.
Alternatively, the depth-to-width ratio of described opening is greater than 8, and the formation technique of described polysilicon electrode layer is chemistryGas-phase deposition.
Alternatively, be also formed with high-K gate dielectric layer in described opening, described polysilicon electrode layer covers instituteState high-K gate dielectric layer surface.
Alternatively, be also formed with functional layer in described opening, described functional layer is formed at described high K grid and is situated betweenMatter layer and polysilicon electrode interlayer.
Accordingly, inventor also provides a kind of semiconductor devices, comprising: Semiconductor substrate; Be positioned at instituteState the insulating barrier of semiconductor substrate surface; Run through the opening of described thickness of insulating layer; Described open bottomSemiconductor substrate surface has aluminium lamination; Described aluminium lamination surface is formed with metal silicide layer, described metallic siliconChanging layer surface flushes with described surface of insulating layer.
Alternatively, the material of described metal silicide layer is titanizing silicon, cobalt SiClx or nickel SiClx.
Alternatively, the thickness of described metal silicide layer is 10 dust-300 dusts.
Alternatively, also comprise: the semiconductor substrate surface high-K gate dielectric layer that is positioned at described open bottom.
Alternatively, also comprise: the functional layer between described high-K gate dielectric layer and aluminium lamination.
Compared with prior art, technical scheme of the present invention has the following advantages:
First form the aluminium film that covers described polysilicon layer surface and the metal level that covers described aluminium film,Follow-up while carrying out annealing in process, the aluminium in described aluminium film enters open bottom, forms to be positioned at describedly partly to leadThe aluminium lamination of body substrate surface, the quality of described aluminium lamination is good, and inside does not have hole, and is mono-crystalline structures, machineTool good endurance. Simultaneously the polysilicon in polysilicon electrode layer upwards shifts, with the metal level shape that reactsBecome metal silicide layer, saved processing step, and follow-up can the protection of metal silicide layer formingThe aluminium on aluminium lamination surface is not oxidized, and in subsequent technique, has avoided aluminium lamination to be damaged, the semiconductor of formationThe stable performance of device.
Because the aluminium lamination surface coverage of semiconductor devices has metal silicide layer, described aluminium lamination is difficult for oxidized,And avoided aluminium lamination to damage in subsequent technique, the quality of described aluminium lamination is good, and described aluminium lamination is monocrystallineStructure, its durability and mechanical strength are high, the stable performance of semiconductor devices.
Brief description of the drawings
Fig. 1-Fig. 5 is the cross-sectional view of the forming process of prior art semiconductor devices;
Fig. 6-Figure 10 is the cross-section structure signal of the forming process of the semiconductor devices of first embodiment of the inventionFigure;
Figure 11-Figure 17 is the cross-section structure signal of the forming process of the semiconductor devices of second embodiment of the inventionFigure.
Detailed description of the invention
The performance of the semiconductor devices that as described in background, prior art forms is stable not.
Find through research, along with the size of semiconductor devices is constantly dwindled, form described semiconductor deviceIn the process of part, please refer to Fig. 4, the depth-to-width ratio of removing the opening 17 forming after dummy gate layer increases gradually,During to the interior filling metal material of described opening 17, can meet difficulty, especially work as the depth-to-width ratio of described opening 17Be greater than at 7 o'clock, the metal gate electrode layer 19(of formation is as shown in Figure 5) there is more defect in inside. For exampleThe interior hole that exists of metal gate electrode layer 19, has had a strong impact on the performance of semiconductor devices.
After further research, inventor finds that a kind of aluminium that adopts substitutes polysilicon(polysilicon-auluminumsubstitute) technology. Under annealing process, be positioned at polysilicon electrodeThe aluminium on layer surface can enter into open bottom, and the polysilicon electrode layer that is positioned at described opening originally turnsMove to open top, the content that is formed on polysilicon in the aluminium lamination of open bottom after described annealing process is few(being less than or equal to 0.4%), can not destroy the performance of semiconductor devices. And, described aluminium lamination after annealing processInside have hardly hole, and described aluminium lamination is mono-crystalline structures, its mechanical endurance can be better, contributes toThe semiconductor devices that follow-up forming property is superior.
Further, inventor's discovery, the aluminium that is used as the aluminium lamination surface of grid after annealing process is exposed toVery easily oxidized in air, and easily destroyed in follow-up glossing, need to be at described aluminium filmSurface forms layer protective layer, to avoid aluminium lamination surface oxidized, and protects aluminium lamination not damaged.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawingThe specific embodiment of the present invention is described in detail.
The first embodiment
In the first embodiment of the present invention, carry out as an example of the forming process of the metal gates of semiconductor devices exampleExemplary illustrated.
Please refer to Fig. 6, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 surface coverage have interfaceFilm 101, described interfacial film 101 surface coverage have high K dielectric film 103, described high K dielectricFilm 103 surface coverage have polysilicon membrane 105, and described polysilicon membrane 105 surfaces are formed with photoresistLayer 107, described photoresist layer 107 has the figure (not indicating) that defines grid.
Described Semiconductor substrate 100 is used to subsequent technique that workbench is provided. Described Semiconductor substrate 100For body silicon or silicon-on-insulator (SOI), the material of described Semiconductor substrate 100 be monocrystalline silicon, SiGe,Silicon-carbon or III-V compounds of group (such as gallium arsenic, indium phosphide and gallium nitride etc.). Embodiments of the inventionIn, in described Semiconductor substrate 100, be also formed with fleet plough groove isolation structure 102, adjacent for follow-up isolationMetal-oxide-semiconductor.
The material of described interfacial film 101 is silica, for follow-up formation boundary layer, reduces the first high KInterface resistance between dielectric layer and Semiconductor substrate 100. The formation technique of described interfacial film 101 isDepositing operation, for example physics or chemical vapor deposition method.
Described high K dielectric film 103 is for follow-up formation high K dielectric layer, isolation of semiconductor substrate 100And metal gate electrode layer. The material of described high K dielectric film 103 is HfO2, HfSiO, HfSiNO orZrO2Deng. The formation technique of described high K dielectric film 103 is depositing operation, for example physics or chemical gasPhase depositing operation.
Described polysilicon membrane 105 is the polysilicon electrode layer as pseudo-grid for follow-up formation. Described polycrystallineThe formation technique of silicon thin film 105 is depositing operation, for example physics or chemical vapor deposition method. At thisIn bright embodiment, the thickness of described polysilicon membrane 105 is 400 dust-800 dusts.
Described photoresist layer 107 is for as mask, polysilicon membrane 105, high K described in etching successivelyDielectric film 103, interfacial film 101. Because the technique that forms described photoresist layer 107 has been this areaTechnical staff knows, and does not repeat them here.
It should be noted that, in other embodiments of the invention, described Semiconductor substrate 100 surfaces canTo be only formed with high-K medium film 103; Or be formed with interfacial film in described Semiconductor substrate 100101, be positioned at the high-K medium film 103 on described interfacial film 101 surfaces and be positioned at described high k JieThe function film (not shown) on matter film 103 surfaces, described function film is for follow-up formation semiconductor deviceThe functional layer of part, adjusts the work function of described semiconductor devices.
Please refer to Fig. 7, taking described photoresist layer 107(as shown in Figure 6) as mask, successively described in etchingPolysilicon membrane 105(is as shown in Figure 6), high K dielectric film 103(as shown in Figure 6), interfacial film101(is as shown in Figure 6), form polysilicon electrode layer 105a, high K dielectric layer 103a, boundary layer 101a;Forming after polysilicon electrode layer 105a, high K dielectric layer 103a, boundary layer 101a, partly lead describedBody substrate 100 surfaces form the insulating barrier 109 with described polysilicon electrode layer 105a flush.
Described in etching, the technique of polysilicon membrane 105, high K dielectric film 103, interfacial film 101 is eachHeterotropic etching technics, for example dry etch process. Due to polysilicon membrane 105 described in described etching,The technique of high K dielectric film 103, interfacial film 101 is well known to those skilled in the art, at thisRepeat no more.
Described polysilicon electrode layer 105a forms after by described polysilicon electrode film 105 etchings, described manyThe thickness of crystal silicon electrode layer 105a is identical with the thickness of described polysilicon electrode film 105. Of the present inventionIn embodiment, the thickness of described polysilicon electrode layer 105a is 300 dust-700 dusts.
Described insulating barrier 109 is for isolating the grid of adjacent semiconductor device. The material of described insulating barrier 109Material is silica, silicon nitride or silicon oxynitride. The formation technique of described insulating barrier 109 is depositing operation,For example physics or chemical vapor deposition method. In an embodiment of the present invention, the material of described insulating barrier 109Material is silica, and its formation method is: adopt ethyl orthosilicate (TEOS) and ozone to react.
In an embodiment of the present invention, for making semiconductor in subsequent chemical-mechanical polishing technique or etching technicsSubstrate 100 is not destroyed, and also comprises: forming before insulating barrier 109, form and cover described polysilicon layerThe etching barrier layer 111 of 105a and Semiconductor substrate 100. The material of described etching barrier layer 111 is nitrogenizeSilicon, it forms technique is chemical vapor deposition method.
It should be noted that, chemical polishing form with described polysilicon electrode layer 105a flush absolutelyWhen edge layer 109, etching barrier layer 111 and the photoresist layer 107 at described polysilicon electrode layer 105a topAlso can be removed.
Please refer to Fig. 8, the aluminium that forms the described insulating barrier 109 of covering and polysilicon electrode layer 105a surface is thinFilm 113; Form the metal level 115 that covers described aluminium film 113 surfaces.
Inventor finds, adopts aluminium to substitute the skill of polysilicon (polysilicon-auluminumsubstitute)Art, under annealing process, the aluminium that is positioned at polysilicon electrode layer 105a surface can enter into opening (this enforcementIn example, corresponding to the position of polysilicon electrode layer 105a, do not indicate) bottom, and be positioned at described high k originallyThe polysilicon electrode layer 105a on dielectric layer 103a surface is transferred to open top.
Described aluminium film 113 is replaced and is positioned at the many of described high K medium layer 103a surface for subsequent techniqueCrystal silicon electrode layer 105a. For only opening described in filling part of the aluminium lamination that makes to form after subsequent anneal technique, shapeThe thinner thickness of the described aluminium film 113 becoming, preferably, the thickness of described aluminium film 113 is polysilicon300 dust-700 dusts of the thickness of electrode layer 105a. In an embodiment of the present invention, described aluminium film 113Thickness be 100 dust-500 dusts.
The formation technique of described aluminium film 113 is physical gas-phase deposition, and its process parameters range is:The pressure of deposition chambers is 1 millitorr-10 millitorr, and depositing temperature is 400 degrees Celsius-600 degrees Celsius. At thisIn inventive embodiment, the technological parameter while adopting gas-phase deposition to form described aluminium film 113 is:The pressure of deposition chambers is 8 millitorrs, and depositing temperature is 500 degrees Celsius.
Inventor's discovery, after subsequent anneal technique, the aluminium that is used as the aluminium lamination surface of grid is exposed in airVery easily oxidized, and easily destroyed in follow-up glossing, need to be described aluminium film surface shapeBecome layer protective layer, to avoid aluminium lamination surface oxidized, and protect aluminium lamination not damaged.
Further, inventor also finds, polysilicon when subsequent anneal technique in polysilicon layer constantly byBottom is transferred to top, described in be transferred to top polysilicon annealing temperature just in time can with metal level 115React, generate metal silicide layer, using as protection aluminium lamination not oxidized protective layer. Therefore,Can, first at aluminium film 113 forming metal layer on surfaces 115, when follow-up formation aluminium lamination, also form and coverThe metal silicide layer on described aluminium lamination surface, has effectively saved processing step.
Described metal level 115 occurs with the polysilicon layer that is transferred to open top during for subsequent anneal techniqueReaction, forms metal silicide layer. After deliberation find, the material of described metal level 115 be titanium (Ti),When cobalt (Co) or nickel (Ni), the better effects if of the metal silicide layer protection aluminium lamination of follow-up formation. ?In embodiments of the invention, the material of described metal level 115 is titanium, forms the shape of described metal level 115One-tenth technique is physical gas-phase deposition.
Please refer to Fig. 9, the said structure forming after metal level 115 is carried out to annealing in process, make described aluminium thinAluminium in film 113 enters open bottom and substitutes polysilicon electrode layer 105a(as shown in Figure 8), formation is positioned atThe aluminium lamination 113a on described Semiconductor substrate 100 surfaces, and polysilicon in polysilicon electrode layer 105a shiftsTo open top, and react and form the metallic silicon that is positioned at described aluminium lamination 113a surface with metal level 115Compound layer 117.
Described annealing in process is used to form aluminium lamination 113a and metal silicide layer 117. Described annealing in processProcess parameters range is: annealing temperature is 400 degrees Celsius-600 degrees Celsius, and annealing time is 30 minutes-450Minute. In an embodiment of the present invention, the technological parameter of described annealing in process is: annealing temperature is 480Degrees Celsius-520 degrees Celsius, be preferably 500 degrees Celsius, annealing time is 60 minutes. This technological parameterUnder, the better quality of the aluminium lamination 113a of formation, described aluminium lamination 113a inside does not almost have defect, and manyCrystal silicon electrode layer 105a is almost all transferred to open top, and the polysilicon content in aluminium lamination 113a is minimum,Its mass percent is less than 0.4%.
Because the thickness of aluminium film 113 is lower than the thickness of polysilicon electrode layer 105a, the aluminium lamination 113a of formationSurface is lower than described open surfaces. In embodiments of the invention, the thickness of the aluminium lamination 113a of formation is 300Dust-700 dust.
Described metal silicide layer 117 is follow-up for the protective layer as aluminium lamination 113a, protects on the one hand aluminiumThe aluminium on layer 113a surface is not oxidized, protects on the other hand aluminium in subsequent etching or CMP processLayer 113a avoids destroying. Because described metal silicide layer 117 is the polycrystalline in polysilicon electrode layer 105aAfter being transferred to open top and metal level 115 and reacting, silicon forms, described metal silicide layer 117Material is titanizing silicon, cobalt SiClx or nickel SiClx. In an embodiment of the present invention, described metal silicide layer117 material is titanizing silicon.
Please refer to Figure 10, chemically mechanical polishing is positioned at the metal level 115 on described Semiconductor substrate 100 surfaces(as shown in Figure 9), aluminium film 113(is as shown in Figure 9) and metal silicide layer 117(as Fig. 9 instituteShow), until expose described insulating barrier 109 surfaces.
Speed while considering chemically mechanical polishing metal level 115 and aluminium film 113 is greater than chemical machinery and throwsSpeed when light metal silicide layer 117. In an example of the present invention, first adopt H2O2WithThe chemical reagent wet etching of HCl is removed metal level 115 and aluminium film 113, then adopts chemical machinery to throwThe method of light is removed described metal silicide layer 117. In another example of the present invention, also can be divided intoTwo step chemically mechanical polishings, first step chemically mechanical polishing adopts and comprises H2O2With the grinding reagent of HCl,The metal silicide layer of removing metal level 115 and aluminium film 113 and segment thickness, then adopts etching goldBelong to when silicide layer 117 speed and grind faster reagent and carry out second step chemically mechanical polishing, until exposeGo out insulating barrier 109 surfaces.
Because described aluminium lamination 113a surface is lower than described open surfaces, lower than described insulating barrier 111 surfaces.Therefore after chemically mechanical polishing, described aluminium lamination 113a surface also has metal silicide layer 117a, described surplusThe thickness of remaining metal silicide layer 117a is 10 dust-300 dusts, can play the work of protection aluminium lamination 113aWith.
It should be noted that, in other embodiments of the invention, except being used to form grid structureDue to larger for the depth-to-width ratio of filling the jack that forms conductive plunger, also can first adopt chemical gas outward,The technique of deposition first forms polysilicon layer in jack mutually; Then formation covers insulating barrier and polysilicon layerAluminium film; Form the metal level that covers described aluminium film surface; Then carry out annealing in process, make described aluminiumPolysilicon in aluminium and jack in film is replaced, and finally forms the conductive plunger of aluminium material. Due to describedThe conductive plunger inside of aluminium material does not almost have cavity, and is mono-crystalline structures, and the conduction of described aluminium material is insertedThe quality of plug is good, stable performance.
After above-mentioned steps completes, the completing of the semiconductor devices of first embodiment of the invention. FirstForm the aluminium film that covers described polysilicon layer surface and the metal level that covers described aluminium film, follow-up carrying outWhen annealing in process, the aluminium in described aluminium film enters open bottom, forms and is positioned at described Semiconductor substrate tableThe aluminium lamination of face, the quality of described aluminium lamination is good, and inside does not have hole, and is mono-crystalline structures, mechanical enduranceGood. Simultaneously the polysilicon in polysilicon electrode layer upwards shifts, with the metal level formation metallic silicon that reactsCompound layer, has saved processing step, and the metal silicide layer forming follow-uply can be protected aluminium lamination surfaceAluminium not oxidized, and in subsequent technique, avoided aluminium lamination to be damaged, the property of the semiconductor devices of formationCan be stable.
Accordingly, please continue to refer to Figure 10, inventor also provides a kind of semiconductor devices, comprising:
Semiconductor substrate 100;
Be positioned at the insulating barrier 109 on described Semiconductor substrate 100 surfaces;
Run through the opening (not indicating) of described insulating barrier 109 thickness;
Semiconductor substrate 100 surfaces of described open bottom have aluminium lamination 113a;
Described aluminium lamination 113a surface is formed with metal silicide layer 117a, described metal silicified layer 117a tableFace and described insulating barrier 109 flush.
Wherein, described Semiconductor substrate 100 is for the workbench as subsequent technique. Described semiconductorSubstrate 100 is body silicon or silicon-on-insulator (SOI), the material of described Semiconductor substrate 100 be monocrystalline silicon,SiGe, silicon-carbon or III-V compounds of group (such as gallium arsenic, indium phosphide and gallium nitride etc.). Of the present inventionIn embodiment, in described Semiconductor substrate 100, be also formed with fleet plough groove isolation structure 102, for follow-up everyFrom adjacent metal-oxide-semiconductor.
Described insulating barrier 109 is for isolating the grid of adjacent semiconductor device. The material of described insulating barrier 109Material is silica, silicon nitride or silicon oxynitride. In an embodiment of the present invention, described insulating barrier 109Material is oxygen silica.
Described opening forms the conduction of metal gate electrode layer or interconnection structure and inserts for filling aluminium lamination 113aPlug. Even if the depth-to-width ratio of described opening is greater than at 7 o'clock, described aluminium lamination 113a is still mono-crystalline structures, durablePerformance is good, and mechanical strength is high, and internal defects is few, and quality is good. For making described aluminium lamination 113a follow-upIn technique, be not destroyed, follow-uply also can form protective layer, therefore described aluminium lamination on described aluminium lamination 113a surfaceThe thickness of 113a is little compared with the degree of depth of described opening, and described aluminium lamination 113a surface is lower than described insulating barrier 111Surface.
It should be noted that, in the time that described aluminium lamination 113a is used as formation metal gate electrode layer, described semiconductorDevice also comprises: the surperficial high K medium layer of Semiconductor substrate 100 103a that is positioned at described opening. AndIn order to reduce the interface resistance between described high K dielectric layer 103a and Semiconductor substrate 100, describedly partly leadBody device also comprises: the boundary layer 101a between described high K medium layer 103a and Semiconductor substrate.
It should be noted that, the forming process of described aluminium lamination 113a please refer to the formation of aforesaid semiconductor deviceMethod, does not repeat them here.
Described metal silicide layer 117a, for the protective layer as aluminium lamination 113a, protects aluminium lamination on the one handThe aluminium on 113a surface is not oxidized, protects on the other hand aluminium lamination in subsequent etching or CMP process113a avoids destroying. The material of described metal silicide layer 117a is titanizing silicon, cobalt SiClx or nickel SiClx.In an embodiment of the present invention, the material of described metal silicide layer 117a is titanizing silicon, described metallic siliconThe thickness of compound layer 117a is 10 dust-300 dusts, can play the effect of protection aluminium lamination 113a.
The structure of the aluminium lamination of the semiconductor devices of first embodiment of the invention is mono-crystalline structures, described monocrystalline knotThe aluminium lamination durability of structure is stronger, and the mechanical strength of the semiconductor devices of formation is high, and semiconductor devices is providedStability. And, because the aluminium on described aluminium lamination surface has metal silicide layer protection, avoided its tableFace aluminium is oxidized, has also protected aluminium lamination in subsequent etching or CMP process to avoid destroying, and partly leadsThe performance of body device is more stable.
The second embodiment
Slightly different from the first embodiment of the present invention, in second embodiment of the invention, to form CMOSPipe carries out exemplary illustrated for example, and forms and gain merit between described high K medium layer and polysilicon electrode layerErgosphere, for the work function of subsequent adjustment semiconductor devices.
Please refer to Figure 11, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 comprises first area IAdjacent second area II with it, Semiconductor substrate 200 surfaces of described first area I are formed with successivelyThe first boundary layer 201a, be positioned at the first high K medium layer 203a, the position on described the first boundary layer 201a surfaceIn the first pseudo-gate electrode layer 205a on described the first high K medium layer 203a surface, described second area IISemiconductor substrate 200 surfaces be formed with successively second contact surface layer 201b, be positioned at described second contact surface layerThe second high K medium layer 203b on 201b surface, be positioned at of described the second high K medium layer 203b surfaceTwo pseudo-gate electrode layer 205b, and described Semiconductor substrate 200 surfaces are also formed with insulating barrier 207, described inInsulating barrier 207 surfaces are neat with described the first pseudo-gate electrode layer 205a and the second pseudo-gate electrode layer 205b surfaceFlat.
Wherein, described Semiconductor substrate 200 is used to subsequent technique that workbench is provided. Described semiconductorSubstrate 200 is body silicon or silicon-on-insulator (SOI), the material of described Semiconductor substrate 200 be monocrystalline silicon,SiGe, silicon-carbon or III-V compounds of group (such as gallium arsenic, indium phosphide and gallium nitride etc.). Of the present inventionIn embodiment, in described Semiconductor substrate 200, be also formed with fleet plough groove isolation structure 202, for follow-up everyFrom region.
In an embodiment of the present invention, first area I is used to form NMOS pipe, described second area IIBe used to form PMOS pipe.
It should be noted that, in other embodiments of the invention, can also be: described first area IBe used to form PMOS pipe, described second area II is for NMOS pipe.
Described the first boundary layer 201a is for reducing the first high K dielectric layer 203a and Semiconductor substrate 200Between interface resistance, described second contact surface layer 201b is for reducing the second high K dielectric layer 203b and halfInterface resistance between conductive substrate 200. In an embodiment of the present invention, described the first boundary layer 201aIdentical with the material of second contact surface layer 201b, be silica. More about the first boundary layer 201a andThe formation technology and step of boundary layer 201b please refer to relevant the retouching of first embodiment of the invention median surface layerState, do not repeat them here.
The Semiconductor substrate 200 and first of described the first high K medium layer 203a for isolating first area IPseudo-gate electrode layer 205a, the material of described the first high K medium layer 203a is HfO2、HfSiO、HfSiNOOr ZrO2Deng. The Semiconductor substrate 200 of described the second high K medium layer 203b for isolating second area IIWith the second pseudo-gate electrode layer 205b, the material of described the second high K medium layer 203b is HfO2、HfSiO、HfSiNO or ZrO2Deng. In an embodiment of the present invention, described the first high K medium layer 203a and secondThe material of high K medium layer 203b is identical, is ZrO2. More about the first high K medium layer 203a andThe associated description of the second high K medium layer 203b please refer to the phase of high K medium layer in first embodiment of the inventionClose and describe, do not repeat them here.
Described the first pseudo-gate electrode layer 205a forms the first opening, described the second pseudo-grid for follow-up being removedElectrode layer 205b forms the second opening for follow-up being removed. In the second embodiment of the present invention, described inThe material of the first pseudo-gate electrode layer 205a and described the second pseudo-gate electrode layer 205b is polysilicon.
It should be noted that the material of described the first pseudo-gate electrode layer 205a and the second pseudo-gate electrode layer 205bMaterial can also be other materials, easily removes as long as follow-up.
Described insulating barrier 207 is for isolating the grid in adjacent two regions. The material of described insulating barrier 207For silica, silicon nitride or silicon oxynitride. In an embodiment of the present invention, described insulating barrier 207 forIsolation the first metal gate electrode of first area I and the second metal gate electrode of second area II, described exhaustedThe material of edge layer 207 is silica. More associated description about described insulating barrier 207 please refer to thisThe first bright embodiment.
It should be noted that, in subsequent technique, protect described insulating barrier 207 and Semiconductor substrate 200,Also comprise: before forming insulating barrier 207, form and cover described the first pseudo-gate electrode layer 205a, secondThe etching barrier layer 209 of pseudo-gate electrode layer 205b and Semiconductor substrate 200, described etching barrier layer 209Material be silicon nitride, its form technique be chemical vapor deposition method. At chemically mechanical polishing insulating barrierIn 207 processing step, described etching barrier layer 209 also can be polished, and only residue is positioned at the first pseudo-grid electricityThe part on utmost point layer 205a sidewall, the second pseudo-gate electrode layer 205b sidewall and Semiconductor substrate 200 surfaces.
Please refer to Figure 12, remove the first pseudo-gate electrode layer 205a(of first area I as shown in figure 11),Form the first opening 211a.
Described the first opening 211a is for follow-up filling the first function film. The shape of described the first opening 211aBecome step to comprise: to form and cover described insulating barrier 207, etching barrier layer 209 and the second pseudo-gate electrode layerThe first photoresist layer (not shown) of 205b; Taking described the first photoresist layer as the first puppet described in mask etchingGate electrode layer 205a, until expose the first high K medium layer 203a. Wherein, the first pseudo-grid described in etchingThe technique of electrode layer 205a is anisotropic dry etch process, because this technique has been art technologyPersonnel know, and do not repeat them here.
Please refer to Figure 13, form and cover described the first opening 211a(as shown in figure 12) bottom and sidewallThe first functional layer 213a, forms the first polysilicon electrode layer 215a that covers described the first functional layer 213a,Described the first polysilicon electrode layer 215a surface and described insulating barrier 207 flush.
Described the first functional layer 213a is used for the work function of the semiconductor devices that regulates first area I. DescribedThe formation step of the first functional layer 213a comprises: form the bottom and the sidewall that cover described the first opening 211a,And the first function film of described insulating barrier 207; Described in chemically mechanical polishing, the first function film, refers toPin exposes insulating barrier 207. In the second embodiment of the present invention, the material of described the first functional layer 213aMaterial is one or more combinations in titanium nitride, tantalum nitride, titanium aluminide or tantalum, for regulating NMOS pipeWork function.
The material of described the first polysilicon electrode layer 215a is polysilicon, during for subsequent anneal by describedAluminium in the aluminium film on one polysilicon electrode layer 215a surface is replaced, in described the first opening 211a theOne functional layer 213a surface forms aluminium lamination. The formation step of described the first polysilicon electrode layer 215a comprises:Form the first polysilicon electrode film (not shown) that covers described the first functional layer 213a; Chemical machineryThe first polysilicon electrode film described in polishing, until expose insulating barrier 207.
In an embodiment of the present invention, described the first polysilicon electrode film covers described the first function film,The first polysilicon electrode film described in chemically mechanical polishing, forms after the first polysilicon electrode layer 215a, tightThen the first function film described in chemically mechanical polishing, forms the first functional layer 213a.
Please refer to Figure 14, remove described the second pseudo-gate electrode layer 205b(as shown in figure 13), form and exposeGo out the second opening 211b of described the second high K medium layer 203b.
Described the second opening 211b is for follow-up filling the second function film. Described the second opening 211b'sForming step can be with reference to the first opening 211a(as shown in figure 12) formation step, do not repeat them here.
Please refer to Figure 15, form the second functional layer that covers described the second opening 211b bottom and sidewall213b, forms the second polysilicon electrode layer 215b that covers described the second functional layer 213b, described more than secondCrystal silicon electrode layer 215b surface and described insulating barrier 207 flush.
Described the second functional layer 213b is used for the work function of the semiconductor devices that regulates second area II. At thisIn inventive embodiment, the material of described the second functional layer 213b be titanium nitride, tantalum nitride, titanium aluminide orOne or more combinations in tantalum, but the material of described the second functional layer 213b is different from described the first functionThe material of layer 213a, for regulating the work function of PMOS pipe. The formation of described the second functional layer 213bStep and technique please refer to the first functional layer 213a(above as shown in figure 13) associated description, at this notRepeat again.
The material of described the second polysilicon electrode layer 215b is polysilicon, during for subsequent anneal by describedAluminium in the aluminium film on two polysilicon electrode layer 215b surfaces is replaced, in described the second opening 211bThe second functional layer 213b surface forms aluminium lamination. More retouching about described the second polysilicon electrode layer 215bState the first polysilicon electrode layer 215a(in please refer to above as shown in figure 13) associated description, at this notRepeat again.
Please refer to Figure 16, form and cover described insulating barrier 207, the first polysilicon electrode layer 215a and secondThe aluminium film 217 of polysilicon electrode layer 215b; Form the metal level 219 that covers described aluminium film 217 surfaces.
Described aluminium film 217 is replaced the first polysilicon electrode layer 215a and more than second for follow-up and techniqueCrystal silicon electrode layer 215b. In an embodiment of the present invention, the thickness of described aluminium film 113 is 100 dust-500Dust, it forms technique is physical gas-phase deposition, process parameters range is: the pressure of deposition chambers is 1Millitorr-10 millitorr, depositing temperature is 400 degrees Celsius-600 degrees Celsius.
Described metal level 219 occurs with the polysilicon layer that is transferred to open top during for subsequent anneal techniqueReaction, forms metal silicide layer. The material of described metal level 219 is titanium (Ti), cobalt (Co) or nickel（Ni）。
More associated description about aluminium film 217 and metal level 219 please refer to first embodiment of the inventionIn associated description, do not repeat them here.
Please refer to Figure 17, the said structure that forms metal level 219 is carried out to annealing in process, make described aluminium thinFilm 217(is as shown in figure 16) in aluminium enter the first opening 211a(as shown in figure 13) bottom, substituteThe first polysilicon electrode layer 215a(is as shown in figure 16), form and be positioned at the of described the first opening 211aThe first aluminium lamination 217a on one functional layer 213a surface, the aluminium in described aluminium film enters the second opening 211b(as shown in figure 13) bottom, substitutes the second polysilicon electrode layer 215b(as shown in figure 16), form positionThe second aluminium lamination 217b on the second functional layer 213b surface in described the second opening 211b, the while firstPolysilicon in polysilicon electrode layer 215a and the second polysilicon electrode layer 215b is transferred to respectively first and opensMouth 211a and the second opening 211b top, react with metal level 219 respectively, forms and be positioned at the first aluminiumThe first metal silicide layer 221a on layer 217a surface, forms and is positioned at second of the second aluminium lamination 217b surfaceMetal silicide layer 221b.
The process parameters range of described annealing in process is: annealing temperature is 400 degrees Celsius-600 degrees Celsius,Annealing time is 30 minutes-450 minutes. In an embodiment of the present invention, the technique of described annealing in process ginsengNumber is: annealing temperature is 480 degrees Celsius-520 degrees Celsius, is preferably 500 degrees Celsius, annealing timeIt is 60 minutes. Under this technological parameter, the first aluminium lamination 217a of formation and the quality of the second aluminium lamination 217b are moreGood, described the first aluminium lamination 217a and the second aluminium lamination 217b inside almost do not have defect, and the first polycrystallinePolysilicon in silicon electrode layer 215a, the second polysilicon electrode layer 215b is almost all transferred to corresponding openingMouth top, the polysilicon content in the first aluminium lamination 217a and the second aluminium lamination 217b is minimum, its quality percentageThan being less than 0.4%.
Manyly form the first aluminium lamination 217a, the second aluminium lamination 217b, the first metal silicide about annealing in processThe formation Method and process of layer 221a and the second metal silicide layer 221b please refer to the present invention first and implementsExample, does not repeat them here.
It should be noted that, after annealing in process, also comprise: chemically mechanical polishing insulating barrier 207 surfacesAluminium film 217(as shown in figure 16), metal level 219(as shown in figure 16), segment thickness firstThe second metal silicide layer 221b of metal silicide layer 221a and segment thickness. Specifically please refer to the present inventionAssociated description in the first embodiment, does not repeat them here.
The formation method of the semiconductor devices of second embodiment of the invention, respectively at the first high k of first areaDielectric layer surface forms the first functional layer, forms the second merit on the second high K medium layer surface of second areaErgosphere, for regulating the work function of semiconductor devices, strengthens the performance of semiconductor devices. Then form and coverCover the first polysilicon electrode layer of the first functional layer, cover the second polysilicon electrode layer of the second functional layer,And the aluminium film of formation covering described the first polycrystalline electrodes layer, the second polysilicon electrode layer and insulating barrier, withAnd covering the metal level of described aluminium film surface, following adopted annealing process, replaces the aluminium in aluminium filmThe first polycrystalline electrodes layer, forms the first aluminium lamination that is positioned at the first functional layer surface, and the aluminium in aluminium film is replacedChange the second polycrystalline electrodes layer, form the second aluminium lamination that is positioned at the second functional layer surface, simultaneously the first polysiliconPolysilicon in electrode layer and the second polysilicon electrode layer is transferred to top and metal level reacts, respectivelyForm the first metal silicide layer and the second metal silicide layer. Due to the matter of the first aluminium lamination and the second aluminium laminationMeasure, inside does not almost have defect, and is mono-crystalline structures, the stable performance of the semiconductor devices of formation.
Accordingly, please continue to refer to Figure 17, inventor provides a kind of semiconductor devices, comprising:
Semiconductor substrate 200, described Semiconductor substrate 200 comprises first area I and second area II;
Be positioned at the insulating barrier 207 on described Semiconductor substrate 200 surfaces;
The first opening (not indicating) that runs through described insulating barrier 207 thickness of first area I, runs through secondSecond opening (not indicating) of insulating barrier 207 thickness of region II;
Semiconductor substrate 200 surfaces of described the first open bottom are formed with the first high K medium layer 203a,Described the first high K medium layer 203a surface and the first opening sidewalls are formed with the first functional layer 213a, described inThe first functional layer 213a surface coverage has the first aluminium lamination 217a, and described the first aluminium lamination 217a surface is formed withThe first metal silicide layer 221a, described the first metal silicide layer 221a surface and described insulating barrier 207Flush;
Semiconductor substrate 200 surfaces of described the second open bottom are formed with the second high K medium layer 203b,Described the second high K medium layer 203b surface and the second opening sidewalls are formed with the second functional layer 213b, described inThe second functional layer 213b surface coverage has the second aluminium lamination 217b, and described the second aluminium lamination 217b surface is formed withThe second metal silicide layer 221b, described the second metal silicide layer 221b surface and described insulating barrier 207Flush.
Wherein, described Semiconductor substrate 200 is for the workbench as subsequent technique. Described semiconductorSubstrate 200 is body silicon or silicon-on-insulator (SOI), the material of described Semiconductor substrate 200 be monocrystalline silicon,SiGe, silicon-carbon or III-V compounds of group (such as gallium arsenic, indium phosphide and gallium nitride etc.). Of the present inventionIn embodiment, described Semiconductor substrate 200 comprises first area I and second area II, described first areaI is used to form NMOS pipe, and described second area II is used to form PMOS pipe, described first area IIsolate by fleet plough groove isolation structure 202 with second area II.
Described insulating barrier 207 is for isolating the first aluminium lamination 217a and of first area I and second area IITwo aluminium lamination 217b. The material of described insulating barrier 207 is silica, silicon nitride or silicon oxynitride. At thisIn bright embodiment, the material of described insulating barrier 207 is silica.
The material of described the first high K medium layer 203a is HfO2, HfSiO, HfSiNO or ZrO2Deng,Be used for isolating the first aluminium lamination 217a and Semiconductor substrate 200. The material of described the second high K medium layer 203bFor HfO2, HfSiO, HfSiNO or ZrO2Deng, for isolating the second aluminium lamination 217b and Semiconductor substrate200. In an embodiment of the present invention, described the first high K medium layer 203a and the second high K medium layer 203bMaterial identical, be ZrO2。
The material of described the first functional layer 213a be a kind of in titanium nitride, tantalum nitride, titanium aluminide or tantalum orMultiple combination, for regulating the work function of semiconductor devices of first area I. Described the second functional layer 213bMaterial be one or more combinations in titanium nitride, tantalum nitride, titanium aluminide or tantalum, but described the second meritThe material of ergosphere 213b is different from the material of described the first functional layer 213a, for regulating second area IIThe work function of semiconductor devices. In an embodiment of the present invention, the material of described the first functional layer 213aFor titanium nitride, for regulating the work function of NMOS pipe, the material of described the second functional layer 213b is calorizeThe combination of titanium and tantalum, for regulating the work function of PMOS pipe.
Described the first aluminium lamination 217a is used to form the metal gates of the semiconductor devices of first area I, described inThe second aluminium lamination 217b is used to form the metal gates of the semiconductor devices of second area II. For protecting the first aluminiumLayer 217a and the second aluminium lamination 217b are not oxidized, and not damaged in subsequent technique, and described firstThe thickness of aluminium lamination 217a and the second aluminium lamination 217b is the degree of depth of the first opening and the second opening respectively, described inThe first aluminium lamination 217a and the second aluminium lamination 217b surface, lower than described insulating barrier 207 surfaces, are beneficial to follow-up shapeBecome the first metal silicide layer 221a and the second metal silicide layer 221b. Described the first aluminium lamination 217a andThe second aluminium lamination 217b is mono-crystalline structures, and durability and mechanical strength are high. More about the first aluminium lamination 217aPlease refer to the description about aluminium lamination in the first embodiment with the associated description of the second aluminium lamination 217b.
Described the first metal silicide layer 221a is not oxidized for the protection of the aluminium on the first aluminium lamination 217a surface,And in subsequent technique, protect the first aluminium lamination 217a not damaged. Described the second metal silicide layer 221bAluminium for the protection of the second aluminium lamination 217b surface is not oxidized, and in subsequent technique, protects the second aluminium lamination217b is not damaged. In an embodiment of the present invention, for better protecting the first aluminium lamination 217a and the second aluminiumLayer 217b, the thickness of described the first metal silicide layer 221a and the second metal silicide layer 221b is 10Dust-300 dust.
The semiconductor devices that the embodiment of the present invention forms, owing to thering is the first functional layer and the second functional layer,Not only can effectively regulate the work function of the semiconductor devices of regional, and each region semiconductor devicesThe quality of metal gates of aluminum good, inside does not almost have defect, and is mono-crystalline structures, durabilityGood, mechanical strength is high. And owing to having the protection of metal silicide layer, the metal gates of described aluminumThe aluminium on surface is difficult for oxidized, and subsequent technique metal gates is not fragile yet, and the performance of semiconductor devices moreStable.
To sum up, first form the aluminium film that covers described polysilicon layer surface and the gold that covers described aluminium filmBelong to layer, follow-up while carrying out annealing in process, the aluminium in described aluminium film enters open bottom, forms and is positioned at instituteState the aluminium lamination of semiconductor substrate surface, the quality of described aluminium lamination is good, and inside does not have hole, and is monocrystalline knotStructure, mechanical endurance is good. Polysilicon in polysilicon electrode layer upwards shifts simultaneously, occurs with metal levelReaction form metal silicide layer, saved processing step, and form metal silicide layer follow-up canAluminium with protection aluminium lamination surface is not oxidized, and in subsequent technique, has avoided aluminium lamination to be damaged, formationThe stable performance of semiconductor devices.
Because the aluminium lamination surface coverage of semiconductor devices has metal silicide layer, described aluminium lamination is difficult for oxidized,And avoided aluminium lamination to damage in subsequent technique, the quality of described aluminium lamination is good, and described aluminium lamination is monocrystallineStructure, its durability and mechanical strength are high, the stable performance of semiconductor devices.
Although the present invention with preferred embodiment openly as above, it is not for limiting the present invention, appointsWhat those skilled in the art without departing from the spirit and scope of the present invention, can utilize above-mentioned announcementMethod and technology contents are made possible variation and amendment to technical solution of the present invention, therefore, every not de-From the content of technical solution of the present invention, that according to technical spirit of the present invention, above embodiment is done is anySimple modification, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.

Claims (11)

1. a formation method for semiconductor devices, is characterized in that, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface is formed with insulating barrier, tool in described insulating barrierThere is the opening that runs through its thickness, in described opening, be formed with the polysilicon electricity flushing with described surface of insulating layerUtmost point layer;
Form the aluminium film that covers described Semiconductor substrate and polysilicon electrode layer surface, described aluminium filmThickness is lower than the thickness of polysilicon electrode layer;
Form the metal level that covers described aluminium film;
After forming described metal level, carry out annealing in process, make aluminium in described aluminium film enter open bottom and replaceFor polysilicon electrode layer, form and be positioned at the aluminium lamination of described semiconductor substrate surface, described aluminium lamination surface lower thanDescribed open surfaces, and polysilicon in polysilicon electrode layer is transferred to open top, and send out with metal levelRaw reaction forms the metal silicide layer that is positioned at described aluminium lamination surface, and part metals silicide layer is positioned at openingIn;
Chemically mechanical polishing is positioned at metal level, aluminium film, the metal silicide of described semiconductor substrate surfaceLayer, until expose described surface of insulating layer, aluminium lamination surface also has metal silicide layer.
2. the formation method of semiconductor devices as claimed in claim 1, is characterized in that, described annealing in processProcess parameters range be: annealing temperature is 400 degrees Celsius-600 degrees Celsius, and annealing time is 30Minutes-450 minutes.
3. the formation method of semiconductor devices as claimed in claim 2, is characterized in that, described annealing in processTime annealing temperature be 480 degrees Celsius-520 degrees Celsius.
4. the formation method of semiconductor devices as claimed in claim 1, is characterized in that, described metal levelMaterial is titanium, cobalt or nickel.
5. the formation method of semiconductor devices as claimed in claim 1, is characterized in that, described aluminium filmThickness is 100 dust-500 dusts.
6. the formation method of semiconductor devices as claimed in claim 1, is characterized in that, described aluminium filmFormation technique is physical gas-phase deposition, and its process parameters range is: the pressure of deposition chambers is 1Millitorr-10 millitorr, depositing temperature is 400 degrees Celsius-600 degrees Celsius.
7. the formation method of semiconductor devices as claimed in claim 1, is characterized in that, described metal silicationThe material of thing layer is titanizing silicon, cobalt SiClx or nickel SiClx.
8. the formation method of semiconductor devices as claimed in claim 1, is characterized in that chemically mechanical polishingAfter, the thickness of the metal silicide layer in described opening is 10 dust-300 dusts.
9. the formation method of semiconductor devices as claimed in claim 1, is characterized in that, described opening darkWide ratio is greater than 8, and the formation technique of described polysilicon electrode layer is chemical vapor deposition method.
10. the formation method of semiconductor devices as claimed in claim 1, is characterized in that, in described opening, goes backBe formed with high-K gate dielectric layer, described polysilicon electrode layer covers described high-K gate dielectric layer surface.
The formation method of 11. semiconductor devices as claimed in claim 10, is characterized in that, in described opening, goes backBe formed with functional layer, described functional layer is formed at described high K dielectric layer and polysilicon electrode interlayer.
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