CN103533350B

CN103533350B - A kind of HEVC interframe interpolation device

Info

Publication number: CN103533350B
Application number: CN201310446341.7A
Authority: CN
Inventors: 郑海伟; 高剑; 刘钦
Original assignee: Huawei Technologies Co Ltd
Current assignee: Shenzhen Huawei Cloud Computing Technology Co ltd
Priority date: 2013-09-26
Filing date: 2013-09-26
Publication date: 2016-12-07
Anticipated expiration: 2033-09-26
Also published as: CN103533350A

Abstract

The embodiment of the invention discloses a kind of HEVC interframe interpolation device, wherein HEVC interframe brightness multiple spot interpolating apparatus includes: 14 shift registers and 22 adders；Wherein, described 14 shift registers comprise: four shift registers of 1 that input data are moved right, four shift registers of 2 that input data are moved right, four shift registers of 3 that input data are moved right, two shift registers of 4 that input data are moved right；Wherein, comprising in described 22 adders, 16 adders input data being added, six have the adder by being added function after input data-conversion.

Description

A kind of HEVC interframe interpolation device

Technical field

The present invention relates to electroporation field, particularly to a kind of HEVC (High Efficiency Video Coding, efficient video coding) interframe interpolation device.

Background technology

Video signal comprises huge quantity of information, with CIF (common intermediate format, general Intermediate form: 352 × 288) video signal as a example by, if without any compression, with 30 frames per second Speed be transmitted if, the code check of transmission reaches 70Mbps, same, if above-mentioned video signal Not compressing, the normal optical disk of a 700M can only store the video of 80 seconds.Therefore, efficient video pressure Contracting coding techniques is extremely urgent.

Although video signal contains huge quantity of information, but these information are often height correlation, There is substantial amounts of redundancy, such as: in image sequence, two adjacent images usually contain the identical back of the body Scape and mobile object, simply the locus of object is slightly different, so the data of a later frame and former frame Data have many identical places (time redundancy)；In any piece image, all have by many gray scales Or color the most same or like neighborhood pixels composition region, therefore these pixel Existential Space continuities, But represent that the mode of object color does not utilize this spatial coherence (empty based on discrete pixels sampling Between redundancy)；Additionally, there may be coding redundancy, visual redundancy etc..

The principle of video compression coding and starting point are that and eliminate various redundancy to greatest extent.For not Same redundancy, video compression coding standard uses different strategies to eliminate.The scheme of general employing is: Time redundancy is eliminated with inter prediction；Spatial redundancy is eliminated with infra-frame prediction；Regard with conversion, quantization elimination Feel redundancy；Coding redundancy is eliminated with entropy code.

Two are mainly had to be organized in research and the formulation carrying out video compression coding standard at present, point Wei ITU-T (International Telecommunication Union, International Telecommunication Union) and MPEG (Moving Pictures Experts Group, dynamic image expert group).The video compress of main flow is compiled at present H.264 (MPEG-4Part10, the advanced video coding of dynamic image expert group-4) code standard is.HEVC (High Efficiency Video Coding, efficient video coding) is as video compression coding mark of future generation Standard, the code check after video compress only has 50% the most H.264, it is achieved that current most advanced coded system cannot The business model realized, such as: by the 3DTV of full resolution (Three Dimensions television, three Dimension TV) in even 4K video compress high definition coding pass up till now, there is huge market prospect, Cost is then the raising of algorithm complex and realizes the increase of cost.

In order to improve the accuracy of inter prediction, by the pattern of inter prediction H.264 in the draft of HEVC FME (Fractional Motion Estimate, fraction movement estimate) frame foundation on add one Merge (merging) predict, it was predicted that block by 4 × 4 H.264,8 × 8 and 16 × 16 3 layers increase to 4 × 4,8 × 8,16 × 16,32 × 32 and 64 × 64 5 layers.

Inter prediction is as one of the major part of HEVC, it was predicted that accuracy directly influence video pressure Reducing the staff the effect of code, FME and Merge is then the major part of inter prediction.In order to improve prediction picture The precision of element, FME carries out the search of 1/4 precision to brightness, and colourity carries out the search of 1/8 precision, and i.e. two Between individual integer luminance pixel, interpolation obtains 3 fraction pixel points (mainly by each 4 the integer pictures in left and right Vegetarian refreshments, is obtained by 3 groups of wave filter respectively), between two integer chroma pixels, interpolation obtains 7 marks Pixel (main by each 2 the integer pixel points in left and right, to be obtained by 7 groups of wave filter respectively), is needed Consume tens Horizontal interpolation unit and vertical interpolation unit.Merge mainly by contiguous block (spatial domain and time Territory) MV/CandIdx (Motion Vector/Candidate Index: motion vector/candidate index) letter Breath substitutes the MV/CandIdx information of current block, more respectively according to brightness MV and colourity MV from 3 1 optimum some output of each selection, interpolation mistake in brightness fraction pixel point and 7 colourity fraction pixel points Journey is also required to consume substantial amounts of Horizontal interpolation unit and vertical interpolation unit.

Understand based on described above: either FME or Merge, use logic hardware to realize being required for Using substantial amounts of interpolating unit, the logical resource of its amount of calculation and consumption accounts for whole HEVC project proportion 25%, logic realization relatively costly.

Use above scheme, in order to complete 3 brightness fraction pixel points and 7 colourity fraction pixel points Interpolation, needs 3 independent brightness interpolating wave filter and 7 chroma interpolation wave filter, each filtering interpolation Each interpolating unit of device is separate.In order to improve the real-time of HEVC video compression coding, need FPGA (Field Programmable Gate Array, field programmable gate array) or ASIC (Application-Specific Integrated Circuit, special IC) upper logic realization HEVC Video compression coding；And FME and Merge needs to consume substantial amounts of interpolating unit, due to each group of wave filter Between separate, consume logical resource more, be unfavorable for that hardware realizes.

Summary of the invention

Embodiments provide a kind of HEVC interframe interpolation device, for reducing disappearing of logical resource Consumption.

Embodiments provide a kind of HEVC interframe brightness multiple spot interpolating apparatus, including: 14 Shift register and 22 adders；

Wherein, described 14 shift registers comprise: input data are moved right 1 by four Shift register is followed successively by: the one one zero one shift register A101, the one one zero two shift register A102, the one one zero three shift register A103, the one one zero four shift register A104, four will The move right shift register of 2 of input data is followed successively by: the 2nd 101 shift register B101, 2nd 102 shift register B102, the 2nd 103 shift register B103, the 2nd 104 displacement Depositor B104, four shift registers of 3 of input data being moved right are followed successively by: the 3rd 10 One shift register C101, the 3rd 102 shift register C102, the 3rd 103 shift register C103, the 3rd 104 shift register C104, two displacements of 4 of input data being moved right are posted Storage is followed successively by: the 4th 101 shift register D101, the 4th 102 shift register D102；

Wherein, described 22 adders comprise, 16 adders that input data are added, It is followed successively by: the one one zero three adder E103, the one one zero four adder E104, the one one zero five addition Device E105, the one one zero six adder E106, the one one zero seven adder E107, the one one zero eight add Musical instruments used in a Buddhist or Taoist mass E108, the one one zero nine adder E109, the first zero adder E110, the one one one by one one by one Adder E111, the first two adders E112, the first three adders E113, first one by one one by one one by one Five adders E115, first one by one six adders E116, first one by one seven adders E117, the 1st One or nine adders E119, the one one two two adder E122, six have phase after input data-conversion Add the adder of function, be followed successively by: the 2nd 101 adder E101, the 2nd 102 adder E102, Second one by one four adders E114, second one by one eight adders E118, the 2nd 120 adder E120, 2nd 121 adder E121；

Eight brightness integral points are followed successively by X₀、X₁、X₂、X₃、X₄、X₅、X₆、X₇；

X₀The 2nd 101 adder E101, X is inputted as data₁As data input the 2nd 101 shifting Bit register B101 and first zero adder E110 one by one, X₂As data input the 1st displacement Depositor A101, the one one zero three adder E103 and the one one zero four adder E104, X₃As number According to input the one one zero three shift register A103, the one one zero five adder E105, the one one zero seven add Musical instruments used in a Buddhist or Taoist mass E107 and the one one zero eight adder E108, X₃Also export as integral point, X₄Defeated as data Enter the one one zero six adder E106, the one one zero seven adder E107, the one one zero four shift register A104 and the one one zero nine adder E109, X₅As data input the one one two two adder E122, One one zero three adder E103 and the one one zero two shift register A102, X₆Input as data 2nd 102 shift register (B102) and the 1st adder E111, X one by one₇As input data Input the 2nd 102 adder E102；

The outfan of the 2nd 101 shift register B101 connects the defeated of the 2nd 101 adder E101 Enter end, outfan connection the 1st adder E111 and first one by one of the 2nd 101 adder E101 Two adder E112 one by one；The outfan of the 2nd 102 shift register (B102) connects the 2nd 10 Two adders E102, outfan connection first zero adder E110 one by one of the 2nd 102 adder E102 With the first two adder E112 one by one, the outfan of the first zero adder E110 one by one connects the 2nd 121 Adder E121, first one by one two adders E112 outfan connect the 2nd 120 adder E120；

The outfan of the one one zero one shift register A101 connects the one one two two adder E122, the The outfan of two or two adders E122 connects the 2nd 103 shift register B103, first one by one one by one Three adders E113 and first, five adder E115 one by one, the 2nd 103 shift register B103's is defeated Going out end and connect the first three adder E113 one by one, the outfan of the first three adders E113 one by one connects second Four adder E114 one by one；The outfan of the one one zero two shift register A102 connects the 1st Adder E104, the outfan of the one one zero four adder E104 connects the 2nd 104 shift register B104, the first five adders E115 and first, six adder E116 one by one one by one；2nd 104 displacement Outfan connection first six adders E116, the one one zero three adder E103 one by one of depositor B104 Outfan connect the 3rd 101 shift register C101, the 3rd 101 shift register C101's Outfan connection first five adder E115 one by one；The outfan of the first five adders E115 one by one connects the 2120 adders E120, first one by one the outfan of six adders E116 connect and the 2nd 121 add Musical instruments used in a Buddhist or Taoist mass E121；

The outfan of the one one zero three shift register A103 connects the one one zero six adder E106 and the 05 adder E105 one by one, the outfan of the one one zero five adder E105 connects the 3rd 102 shifting Outfan connection first seven addition one by one of bit register C102, the 3rd 102 shift register C102 Device E117；The outfan of the one one zero six adder E106 connects the 4th 101 shift register D101 With the first seven adders E117, outfan connection first of the 4th 101 shift register D101 one by one Seven adders E117 and second, eight adder E118 one by one one by one；One one zero seven adder E107 defeated Go out end and connect the 3rd 103 shift register C103, the output of the 3rd 103 shift register C103 End connection second eight adder E118 one by one；The outfan of the one one zero four shift register A104 connects One one zero eight adder E108 and the one one zero nine adder E109, the one one zero nine adder E109 Outfan connect the 3rd 104 shift register C104, the 3rd 104 shift register C104's Outfan connection first nine adder E119 one by one；The outfan of the one one zero eight adder E108 connects 4th 102 shift register D102 and first, nine adders E119 one by one, the 4th 102 displacement is posted Outfan connection second eight adders E118 and first, nine adder E119 one by one one by one of storage D102； The outfan of the one one adder E111 one by one connects the second four adders E114 one by one, and first seven adds one by one The outfan of musical instruments used in a Buddhist or Taoist mass E117 connects the second four adder E114 one by one, the second eight adders E118 one by one Outfan connect the 2nd 120 adder E120, first one by one nine adders E119 outfan connect 2nd 121 adder E121；

Wherein, the 2nd 101 adder E101 X to input₀Negate, the 2nd 102 adder E102 X to input₇Negate, second one by one four adders E114 to from first one by one three adders E113 input Data-conversion, second one by one eight adders E118 to from the 3rd 103 shift register C103 input Data-conversion, the 2nd 120 adder E120 to from first one by one five adders E115 input number According to negating, the data from the first six adders E116 inputs one by one take by the 2nd 121 adder E121 Instead；

Second one by one four adders E114 output first fractional point FLT1, the 2nd 120 adder E120 Exporting second fractional point FLT2, the 2nd 121 adder E121 exports the 3rd fractional point FLT3.

A kind of HEVC interframe colourity multiple spot interpolating apparatus, including: 14 shift registers, 24 Individual adder and five SYN registers；

Wherein, described 14 shift registers comprise: five shiftings of 1 of input data being moved right Bit register is followed successively by: the one one zero five shift register A105, the one one zero six shift register A106, One one zero seven shift register A107, the one one zero eight shift register A108, the one one zero nine shifting Bit register A109；Three shift registers of 2 of input data being moved right are followed successively by: the 2nd 1 05 shift register B105, the 2nd 106 shift register B106, the 2nd 107 shift register B107, two shift registers of 3 of input data being moved right are followed successively by: the 3rd 105 displacement Depositor C105, the 3rd 106 shift register C106, input data are moved right 4 by two Shift register is followed successively by: the 4th 103 shift register D103, the 4th 104 shift register D104；Two shift registers of 5 of input data being moved right are followed successively by: May Day 01 shifts Depositor F101, shift register F102 on May Day 02；

Wherein, described 24 adders comprise, 17 adders that input data are added, It is followed successively by: the one one two three adder E123, the one one two four adder E124, the one one two five addition Device E125, the one one two six adder E126, the one one two seven adder E127, the one one sixteen add Musical instruments used in a Buddhist or Taoist mass E128, the one one two nine adder E129, the one one three zero adder E130, the 1st Adder E131, the one one three two adder E132, the one one three three adder E133, the 1st Four adders E134, the one one three five adder E135, the one one three six adder E136, the 1st Radix Notoginseng adder E137, the one one three eight adder E138, the one one four six adder E146, seven There is the adder by being added function after input data-conversion, be followed successively by: the 2nd 1 three nine-day periods after the winter solstice adder E139, the 2nd 140 adder E140, the 2nd 141 adder E141, the 2nd 142 adder E142, the 2nd 143 adder E143, the 2nd 144 adder E144, the 2nd 145 adder E145；

Five SYN registers with clock synchronizing function, are followed successively by: the one zero one SYN register H101, the one zero two SYN register H102, the one zero three SYN register H103, the 1st with Step depositor H104, the one zero five SYN register H105；

Four colourity integral points are followed successively by X₀、X₁、X₂、X₃；

X₀As data input the one one zero six shift register A106 and the one one four six adder E146, X₁The one one zero five shift register A105, the 2nd 105 shift register is inputted as data B105, the 3rd 105 shift register C105, the 4th 103 shift register D103 and May Day 01 shift register F101, X₁Also export as integral point, X₂As data input the 1st shifting Bit register A109, the 2nd 107 shift register B107, the 3rd 106 shift register C106, 4th 104 shift register D104 and shift register F102 on May Day 02, X₃Defeated as data Enter the one one four six adder E146 and the one one zero eight shift register A108；

The outfan of the one one zero five shift register A105 connect the one one two three adder E123, the Two or four adders E124, the one one two five adder E125 and the one one sixteen adder E128 one by one, The outfan of the 2nd 105 shift register B105 connect the one one two four adder E124, the 1st Two or five adders E125, the one one two six adder E126 and the one one two seven adder E127, the 3rd The outfan of one zero five shift register C105 connect the one one two three adder E123, the 1st Adder E125, the one one two seven adder E127 and the one one sixteen adder E128, the 4th 10 The outfan of three shift register D103 connects the one one two three adder E123, the one one two four addition Device E124, the one one two seven adder E127 and the one zero one SYN register H101, May Day 01 The outfan of shift register F101 connects the one one two three adder E123, the one one two four adder E124, the one one two five adder E125 and the one one two six adder E126；One one two three addition The outfan of device E123 connect the 2nd 1 three nine-day periods after the winter solstice adder E139, the one one two four adder E124 defeated Go out that end connects the 2nd 140 adder E140, the outfan of the one one two five adder E125 connects the 2141 adders E141, the outfan of the one one two six adder E126 connect the 2nd 142 and add Musical instruments used in a Buddhist or Taoist mass E142, the one one two seven adder E127 outfan connect the 2nd 143 adder E143, The outfan of the one zero one SYN register H101 connect the 2nd 144 adder E144, the 1st The outfan of eight adders E128 connects the 2nd 145 adder E145；

The outfan of the one one zero six shift register A106 connects the one one two nine adder E129 and the 30 adder E130 one by one, the outfan of the one one four six adder E146 connects the one one zero seven shifting Bit register A107 and the 2nd 106 shift register B106, the one one zero eight shift register A108 Outfan connect the one one three one adder E131 and the one one three two adder E132, the 1st The outfan of seven shift register A107 connects the one zero two SYN register H102, the one one two nine adds Musical instruments used in a Buddhist or Taoist mass E129, the one one three two adder E132 and the one zero four SYN register H104, the one one zero The outfan of six shift register A106 connects the one one three zero adder E130, the one zero three synchronization is posted Storage H103 and the one one three one adder E131, the outfan of the one zero two SYN register H102 is even Connecing the 2nd 1 three nine-day periods after the winter solstice adder E139, the outfan of the one one two nine adder E129 connects the 2nd 14 Zero adder E140, the outfan of the one one three zero adder E130 connects the 2nd 141 adder The outfan of E141, the one zero three SYN register H103 connects the 2nd 142 adder E142, the The outfan of 31 adders E131 connects the 2nd 143 adder E143 one by one, and the one one three two adds The outfan of musical instruments used in a Buddhist or Taoist mass E132 connects the 2nd 144 adder E144, the one zero four SYN register H104 Outfan connect the 2nd 145 adder E145；

The outfan of the one one zero nine shift register A109 connect the one one three three adder E133, the Three or six adders E136, the one one Radix Notoginseng adder E137 and the one one three eight adder E138 one by one, The outfan of the 2nd 107 shift register B107 connect the one one three four adder E134, the 1st Three or five adders E135, the one one three six adder E136 and the one one Radix Notoginseng adder E137, the 3rd The outfan of one zero six shift register C106 connect the one one three three adder E133, the 1st Adder E134, the one one three six adder E136 and the one one three eight adder E138, the 4th 10 The outfan of four shift register D104 connects the one zero five SYN register H105, the one one three four adds Musical instruments used in a Buddhist or Taoist mass E134, the one one Radix Notoginseng adder E137 and the one one three eight adder E138, May Day 02 The outfan of shift register F102 connects the one one three five adder E135, the one one three six adder E136, the one one Radix Notoginseng adder E137 and the one one three eight adder E138；

Outfan connection the 2nd 1 three nine-day periods after the winter solstice adder E139 of the one one three three adder E133, the one zero The outfan of five SYN register H105 connects the 2nd 140 adder E140, the one one three four addition The outfan of device E134 connects the 2nd 141 adder E141, the one one three five adder E135 defeated Going out end and connect the 2nd 142 adder E142, the outfan of the one one three six adder E136 connects the 2143 adders E143, the outfan of the one one Radix Notoginseng adder E137 connects the 2nd 144 and adds Musical instruments used in a Buddhist or Taoist mass E144, the outfan of the one one three eight adder E138 connects the 2nd 145 adder E145；

2nd 1 three nine-day periods after the winter solstice adder E139 to from the 1st SYN register H102 input data-conversion, 2nd 140 adder E140 to from the 1st adder E129 input data-conversion, second One four one adders E141 to from the 1st adder E130 input data-conversion, the 2nd 14 Two adders E142 to from the 1st SYN register H103 input data-conversion, the 2nd 143 Adder E143 is to from the data-conversion of the one one three one adder E131 input, the 2nd 144 addition Device E144 is to from the data-conversion of the one one three two adder E132 input, the 2nd 145 adder E145 is to the data-conversion from the one zero four SYN register H104 input；

Outfan first fractional point FLT1 of output of the 2nd 1 three nine-day periods after the winter solstice adder E139, the 2nd 140 Outfan second fractional point FLT2 of output of adder E140, the 2nd 141 adder E141 defeated Going out end the 3rd fractional point FLT3 of output, the outfan of the 2nd 142 adder E142 exports the 4th Fractional point FLT4, the outfan of the 2nd 143 adder E143 exports the 5th fractional point FLT5, the The outfan of 2144 adders E144 exports the 6th fractional point FLT6, the 2nd 145 adder The outfan of E145 exports the 7th fractional point FLT7.

A kind of HEVC interframe brightness single-point interpolating apparatus, including: 16 shift registers, 16 Adder and 18 selection circuits；

Wherein, described 16 shift registers comprise: four shiftings of 1 of input data being moved right Bit register is followed successively by: first one by one zero shift register A110, the 1st one by one shift register A111, One one First Five-Year Plan shift register A115, the first six shift register A116 one by one, four will input data The shift register of 2 of moving right is followed successively by: the 2nd 108 shift register B108, the 2nd 10 Nine shift register B109, the second zero shift register B110, the second four shift register one by one one by one B114, four shift registers of 3 of input data being moved right are followed successively by: the 3rd 107 displacement Depositor C107, the 3rd 108 shift register C108, the 3rd one by one zero shift register C110, 3rd 1 shift register C111 one by one, two shift registers of 4 that input data are moved right: 4th 105 shift register D105, the 4th 107 shift register D107, two will input number According to moving right the shift register of 5: May Day 03 shift register F103, May Day 05 moves Bit register F105；

Described 16 adders comprise: 14 adders input data being added, and are followed successively by: the One by one four or seven adders E147, the one one four eight adder E148, the one one four nine adder E149, 1st May Day adder E151, the first First Five-Year Plan two adder E152, the one one the May 4th adder E154, First First Five-Year Plan five adder E155, the first First Five-Year Plan six adder E156, the one one six four adder E164, First parathion adder E165, the one one six six adder E166, the one one six seven adder E167, One one six eight adder E168, the one one six nine adder E169, two have and will input data-conversion It is added the adder of function later, is followed successively by: the second First Five-Year Plan zero adder E150, the second First Five-Year Plan three addition Device E153；

18 selection circuits are followed successively by: the one zero one selection circuit G101, the one zero two selection circuit G102, the one zero three selection circuit G103, the one zero four selection circuit G104, the one zero five selection electricity Road G105, the one zero six selection circuit G106, the one zero seven selection circuit G107, the one zero eight selection Circuit G108, the one zero nine selection circuit G109, the one one zero option circuit G110, first select one by one Select circuit G111, the one two one selection circuit G121, the one two two selection circuit G122, the 1st Selection circuit G123, the one two four selection circuit G124, the one two five selection circuit G125, the one or two Six selection circuit G126, the one two seven selection circuit G127；

X₀The one zero one selection circuit G101, X is inputted as data₁As data input the 1st selection Circuit G103 and the 2nd 108 shift register B108, X₂As data input the 3rd 108 displacement Depositor C108, second one by one zero shift register B110, the 1st one by one shift register A111 and One one zero option circuit G110, X₅As data input the 3rd 1 shift register C111 one by one, the 211 four shift register B114, first one by one six shift register A116 and the 1st select electricity Road G127, X₃Input shift register F103 on May Day 03 as data, the 3rd 107 displacement is posted Storage C107, the 4th 105 shift register D105, first one by one zero shift register A110 and One zero six selection circuit G106, X₄As data input shift register F105 on May Day 03, Three one by one zero shift register C110, the 4th 107 shift register D107, the 1st the First Five-Year Plan displacement post Storage A115 and the one two two selection circuit G122, X₆The one zero four selection circuit is inputted as data G104 and the 2nd 109 shift register B109, X₇As input data input the 1st selection electricity Road G102；Constant 0 input the most respectively the one zero one selection circuit G101, the one zero two selection circuit G102, One zero five selection circuit G105, the one zero six selection circuit G106, the one zero seven selection circuit G107, One zero eight selection circuit G108, the one zero nine selection circuit G109, the one one zero option circuit G110 With the first selection circuit G111, the one two one selection circuit G121, the one two two selection circuit one by one G122, the one two four selection circuit G124, the one two five selection circuit G125, the one two six selection electricity Road G126, the one two seven selection circuit G127 and the one two three selection circuit G123；

The outfan of the 2nd 108 shift register B108 connects the one zero three selection circuit G103, the Outfan connection the one zero four selection circuit G104 of 2109 shift register B109, the one zero one The outfan of selection circuit G101 connects the one one four seven adder E147, the one zero two selection circuit The outfan of G102 connects the one one four seven adder E147, the output of the one one four seven adder E147 End connects the second First Five-Year Plan zero adder E150, and the outfan of the one zero three selection circuit G103 connects first One four eight adders E148, the outfan of the one zero four selection circuit G104 connects the one one four eight addition Device E148, the outfan of the one one four eight adder E148 connects the second First Five-Year Plan zero adder E150, the The outfan of two First Five-Year Plan zero adders E150 connects the second First Five-Year Plan three adder E153；

May Day 03, the outfan of shift register F103 connected the one one four nine adder E149, the Outfan connection the one one four nine adder E149 of 3107 shift register C107, the 4th 10 The outfan of five shift register D105 connects the one zero five selection circuit G105, the first zero displacement one by one The outfan of depositor A110 connects the one zero six selection circuit G106, the one one four nine adder E149 Outfan connect first one by one selection circuit G111, the one zero five selection circuit G105 outfan even Connect the 1st May Day adder E151, the outfan of the one zero six selection circuit G106 connected for the first First Five-Year Plan One adder E151, the outfan of the first selection circuit G111 one by one connects the first First Five-Year Plan two adder E152, the 1st May Day adder E151 outfan connect the first First Five-Year Plan two adder E152, first The outfan of First Five-Year Plan two adder E152 connects the second First Five-Year Plan three adder E153；

May Day 05, the outfan of shift register F105 connected the one one six four adder E164, the Three one by one zero shift register C110 outfan connect the one one six four adder E164, the 4th 10 The outfan of seven shift register D107 connects the one two one selection circuit G121, the displacement of the one one First Five-Year Plan The outfan of depositor A115 connects the one two two selection circuit G122, the one one six four adder E164 Outfan connect the outfan of the one two three selection circuit G123, the one two one selection circuit G121 even Connecing the first parathion adder E165, the outfan of the one two two selection circuit G122 connects the 1st Five adders E165, the outfan of the one two three selection circuit G123 connects the one one six six adder E166, the 1st May Day adder E151 outfan connect the one one six six adder E166, first The outfan of one six six adders E166 connects the second First Five-Year Plan three adder E153；

The outfan of the 3rd 108 shift register C108 connects the one zero seven selection circuit G107, the The outfan of 211 zero shift register B110 connects the one zero eight selection circuit G108, and first one by one The outfan of one shift register A111 connects the one zero nine selection circuit G109, and the one zero seven selects electricity The outfan of road G107 connects the one one the May 4th adder E154, and the one zero eight selection circuit G108's is defeated Going out end and connect the one one the May 4th adder E154, the outfan of the one zero nine selection circuit G109 connects the One First Five-Year Plan slender acanthopanax musical instruments used in a Buddhist or Taoist mass E155, the outfan of the one one zero option circuit G110 connects the first First Five-Year Plan slender acanthopanax Musical instruments used in a Buddhist or Taoist mass E155, the outfan of the one one the May 4th adder E154 connects the first First Five-Year Plan six adder E156, The outfan of the first First Five-Year Plan five adder E155 connects the first First Five-Year Plan six adder E156, the first First Five-Year Plan six The outfan of adder E156 connects the second First Five-Year Plan three adder E153；

The outfan of the 3rd 1 shift register C111 one by one connects the one two four selection circuit G124, and the The outfan of 211 four shift register B114 connects the one two five selection circuit G125, and first one by one The outfan of six shift register A116 connects the one two six selection circuit G126, and the one two four selects electricity The outfan of road G124 connects the one one six seven adder E167, and the one two five selection circuit G125's is defeated Going out end and connect the one one six seven adder E167, the outfan of the one two six selection circuit G126 connects the Six or eight adder E168 one by one, the outfan of the one one zero option circuit G110 connects the 1st and adds Musical instruments used in a Buddhist or Taoist mass E168, the outfan of the one one six seven adder E167 connects the one one six nine adder E169, Outfan connection the one one six nine adder E169 of the one one six eight adder E168, the one one six nine The outfan of adder E169 connects the second First Five-Year Plan three adder E153；

Second First Five-Year Plan zero adder E150 to from the 1st adder E147 input data-conversion, Second First Five-Year Plan three adder E153 is to the data-conversion from the first First Five-Year Plan six adder E156 input；

The output data of the second First Five-Year Plan three adder E153 are as brightness fraction pixel point.

A kind of HEVC interframe colourity single-point interpolating apparatus, including: 14 shift registers, ten add Musical instruments used in a Buddhist or Taoist mass and 14 selection circuits；

Wherein, described 14 shift registers comprise: four shiftings of 1 of input data being moved right Bit register is followed successively by: first one by one two shift register A112, first one by one three shift register A113, First four shift register A114, the first seven shift register A117 one by one one by one, four will input data The shift register of 2 of moving right is followed successively by: the 2nd 1 shift register B111, second one by one one by one Two shift register B112, the second three shift register B113, the 2nd 1 First Five-Year Plan shift register one by one B115, two shift registers of 3 that input data are moved right: the 3rd 109 shift register C109, the 3rd two shift register C112 one by one, two displacements of 4 of input data being moved right are posted Storage: the 4th 106 shift register D106, the 4th 108 shift register D108, two will Input data move right the shift register of 5: May Day 04 shift register F104, May Day 06 shift register F106；

Described ten adders comprise: six adders input data being added, and are followed successively by: the 1st Five or seven adders E157, the first First Five-Year Plan eight adder E158, the first First Five-Year Plan nine adder E159, first One six zero adders E160, the one one six one adder E161, the one one six two adder E162, four Individual have will be added the adder of function after input data-conversion: the 2nd 163 adder E163, the 70 adders E170, the first 171 adder E171, the one one seven two adder E172 one by one；

14 selection circuits are followed successively by: the one one two selection circuit G112, the one one three selection circuit G113, the one one four selection circuit G114, the first First Five-Year Plan selection circuit G115, the one one six selection electricity Road G116, the one one seven selection circuit G117, the one one eight selection circuit G118, the one one nine selection Circuit G119, the one or two zero option circuit G120, the one sixteen selection circuit G128, the one two nine choosing Select circuit G129, the one or three zero option circuit G130, the one three one selection circuit G131, the 1st Selection circuit G132；

Four colourity integral points are followed successively by: X₀、X₁、X₂、X₃；

X₀As data input first three shift register A113 and second, two shift register one by one one by one B112, X₁Shift register F104 on May Day 04, the 4th 106 shift register is inputted as data D106, the 3rd 109 shift register C109, the 2nd 1 shift register B111 and the 1st one by one One or two shift register A112, X₂As data input shift register F106 on May Day 06, the 4th One zero eight shift register D108, the 3rd two shift register C112, the 2nd 1 First Five-Year Plan shift LD one by one Device B115 and first seven shift register A117, X one by one₃Post as data input first four displacements one by one Storage A114 and second three shift register B113 one by one；Constant 0 inputs the one one two selection the most respectively Circuit G112, the one one three selection circuit G113, the one one four selection circuit G114, the choosing of the first First Five-Year Plan Select circuit G115, the one one six selection circuit G116, the one one four selection circuit G114, the 1st Selection circuit G118, the one one nine selection circuit G119, the one sixteen selection circuit G128, the one or two Nine selection circuit G129, the one or three zero option circuit G130, the one three one selection circuit G131, first Three or two selection circuit G132 and the one or two zero option circuit G120；

May Day 04, the outfan of shift register F104 connected the one one two selection circuit G112, the Outfan connection the one one three selection circuit G113 of 4106 shift register D106, the 3rd 10 The outfan of nine shift register C109 connects the one one four selection circuit G114, and the 2nd 1 shifts one by one The outfan of depositor B111 connects the first First Five-Year Plan selection circuit G115, the first two shift register one by one The outfan of A112 connects the one one six selection circuit G116, the output of the one one two selection circuit G112 End connects the first First Five-Year Plan seven adder E157, and the outfan of the one one three selection circuit G113 connects first First Five-Year Plan seven adder E157, the outfan of the one one four selection circuit G114 connects the one one six one addition Device E161, the outfan of the first First Five-Year Plan selection circuit G115 connects the first First Five-Year Plan eight adder E158, the The outfan of six selection circuit G116 connects the first First Five-Year Plan eight adder E158 one by one, and the first First Five-Year Plan seven added The outfan of musical instruments used in a Buddhist or Taoist mass E157 connects the one one six one adder E161, the first First Five-Year Plan eight adder E158 Outfan connects the one one six one adder E161；

May Day 06, the outfan of shift register F106 connected the one sixteen selection circuit G128, the The outfan of 4108 shift register D108 connects the one two nine selection circuit G129, and the 3rd one by one The outfan of two shift register C112 connects the one or three zero option circuit G130, the displacement of the 2nd 1 First Five-Year Plan The outfan of depositor B115 connects the one three one selection circuit G131, the first seven shift register one by one The outfan of A117 connects the one three two selection circuit G132, the output of the one sixteen selection circuit G128 End connects the one one seven zero adder E170, and the outfan of the one two nine selection circuit G129 connects first One seven zero adders E170, the outfan of the one or three zero option circuit G130 connects the one one seven two addition Device E172, the outfan of the one three one selection circuit G131 connects the first 171 adder E171, the The outfan of one three two selection circuit G132 connects the first 171 adder E171, and the first 171 adds The outfan of musical instruments used in a Buddhist or Taoist mass E171 connects the one one seven two adder E172, the first 171 adder E171 Outfan connects the one one seven two adder E172；

The outfan of the first three shift register A113 one by one connects the one one seven selection circuit G117, and the Outfan connection the one one eight selection circuit G118 of 211 two shift register B112, the one one seven The outfan of selection circuit G117 connects the first First Five-Year Plan nine adder E159, the one one eight selection circuit The outfan of G118 connects the first First Five-Year Plan nine adder E159；First four shift register A114 one by one Outfan connects the one one nine selection circuit G119, the outfan of the second three shift register B113 one by one Connecting the one or two zero option circuit G120, the outfan of the one one nine selection circuit G119 connects the 1st 60 adders E160, the outfan of the one or two zero option circuit G120 connects the one one six zero adder E160；Outfan connection the one one six two adder E162 of the first First Five-Year Plan nine adder E159, first The outfan of one six zero adders E160 connects the one one six two adder E162；

The outfan of the one one six one adder E161 and the outfan of the one one seven two adder E172 Connecting the 2nd 163 adder E163, the outfan of the one one six two adder E162 connects the 2nd 1 Six or three adders E163, the 2nd 163 adder E163 is to from the one one six two adder E162 input Data-conversion, the output data of the 2nd 163 adder E163 are as colourity fraction pixel point.

As can be seen from the above technical solutions, the embodiment of the present invention has the advantage that by adding with displacement Replace multiplication operation, and multiplexing logical resource, compare the brightness interpolating scheme in background technology, be not required to Multiplier unit to be consumed (in background technology, Horizontal interpolation needs 6, and vertical interpolation needs 18), And depositor reduces 25%, combination logic reduce 10% resource consumption.If FME carries out 5x5 Mark search, then need to call 10 sub-level interpolation and 17 vertical interpolation unit, background technology needs Consuming 10488 register resources, 9156 combination logic resource, embodiment of the present invention scheme consumes 7866 register resources, 8240 combination logic resource.Greatly reduce the consumption of logical resource.

Accompanying drawing explanation

For the technical scheme being illustrated more clearly that in the embodiment of the present invention, in embodiment being described below The required accompanying drawing used is briefly introduced, it should be apparent that, the accompanying drawing in describing below is only this Some bright embodiments, from the point of view of those of ordinary skill in the art, are not paying creative work On the premise of, it is also possible to other accompanying drawing is obtained according to these accompanying drawings.

Fig. 1 is three fractional point schematic diagrams of the embodiment of the present invention；

Fig. 2 is seven fractional point schematic diagrams of the embodiment of the present invention；

Fig. 3 is embodiment of the present invention logic circuit structure schematic diagram；

Fig. 4 is embodiment of the present invention logic circuit structure schematic diagram；

Fig. 5 is embodiment of the present invention logic circuit structure schematic diagram；

Fig. 6 is embodiment of the present invention logic circuit structure schematic diagram；

Fig. 7 is embodiment of the present invention logic circuit structure schematic diagram；

Fig. 8 is embodiment of the present invention logic circuit structure schematic diagram；

Fig. 9 is embodiment of the present invention logic circuit structure schematic diagram；

Figure 10 is embodiment of the present invention logic circuit structure schematic diagram；

Figure 11 is embodiment of the present invention logic circuit structure schematic diagram；

Figure 12 A is embodiment of the present invention logic circuit structure schematic diagram；

Figure 12 B is embodiment of the present invention logic circuit structure schematic diagram；

Figure 13 A is embodiment of the present invention logic circuit structure schematic diagram；

Figure 13 B is embodiment of the present invention logic circuit structure schematic diagram；

Figure 14 is embodiment of the present invention logic circuit structure schematic diagram；

Figure 15 A is embodiment of the present invention logic circuit structure schematic diagram；

Figure 15 B is embodiment of the present invention logic circuit structure schematic diagram；

Figure 16 A is embodiment of the present invention logic circuit structure schematic diagram；

Figure 16 B is embodiment of the present invention logic circuit structure schematic diagram；

Figure 17 is embodiment of the present invention logic circuit structure schematic diagram.

Detailed description of the invention

In order to make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to this Invention is described in further detail, it is clear that described embodiment is only that some of the present invention is implemented Example rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art exist Do not make all other embodiments obtained under creative work premise, broadly fall into present invention protection Scope.

For luminance pixel, a total of 3 kind of 8 tap filter, as shown in table 1 below:

The filter tap coefficients that table 1 luminance pixel is relevant

FLT1	-1	4	-10	58	17	-5	1	0
									FLT2	-1	4	-11	40	40	-11	4	-1
FLT3	0	1	-5	17	58	-10	4	-1

FLT1～FLT3 is respectively 1/4,2/4 and 3/4 3 fractional point, as it is shown in figure 1,1/4 is corresponding FLT1, then-3～4 are corresponding in turn to the coefficient that FLT1 is expert at；2/4 corresponding FLT2, then-3～4 depend on The coefficient that secondary corresponding FLT2 is expert at；3/4 corresponding FLT3, then-3～4 are corresponding in turn to FLT3 is expert at Coefficient.

For chroma pixel, a total of 7 kind of 4 tap filter, as shown in table 2 below:

The filter tap coefficients that table 2 chroma pixel is relevant

FLT1	-2	58	10	-2
					FLT2	-4	54	16	-2
FLT3	-6	46	28	-4
					FLT4	-4	36	36	-4
FLT5	-4	28	46	-6
					FLT6	-2	16	54	-4
FLT7	-2	10	58	-2

In FLT1～FLT7 shown in Fig. 2, when value FLT1～FLT7, more than-1～2 difference correspondences The coefficient that FLT1～FLT7 is expert at.

Following example are the embodiment of the many point interpolations of interframe, and including two parts, respectively interframe multiple spot is inserted The luminance part of value and chrominance section, specific as follows:

One, the luminance part of the many point interpolations of interframe.

First, extract interframe brightness interpolating filter factor general character, specific as follows:

Two coefficients of the 1st, the 2nd liang of group wave filter identical (in table 3, circle in FLT1 and FLT7 Marker location), latter two coefficient of the 2nd, the 3rd liang of group wave filter identical (in table 3, FLT2 and FLT3 circle marker location)；Refer to shown in table 3:

Table 3

Obtain circuit as shown in Figure 3.Fig. 3 is a part of Fig. 6, refers to illustrating of Fig. 6. x₂And x₅Corresponding coefficient 5,10,11 has common portion, as follows:

10x₂+5x₅=(2x₂+x₅)*4+(2x₂+x₅)；

10x₅+5x₂=(2x₅+x₂)*4+(2x₅+x₂)；

The common portion of above three formulas:Obtain circuit as shown in Figure 4.Fig. 4 is of Fig. 6 Point, refer to illustrating of Fig. 6.

x₃And x₄Corresponding coefficient 58,40,17 has a common portion:

58x₃+17x₄=(x₃+2x₃)*8+(2x₃+x₄)+(2x₃+x₄)*16；

40x₃+40x₄=(2x₃+x₄)*16+(2x₄+x₃)*16-(x₃+x₃)*8；

17x₃+58x₄=(x₄+2x₄)*8+(2x₄+x₃)+(2x₄+x₃)*16；

The common portion of above three formulas is:Obtain logic circuit as shown in Figure 5.Fig. 5 is Fig. 6 A part, refer to illustrating of Fig. 6.

Embodiments provide a kind of HEVC interframe interpolation device, be used for realizing the many point interpolations of interframe Luminance part, comprehensive figure 3 above～5 obtains integral point and the circuit diagram of three fractional point, such as Fig. 6 Shown in.Including: 14 shift registers and 22 adders；

A～t shown in Fig. 6 is the intermediate value of each logical device output.

Two, the chrominance section of the many point interpolations of interframe.

Secondly, interframe chroma interpolation filter factor general character is extracted:

The 1st of 7 groups of wave filter, the 4th coefficient is all the combination of 2,4,6 wherein 2 data, can obtain Circuit as shown in Figure 8, circuit shown in Fig. 8 is a part for circuit shown in Figure 10, refers to Figure 10 Illustrate.

The 2nd of 7 groups of wave filter, the 3rd coefficient has a common portion:

58x=2x+8x+16x+32x；

54x=2x+4x+16x+32x；

46x=2x+4x+8x+32x；

36x=4x+32x；

28x=4x+8x+16x；

16x=16x；

10x=2x+8x；

Common portion refers to four row of as above 7 formulas.Circuit as shown in Figure 7 and Figure 8 can be obtained, Circuit shown in Fig. 7 and Fig. 8 is a part for circuit shown in Figure 10, refers to illustrating of Figure 10.

Embodiments provide a kind of HEVC interframe interpolation device, be used for realizing the many point interpolations of interframe Chrominance section, comprehensive figure 7 above～9 obtains integral point and the circuit diagram of seven fractional point, such as Figure 10 Shown in.Including: 14 shift registers, 24 adders and five SYN registers；

Above example scheme, operates by adding replacement multiplication with displacement, and multiplexing logical resource, phase Ratio brightness interpolating scheme in background technology, it is not necessary to (in background technology, level is inserted to consume multiplier unit Value needs 6, and vertical interpolation needs 18), and depositor reduces 25%, combination logic reduces The resource consumption of 10%.If FME carries out the mark search of 5x5, then need to call 10 sub-level interpolation With 17 vertical interpolation unit, background technology needs to consume 10488 register resources, 9156 combinations Logical resource, embodiment of the present invention scheme consumes 7866 register resources, 8240 combination logic resource. Greatly reduce the consumption of logic.

Following example are the embodiment of interframe single-point interpolation, and including two parts, respectively interframe multiple spot is inserted The luminance part of value and chrominance section, specific as follows:

One, the luminance part of interframe single-point interpolation.

First, interframe brightness interpolating filter factor general character is extracted:

The coefficient that x0, x1, x6 are corresponding with x7 has moiety (in table 4 ,-1 and 4), such as table 4 below Shown in:

Table 4

Can obtain structure shown in Figure 11, Figure 11 is a part of Figure 14, refers to the detailed of Figure 14 Explanation.

Wherein mux show the selection circuit of multiselect one, in addition to the importation shown in Figure 14, Each mux also has a LPFSel as input value, and LPFSel represents and selects 1/4th of FLT1 Pixel or select FLT2 2/4ths pixels or select FLT3 3/4ths pixels Point；Select which in upper table 1 or table 4 corresponding to restriction, with the one zero one selection circuit G101 be Example: 1/4 selects the coefficient of this line of FLT1 to take advantage of with X0～X7, then the cumulative value that obtains is as output.

Coefficient 5,10,11 corresponding for x2 with x5 has common portion (in table 5, respectively row), such as table 5 below Shown in:

Table 5

5x	1x		4x
					10x	2x	8x
11x	1x	2x		8x

Can obtain structure shown in Figure 12 A and Figure 12 B, Figure 12 A and Figure 12 B is all one of Figure 14 Point, refer to the detailed description of Figure 14.

Figure 12 A and Figure 12 B is the independent circuits that two structures are identical, and the data simply entered are different, For simplicity the structure that illustrate only Figure 12 A therein in Figure 14.

Coefficient 58,40,17 corresponding for x3 with x4 has common portion (in table 6, respectively row), such as table 6 below Shown in:

Table 6

58x		2x	8x	16x	32x
						40x	8x	32x
17x	1x			16x

Can obtain structure shown in Figure 13 A and Figure 13 B, Figure 13 A and Figure 13 B is all one of Figure 14 Point, refer to the detailed description of Figure 14.

Figure 13 A and Figure 13 B is the independent circuits that two structures are identical, and the data simply entered are different, For simplicity the structure that illustrate only Figure 13 A therein in Figure 14.

Embodiments provide a kind of HEVC interframe interpolation device, be used for realizing interframe single-point interpolation Luminance part, comprehensive figure 11 above～13 obtains the circuit diagram of fraction pixel point, as shown in figure 14.Bag Include: 16 shift registers, 16 adders and 18 selection circuits；

Two, the chrominance section of interframe single-point interpolation.

Secondly, interframe chroma interpolation filter factor general character is extracted.

Coefficient corresponding for x0 with x3 has common portion (respectively arranging in table 7), as shown in table 7 below:

Table 7

2x	2x
			4x	4x
6x	2x	4x

The part that structure shown in Figure 15 A and Figure 15 B, Figure 15 A and Figure 15 B are Figure 17 can be obtained, Refer to the detailed description of Figure 17.

Coefficient corresponding for x1 with x2 has common portion (respectively arranging in table 8), as shown in table 8 below:

Table 8

58x	2x		8x	16x	32x
						54x	2x	4x	16x	32x
46x	2x	4x	8x		32x
						36x		4x		32x
28x		4x	8x	16x
						16x			16x
10x	2x		8x

Can obtain structure shown in Figure 16 A and Figure 16 B, Figure 16 A and Figure 16 B is all one of Figure 17 Point, refer to the detailed description of Figure 17.

Figure 16 A and Figure 16 B is the independent circuits that two structures are identical, and the data simply entered are different, For simplicity the structure that illustrate only Figure 16 A therein in Figure 17.

Embodiments provide a kind of HEVC interframe interpolation device, be used for realizing interframe single-point interpolation Chrominance section, comprehensive figure 15 above A～16 obtains the circuit diagram of fraction pixel point, as shown in figure 17. Including: 14 shift registers, ten adders and 14 selection circuits；

In above example scheme, add with displacement and instead of multiplication operation, and well multiplexing logic money Source；Have only to calculate a fractional point corresponding to mark MV, reduce the complexity that algorithm realizes, than The interpolation of background technology obtains the structure of all fractional point, brightness interpolating aspect, depositor reduces 50%, Combination logic reduces the resource consumption of 40%；And well meet Merge prediction only output one point The requirement of several points.Merge prediction needs respectively to call 24 luminance level/vertical interpolation and 12 colourity water Flat/vertical interpolation unit, background technology scheme needs to consume 36179 register resources, 37739 groups Logical resource, embodiment of the present invention scheme consumes 15195 register resources, 20379 combination logiies Resource.

These are only the present invention preferably detailed description of the invention, but protection scope of the present invention is not limited to This, any those familiar with the art, can in the technical scope that the embodiment of the present invention discloses The change readily occurred in or replacement, all should contain within protection scope of the present invention.Therefore, the present invention Protection domain should be as the criterion with scope of the claims.

Claims

1. a HEVC interframe brightness multiple spot interpolating apparatus, it is characterised in that including: 14 displacements Depositor and 22 adders；

Wherein, described 14 shift registers comprise: input data are moved right 1 by four Shift register is followed successively by: the one one zero one shift register (A101), the one one zero two shift register (A102), the one one zero three shift register (A103), the one one zero four shift register (A104), Four shift registers of 2 of input data being moved right are followed successively by: the 2nd 101 shift register (B101), the 2nd 102 shift register (B102), the 2nd 103 shift register (B103), 2nd 104 shift register (B104), four shift registers of 3 that input data are moved right Be followed successively by: the 3rd 101 shift register (C101), the 3rd 102 shift register (C102), 3rd 103 shift register (C103), the 3rd 104 shift register (C104), two by defeated Enter the move right shift register of 4 of data to be followed successively by: the 4th 101 shift register (D101), 4th 102 shift register (D102)；

Wherein, described 22 adders comprise, 16 adders that input data are added, Be followed successively by: the one one zero three adder (E103), the one one zero four adder (E104), the 1st Five adders (E105), the one one zero six adder (E106), the one one zero seven adder (E107), One one zero eight adder (E108), the one one zero nine adder (E109), the first zero adder one by one (E110), the one one adder (E111), the first two adders (E112), first one by one one by one one by one Three adders (E113), first one by one five adders (E115), first one by one six adders (E116), First seven adders (E117), the first nine adders (E119), the one one two two adder one by one one by one (E122), six have the adder by being added function after input data-conversion, are followed successively by: the 2nd 1 01 adders (E101), the 2nd 102 adder (E102), second one by one four adders (E114), Second eight adders (E118), the 2nd 120 adder (E120), the 2nd 121 adder one by one (E121)；

X₀The 2nd 101 adder (E101), X is inputted as data₁The 2nd 10 is inputted as data One shift register (B101) and first zero adder (E110), X one by one₂First is inputted as data One zero one shift registers (A101), the one one zero three adder (E103) and the one one zero four adder (E104), X₃The one one zero three shift register (A103), the one one zero five addition is inputted as data Device (E105), the one one zero seven adder (E107) and the one one zero eight adder (E108), X₃Also Export as integral point, X₄As data input the one one zero six adder (E106), the one one zero seven add Musical instruments used in a Buddhist or Taoist mass (E107), the one one zero four shift register (A104) and the one one zero nine adder (E109), X₅As data input the one one two two adder (E122), the one one zero three adder (E103) with And the one one zero two shift register (A102), X₆The 2nd 102 shift register is inputted as data And the one one adder (E111), X one by one (B102)₇Add as input data input the 2nd 102 Musical instruments used in a Buddhist or Taoist mass (E102)；

The outfan of the 2nd 101 shift register (B101) connects the 2nd 101 adder (E101) Input, the outfan of the 2nd 101 adder (E101) connects the one one adder (E111) one by one With the first two adders (E112) one by one；The outfan of the 2nd 102 shift register (B102) connects 2nd 102 adder (E102), the outfan of the 2nd 102 adder (E102) connects the 1st One zero adders (E110) and first, two adders (E112) one by one, the first zero adder (E110) one by one Outfan connect the 2nd 121 adder (E121), the output of the first two adders (E112) one by one End connects the 2nd 120 adder (E120)；

The outfan of the one one zero one shift register (A101) connects the one one two two adder (E122), The outfan of the one one two two adder (E122) connect the 2nd 103 shift register (B103), the One Acanthopanan trifoliatus (L.) Merr. musical instruments used in a Buddhist or Taoist mass (E113) and first five adders (E115) one by one, the 2nd 103 shift LD one by one The outfan of device (B103) connects the first three adders (E113) one by one, the first three adders (E113) one by one Outfan connect the second four adders (E114) one by one；One one zero two shift register (A102) Outfan connects the one one zero four adder (E104), the outfan of the one one zero four adder (E104) Connect the 2nd 104 shift register (B104), first five adders (E115) and first are one by one one by one Six adders (E116)；The outfan of the 2nd 104 shift register (B104) connects first one by one six Adder (E116), the outfan of the one one zero three adder (E103) connects the 3rd 101 displacement and posts Storage (C101), outfan connection first five addition one by one of the 3rd 101 shift register (C101) Device (E115)；First one by one five adders (E115) outfan connect the 2nd 120 adder (E120), First one by one six adders (E116) outfan connect the 2nd 121 adder (E121)；

The outfan of the one one zero three shift register (A103) connects the one one zero six adder (E106) With the one one zero five adder (E105), the outfan of the one one zero five adder (E105) connects the 3rd One zero two shift registers (C102), the outfan of the 3rd 102 shift register (C102) connects the One seven adders (E117) one by one；The outfan of the one one zero six adder (E106) connects the 4th 10 One shift register (D101) and first, seven adders (E117) one by one, the 4th 101 shift register (D101) outfan connection first seven adders (E117) and second, eight adders (E118) one by one one by one； The outfan of the one one zero seven adder (E107) connects the 3rd 103 shift register (C103), the Outfan connection second eight adders (E118) one by one of 3103 shift registers (C103)；First The outfan of one zero four shift registers (A104) connects the one one zero eight adder (E108) and first One zero nine adders (E109), the outfan of the one one zero nine adder (E109) connects the 3rd 104 Shift register (C104), the outfan of the 3rd 104 shift register (C104) connects first one by one Nine adders (E119)；The outfan of the one one zero eight adder (E108) connects the 4th 102 displacement Depositor (D102) and first nine adders (E119) one by one, the 4th 102 shift register (D102) Outfan connect the second eight adders (E118) and first, nine adders (E119) one by one one by one；First The outfan of one adder (E111) one by one connects the second four adders (E114) one by one, and first one by one seven The outfan of adder (E117) connects the second four adders (E114) one by one, the second eight adder one by one (E118) outfan connects the 2nd 120 adder (E120), the first nine adders (E119) one by one Outfan connect the 2nd 121 adder (E121)；

Wherein, the 2nd 101 adder (E101) X to input₀Negate, the 2nd 102 adder (E102) X to input₇Negate, second one by one four adders (E114) to from the first three addition one by one Data-conversion that device (E113) inputs, second one by one eight adders (E118) move from the 3rd 103 Data-conversion that bit register (C103) inputs, the 2nd 120 adder (E120) are to from the 1st Data-conversion that First Five-Year Plan adder (E115) inputs, the 2nd 121 adder (E121) are to from first The data-conversion that six adders (E116) input one by one；

Second one by one four adders (E114) export first fractional point FLT1, the 2nd 120 adder (E120) second fractional point FLT2 of output, the 2nd 121 adder (E121) exports three point Several somes FLT3.

2. a HEVC interframe colourity multiple spot interpolating apparatus, it is characterised in that including: 14 displacements Depositor, 24 adders and five SYN registers；

Wherein, described 14 shift registers comprise: five shiftings of 1 of input data being moved right Bit register is followed successively by: the one one zero five shift register (A105), the one one zero six shift register (A106), the one one zero seven shift register (A107), the one one zero eight shift register (A108), One one zero nine shift register (A109)；Three shift registers of 2 that input data are moved right Be followed successively by: the 2nd 105 shift register (B105), the 2nd 106 shift register (B106), 2nd 107 shift register (B107), two shift registers of 3 that input data are moved right It is followed successively by: the 3rd 105 shift register (C105), the 3rd 106 shift register (C106), Two shift registers of 4 of input data being moved right are followed successively by: the 4th 103 shift register (D103), the 4th 104 shift register (D104)；Input data are moved right 5 by two Shift register is followed successively by: shift register on May Day 01 (F101), shift register on May Day 02 (F102)；

Wherein, described 24 adders comprise, 17 adders that input data are added, Be followed successively by: the one one two three adder (E123), the one one two four adder (E124), the 1st Five adders (E125), the one one two six adder (E126), the one one two seven adder (E127), One one sixteen adder (E128), the one one two nine adder (E129), the one one three zero adder (E130), the one one three one adder (E131), the one one three two adder (E132), the 1st Three adders (E133), the one one three four adder (E134), the one one three five adder (E135), One one three six adder (E136), the one one Radix Notoginseng adder (E137), the one one three eight adder (E138), the one one four six adder (E146), seven have and are added merit after input data-conversion Can adder, be followed successively by: the 2nd 1 three nine-day periods after the winter solstice adder (E139), the 2nd 140 adder (E140), 2nd 141 adder (E141), the 2nd 142 adder (E142), the 2nd 143 adder (E143), the 2nd 144 adder (E144), the 2nd 145 adder (E145)；

Five SYN registers with clock synchronizing function, are followed successively by: the one zero one SYN register (H101), the one zero two SYN register (H102), the one zero three SYN register (H103), One zero four SYN registers (H104), the one zero five SYN register (H105)；

X₀The one one zero six shift register (A106) and the one one four six adder is inputted as data (E146), X₁As data input the one one zero five shift register (A105), the 2nd 105 displacement Depositor (B105), the 3rd 105 shift register (C105), the 4th 103 shift register And shift register on May Day 01 (F101), X (D103)₁Also export as integral point, X₂As Data input the one one zero nine shift register (A109), the 2nd 107 shift register (B107), 3rd 106 shift register (C106), the 4th 104 shift register (D104) and May Day zero Two shift registers (F102), X₃The one one four six adder (E146) and the 1st is inputted as data 08 shift registers (A108)；

The outfan of the one one zero five shift register (A105) connect the one one two three adder (E123), One one two four adder (E124), the one one two five adder (E125) and the one one sixteen adder (E128), the outfan of the 2nd 105 shift register (B105) connects the one one two four adder (E124), the one one two five adder (E125), the one one two six adder (E126) and the 1st Two or seven adders (E127), the outfan of the 3rd 105 shift register (C105) connects the 1st Three adders (E123), the one one two five adder (E125), the one one two seven adder (E127) With the one one sixteen adder (E128), the outfan of the 4th 103 shift register (D103) connects One one two three adder (E123), the one one two four adder (E124), the one one two seven adder (E127) and the one zero one SYN register (H101), shift register on May Day 01 (F101) Outfan connect the one one two three adder (E123), the one one two four adder (E124), the 1st Two or five adders (E125) and the one one two six adder (E126)；One one two three adder (E123) Outfan connect the 2nd 1 three nine-day periods after the winter solstice adder (E139), the output of the one one two four adder (E124) End connects the 2nd 140 adder (E140), the outfan of the one one two five adder (E125) connects 2nd 141 adder (E141), the outfan of the one one two six adder (E126) connect the 2nd 1 Four or two adders (E142), the outfan of the one one two seven adder (E127) connect the 2nd 14 Acanthopanan trifoliatus (L.) Merr. Musical instruments used in a Buddhist or Taoist mass (E143), the outfan of the one zero one SYN register (H101) connect the 2nd 144 adder (E144), the outfan of the one one sixteen adder (E128) connects the 2nd 145 adder (E145)；

The outfan of the one one zero six shift register (A106) connects the one one two nine adder (E129) With the one one three zero adder (E130), the outfan of the one one four six adder (E146) connects first One zero seven shift registers (A107) and the 2nd 106 shift register (B106), the one one zero eight moves The outfan of bit register (A108) connects the one one three one adder (E131) and the 1st and adds Musical instruments used in a Buddhist or Taoist mass (E132), the outfan of the one one zero seven shift register (A107) connects the one zero two synchronization and posts Storage (H102), the one one two nine adder (E129), the one one three two adder (E132) and One zero four SYN registers (H104), the outfan of the one one zero six shift register (A106) connects One one three zero adder (E130), the one zero three SYN register (H103) and the one one three one addition Device (E131), the outfan of the one zero two SYN register (H102) connects the 2nd 1 three nine-day periods after the winter solstice adder (E139), the outfan of the one one two nine adder (E129) connects the 2nd 140 adder (E140), Outfan connection the 2nd 141 adder (E141) of the one one three zero adder (E130), the one zero Outfan connection the 2nd 142 adder (E142) of three SYN registers (H103), the one one three one The outfan of adder (E131) connects the 2nd 143 adder (E143), the one one three two adder (E132) outfan connects the 2nd 144 adder (E144), the one zero four SYN register (H104) outfan connects the 2nd 145 adder (E145)；

The outfan of the one one zero nine shift register (A109) connect the one one three three adder (E133), One one three six adder (E136), the one one Radix Notoginseng adder (E137) and the one one three eight adder (E138), the outfan of the 2nd 107 shift register (B107) connects the one one three four adder (E134), the one one three five adder (E135), the one one three six adder (E136) and the 1st Radix Notoginseng adder (E137), the outfan of the 3rd 106 shift register (C106) connects the 1st Three adders (E133), the one one three four adder (E134), the one one three six adder (E136) With the one one three eight adder (E138), the outfan of the 4th 104 shift register (D104) connects One zero five SYN register (H105), the one one three four adder (E134), the one one Radix Notoginseng addition Device (E137) and the one one three eight adder (E138), shift register on May Day 02 (F102) Outfan connect the one one three five adder (E135), the one one three six adder (E136), the 1st Radix Notoginseng adder (E137) and the one one three eight adder (E138)；

The outfan of the one one three three adder (E133) connects the 2nd 1 three nine-day periods after the winter solstice adder (E139), the Outfan connection the 2nd 140 adder (E140) of one zero five SYN registers (H105), the one one The outfan of three or four adders (E134) connects the 2nd 141 adder (E141), the one one three slender acanthopanax The outfan of musical instruments used in a Buddhist or Taoist mass (E135) connects the 2nd 142 adder (E142), the one one three six adder (E136) outfan connects the 2nd 143 adder (E143), the one one Radix Notoginseng adder (E137) Outfan connect the 2nd 144 adder (E144), the output of the one one three eight adder (E138) End connects the 2nd 145 adder (E145)；

The 2nd 1 three nine-day periods after the winter solstice adder (E139) number to inputting from the one zero two SYN register (H102) According to negating, the 2nd 140 adder (E140) is to inputting from the one one two nine adder (E129) Data-conversion, the 2nd 141 adder (E141) are to from the one one three zero adder (E130) input Data-conversion, the 2nd 142 adder (E142) is to from the one zero three SYN register (H103) The data-conversion of input, the 2nd 143 adder (E143) are to from the one one three one adder (E131) The data-conversion of input, the 2nd 144 adder (E144) are to from the one one three two adder (E132) The data-conversion of input, the 2nd 145 adder (E145) are to from the one zero four SYN register (H104) The data-conversion of input；

Outfan first fractional point FLT1 of output of the 2nd 1 three nine-day periods after the winter solstice adder (E139), the 2nd 14 Outfan second fractional point FLT2 of output of zero adder (E140), the 2nd 141 adder (E141) Outfan export the 3rd fractional point FLT3, the output of the outfan of the 2nd 142 adder (E142) 4th fractional point FLT4, the outfan of the 2nd 143 adder (E143) exports the 5th fractional point FLT5, the outfan of the 2nd 144 adder (E144) exports the 6th fractional point FLT6, and the 2nd 1 The outfan of four or five adders (E145) exports the 7th fractional point FLT7.

3. a HEVC interframe brightness single-point interpolating apparatus, it is characterised in that including: 16 displacements Depositor, 16 adders and 18 selection circuits；

Wherein, described 16 shift registers comprise: four shiftings of 1 of input data being moved right Bit register is followed successively by: the first zero shift register (A110), the one one shift register one by one one by one (A111), the one one First Five-Year Plan shift register (A115), the first six shift registers (A116) one by one, Four shift registers of 2 of input data being moved right are followed successively by: the 2nd 108 shift register (B108), the 2nd 109 shift register (B109), second one by one zero shift register (B110), Second four shift registers (B114) one by one, four shift registers of 3 that input data are moved right Be followed successively by: the 3rd 107 shift register (C107), the 3rd 108 shift register (C108), 3rd zero shift register (C110), the 3rd 1 shift register (C111) one by one one by one, two by defeated Enter data to move right the shift register of 4: the 4th 105 shift register (D105), the 4th 1 07 shift registers (D107), two shift registers of 5 that input data are moved right: the 5th One zero three shift registers (F103), shift register on May Day 05 (F105)；

Described 16 adders comprise: 14 adders input data being added, and are followed successively by: the Four or seven adders (E147), the one one four eight adder (E148), the one one four nine adder one by one (E149), the one one adder on May Day (E151), the first First Five-Year Plan two adder (E152), the first First Five-Year Plan Four adders (E154), the first First Five-Year Plan five adder (E155), the first First Five-Year Plan six adder (E156), One one six four adder (E164), the first parathion adder (E165), the one one six six adder (E166), the one one six seven adder (E167), the one one six eight adder (E168), the 1st Nine adders (E169), two have the adder by being added function after input data-conversion, are followed successively by: Second First Five-Year Plan zero adder (E150), the second First Five-Year Plan three adder (E153)；

18 selection circuits are followed successively by: the one zero one selection circuit (G101), the one zero two selection circuit (G102), the one zero three selection circuit (G103), the one zero four selection circuit (G104), the 1st Five selection circuits (G105), the one zero six selection circuit (G106), the one zero seven selection circuit (G107), One zero eight selection circuit (G108), the one zero nine selection circuit (G109), the one one zero option circuit (G110), first one by one selection circuit (G111), the one two one selection circuit G (121), the one or two Two selection circuits (G122), the one two three selection circuit (G123), the one two four selection circuit (G124), One two five selection circuit (G125), the one two six selection circuit (G126), the one two seven selection circuit (G127)；

X₀The one zero one selection circuit (G101), X is inputted as data₁The 1st is inputted as data Selection circuit (G103) and the 2nd 108 shift register (B108), X₂The 3rd is inputted as data One zero eight shift registers (C108), second one by one zero shift register (B110), the one one move one by one Bit register (A111) and the one one zero option circuit (G110), X₅As data input the 3rd one by one One shift register (C111), second one by one four shift registers (B114), first one by one six displacement post Storage (A116) and the one two seven selection circuit (G127), X₃Shifting on May Day 03 is inputted as data Bit register (F103), the 3rd 107 shift register (C107), the 4th 105 shift register (D105), the first zero shift register (A110) and the one zero six selection circuit (G106) one by one, X₄Shift register on May Day 03 (F105), the 3rd zero shift register one by one is inputted as data (C110), the 4th 107 shift register (D107), the one one First Five-Year Plan shift register (A115) And the one two two selection circuit (G122), X₆The one zero four selection circuit (G104) is inputted as data With the 2nd 109 shift register (B109), X₇As input data input the one zero two selection circuit (G102)；Constant 0 inputs the one zero one selection circuit (G101), the one zero two selection circuit the most respectively (G102), the one zero five selection circuit (G105), the one zero six selection circuit (G106), the 1st Seven selection circuits (G107), the one zero eight selection circuit (G108), the one zero nine selection circuit (G109), One one zero option circuit (G110) and first selection circuit (G111), the one two one selection circuit one by one (G121), the one two two selection circuit (G122), the one two four selection circuit (G124), the one or two Five selection circuits (G125), the one two six selection circuit (G126), the one two seven selection circuit (G127) With the one two three selection circuit (G123)；

The outfan of the 2nd 108 shift register (B108) connects the one zero three selection circuit (G103), The outfan of the 2nd 109 shift register (B109) connects the one zero four selection circuit (G104), the Outfan connection the one one four seven adder (E147) of one zero one selection circuits (G101), the one zero two The outfan of selection circuit (G102) connects the one one four seven adder (E147), the one one four seven addition The outfan of device (E147) connects the second First Five-Year Plan zero adder (E150), the one zero three selection circuit (G103) Outfan connect the one one four eight adder (E148), the output of the one zero four selection circuit (G104) End connects the one one four eight adder (E148), and the outfan of the one one four eight adder (E148) connects Second First Five-Year Plan zero adder (E150), the outfan of the second First Five-Year Plan zero adder (E150) connects the 2nd 1 Five or three adders (E153)；

The outfan on shift register on May Day 05 (F105) connects the one one six four adder (E164), The outfan of the 3rd zero shift register (C110) one by one connects the one one six four adder (E164), and the The outfan of 4107 shift registers (D107) connects the one two one selection circuit (G121), the The outfan of First Five-Year Plan shift register (A115) connects the one two two selection circuit (G122) one by one, the Outfan connection the one two three selection circuit (G123) of six or four adders (E164) one by one, the one two one The outfan of selection circuit (G121) connects the first parathion adder (E165), and the one two two selects electricity The outfan on road (G122) connects the first parathion adder (E165), the one two three selection circuit (G123) Outfan connect the one one six six adder (E166), the output on the one one adder on May Day (E151) End connects the one one six six adder (E166), and the outfan of the one one six six adder (E166) connects Second First Five-Year Plan three adder (E153)；

The outfan on shift register on May Day 03 (F103) connects the one one four nine adder (E149), The outfan of the 3rd 107 shift register (C107) connects the one one four nine adder (E149), the The outfan of 4105 shift registers (D105) connects the one zero five selection circuit (G105), the The outfan of one zero shift register (A110) one by one connects the one zero six selection circuit (G106), and the Outfan connection first selection circuit (G111) one by one of four or nine adders (E149) one by one, the one zero five The outfan of selection circuit (G105) connected for the one one adder on May Day (E151), and the one zero six selects electricity The outfan on road (G106) connected for the one one adder on May Day (E151), the first selection circuit (G111) one by one Outfan connect the first First Five-Year Plan two adder (E152), the output on the one one adder on May Day (E151) End connected for the first First Five-Year Plan two adder (E152), and the outfan of the first First Five-Year Plan two adder (E152) connects Second First Five-Year Plan three adder (E153)；

3rd 1 one by one shift register (C111) outfan connect the one two four selection circuit (G124), The outfan of the second four shift registers (B114) one by one connects the one two five selection circuit (G125), and the The outfan of one six shift registers (A116) one by one connects the one two six selection circuit (G126), and the Outfan connection the one one six seven adder (E167) of one two four selection circuits (G124), the one two five The outfan of selection circuit (G125) connects the one one six seven adder (E167), and the one two six selects electricity The outfan on road (G126) connects the one one six eight adder (E168), the one one zero option circuit (G110) Outfan connect the one one six eight adder (E168), the output of the one one six seven adder (E167) End connects the one one six nine adder (E169), and the outfan of the one one six eight adder (E168) connects One one six nine adder (E169), the outfan of the one one six nine adder (E169) connects the 2nd 1 Five or three adders (E153)；

The outfan of the 3rd 108 shift register (C108) connects the one zero seven selection circuit (G107), The outfan of the second zero shift register (B110) one by one connects the one zero eight selection circuit (G108), and the Outfan connection the one zero nine selection circuit (G109) of shift register (A111) the most one by one, first The outfan of 07 selection circuits (G107) connects the one one the May 4th adder (E154), the one zero eight choosing The outfan selecting circuit (G108) connects the one one the May 4th adder (E154), the one zero nine selection circuit (G109) outfan connects the first First Five-Year Plan five adder (E155), the one one zero option circuit (G110) Outfan connect the first First Five-Year Plan five adder (E155), the output of the one one the May 4th adder (E154) End connected for the first First Five-Year Plan six adder (E156), and the outfan of the first First Five-Year Plan five adder (E155) connects First First Five-Year Plan six adder (E156), the outfan of the first First Five-Year Plan six adder (E156) connects the 2nd 1 Five or three adders (E153)；

Second First Five-Year Plan zero adder (E150) data to inputting from the one one four seven adder (E147) Negate, second First Five-Year Plan three adder (E153) number to inputting from the first First Five-Year Plan six adder (E156) According to negating；

The output data of the second First Five-Year Plan three adder (E153) are as brightness fraction pixel point.

4. a HEVC interframe colourity single-point interpolating apparatus, it is characterised in that including: 14 displacements Depositor, ten adders and 14 selection circuits；

Wherein, described 14 shift registers comprise: four shiftings of 1 of input data being moved right Bit register is followed successively by: the first two shift registers (A112), the first three shift register one by one one by one (A113), the first four shift registers (A114), the first seven shift registers (A117) one by one one by one, Four shift registers of 2 of input data being moved right are followed successively by: the 2nd 1 shift register one by one (B111), second one by one two shift registers (B112), second one by one three shift registers (B113), 2nd 1 First Five-Year Plan shift register (B115), two shift registers of 3 that input data are moved right: 3rd 109 shift register (C109), the 3rd two shift registers (C112) one by one, two by defeated Enter data to move right the shift register of 4: the 4th 106 shift register D106, the 4th 10 Eight shift registers (D108), two shift registers of 5 that input data are moved right: May Day 04 shift register F104, shift register on May Day 06 (F106)；

Described ten adders comprise: six adders input data being added, and are followed successively by: the 1st Five or seven adders (E157), the first First Five-Year Plan eight adder (E158), the first First Five-Year Plan nine adder (E159), One one six zero adder (E160), the one one six one adder (E161), the one one six two adder (E162), four adders having being added function after input data-conversion: the 2nd 163 addition Device (E163), the one one seven zero adder (E170), the first 171 adder (E171), the 1st Seven or two adders (E172)；

14 selection circuits are followed successively by: the one one two selection circuit (G112), the one one three selection circuit (G113), the one one four selection circuit (G114), the first First Five-Year Plan selection circuit (G115), the 1st Six selection circuits (G116), the one one seven selection circuit (G117), the one one eight selection circuit (G118), One one nine selection circuit (G119), the one or two zero option circuit (G120), the one sixteen selection circuit (G128), the one two nine selection circuit (G129), the one or three zero option circuit (G130), the one or three One selection circuit (G131), the one three two selection circuit (G132)；

X₀As data input first three shift registers (A113) and second, two shift LD one by one one by one Device (B112), X₁Shift register on May Day 04 (F104), the 4th 106 shifting is inputted as data Bit register (D106), the 3rd 109 shift register (C109), the 2nd 1 shift register one by one (B111) and the first two shift registers (A112), X one by one₂Shifting on May Day 06 is inputted as data Bit register (F106), the 4th 108 shift register (D108), the 3rd two shift register one by one (C112), the 2nd 1 First Five-Year Plan shift register (B115) and first seven shift registers (A117) one by one, X₃As data input first four shift registers (A114) and second, three shift register one by one one by one (B113)；Constant 0 inputs the one one two selection circuit (G112), the one one three selection circuit the most respectively (G113), the one one four selection circuit (G114), the first First Five-Year Plan selection circuit (G115), the 1st Six selection circuits (G116), the one one four selection circuit (G114), the one one eight selection circuit (G118), One one nine selection circuit (G119), the one sixteen selection circuit (G128), the one two nine selection circuit (G129), the one or three zero option circuit (G130), the one three one selection circuit (G131), the one or three Two selection circuits (G132) and the one or two zero option circuit (G120)；

The outfan on shift register on May Day 04 (F104) connects the one one two selection circuit (G112), The outfan of the 4th 106 shift register (D106) connects the one one three selection circuit (G113), The outfan of the 3rd 109 shift register (C109) connects the one one four selection circuit (G114), the The outfan of 211 one shift register (B111) connects the first First Five-Year Plan selection circuit (G115), and first Outfan connection the one one six selection circuit (G116) of two shift registers (A112) one by one, the one one The outfan of two selection circuits (G112) connected for the first First Five-Year Plan seven adder (E157), and the one one three selects The outfan of circuit (G113) connects the first First Five-Year Plan seven adder (E157), the one one four selection circuit (G114) outfan connects the one one six one adder (E161), the first First Five-Year Plan selection circuit (G115) Outfan connect the first First Five-Year Plan eight adder (E158), the output of the one one six selection circuit (G116) End connected for the first First Five-Year Plan eight adder (E158), and the outfan of the first First Five-Year Plan seven adder (E157) connects One one six one adder (E161), the outfan of the first First Five-Year Plan eight adder (E158) connects the 1st 61 adders (E161)；

The outfan on shift register on May Day 06 (F106) connects the one sixteen selection circuit (G128), The outfan of the 4th 108 shift register (D108) connects the one two nine selection circuit (G129), The outfan of the 3rd two shift registers (C112) one by one connects the one or three zero option circuit (G130), and the Outfan connection the one three one selection circuit (G131) of 211 five shift register (B115), first Outfan connection the one three two selection circuit (G132) of seven shift registers (A117) one by one, first The outfan of sixteen selection circuits (G128) connects the one one seven zero adder (E170), the one two nine choosing The outfan selecting circuit (G129) connects the one one seven zero adder (E170), the one or three zero option circuit (G130) outfan connects the one one seven two adder (E172), the one three one selection circuit (G131) Outfan connect the first 171 adder (E171), the output of the one three two selection circuit (G132) End connects the first 171 adder (E171), and the outfan of the first 171 adder (E171) connects One one seven two adder (E172), the outfan of the first 171 adder (E171) connects the 1st Seven or two adders (E172)；

First one by one three shift registers (A113) outfan connect the one one seven selection circuit (G117), The outfan of the second two shift registers (B112) one by one connects the one one eight selection circuit (G118), and the The outfan of seven selection circuits (G117) connected for the first First Five-Year Plan nine adder (E159) one by one, and the one one eight The outfan of selection circuit (G118) connected for the first First Five-Year Plan nine adder (E159)；First four displacement one by one The outfan of depositor (A114) connects the one one nine selection circuit (G119), second one by one three displacements post The outfan of storage (B113) connects the one or two zero option circuit (G120), the one one nine selection circuit (G119) outfan connects the one one six zero adder (E160), the one or two zero option circuit (G120) Outfan connect the one one six zero adder (E160)；The output of the first First Five-Year Plan nine adder (E159) End connects the one one six two adder (E162), and the outfan of the one one six zero adder (E160) connects One one six two adder (E162)；

The outfan of the one one six one adder (E161) and the one one seven two adder (E172) Outfan connects the 2nd 163 adder (E163), the outfan of the one one six two adder (E162) Connecting the 2nd 163 adder (E163), the 2nd 163 adder (E163) is to from the 1st The data-conversion that adder (E162) inputs, the output data of the 2nd 163 adder (E163) are made For colourity fraction pixel point.