CN103533350A

CN103533350A - HEVC (High Efficiency Video Coding) inter-frame interpolation device

Info

Publication number: CN103533350A
Application number: CN201310446341.7A
Authority: CN
Inventors: 郑海伟; 高剑; 刘钦
Original assignee: Huawei Technologies Co Ltd
Current assignee: Shenzhen Huawei Cloud Computing Technology Co ltd
Priority date: 2013-09-26
Filing date: 2013-09-26
Publication date: 2014-01-22
Anticipated expiration: 2033-09-26
Also published as: CN103533350B

Abstract

The embodiment of the invention discloses an HEVC (High Efficiency Video Coding) inter-frame interpolation device. An HEVC inter-frame brightness multi-point interpolation device comprises fourteen shifting registers and twenty-two adders, wherein the fourteen shifting registers include four shifting registers capable of moving input data rightwards for one bit, four shifting registers capable of moving the input data rightwards for two bits, four shifting registers capable of moving the input data rightwards for three bits, and two shifting registers capable of moving the input data rightwards for four bits, wherein the twenty-two adders include sixteen adders capable of adding the input data, and six adders capable of adding the input data after negation.

Description

A kind of HEVC interframe interpolation device

Technical field

The present invention relates to electroporation field, particularly a kind of HEVC(High Efficiency Video Coding, efficient video coding) interframe interpolation device.

Background technology

Vision signal comprises huge amount of information, with CIF(common intermediate format, CLV Common Intermediate Format: vision signal 352 * 288) is example, if without any compression, speed with 30 frames per second is transmitted, and the code check of transmission reaches 70Mbps, same, if above-mentioned vision signal is not compressed, the normal optical disk of a 700M can only be stored the video of 80 seconds.Therefore, technology of video compressing encoding is extremely urgent efficiently.

Although vision signal has comprised huge amount of information, but these information are height correlation often, exist a large amount of redundant informations, as: in image sequence, two adjacent images often comprise identical background and mobile object, just the locus of object is slightly different, and the later data of a frame of institute and the data of former frame have many identical places (time redundancy); In any piece image, all by by many gray scales or the color region that all identical or close neighborhood pixels forms, therefore these pixel Existential Space continuities, but based on discrete pixel sampling, represent that the mode of object color do not utilize this space continuity (spatial redundancy); Exist in addition coding redundancy, visual redundancy etc.

The principle of video compression coding and starting point are just to eliminate to greatest extent various redundancies.For different redundancies, video compression coding standard adopts different strategies to eliminate.The general scheme adopting is: with inter prediction, eliminate time redundancy; With infra-frame prediction, eliminate spatial redundancy; With conversion, quantification, eliminate visual redundancy; With entropy coding, eliminate coding redundancy.

At present mainly contain in the world two and be organized in research and the formulation of carrying out video compression coding standard, be respectively ITU-T(International Telecommunication Union, International Telecommunications Union) and MPEG(Moving Pictures Experts Group, dynamic image expert group).At present the video compression coding standard of main flow is for H.264(MPEG-4Part10, the advanced video coding of dynamic image expert group-4).HEVC(High Efficiency Video Coding, efficient video coding) as video compression coding standard of future generation, code check after video compression only have H.264 50%, realized the business model that current most advanced coded system cannot realize, as: by the 3DTV(Three Dimensions television of full resolution, three-dimensional television) or even in 4K video compression high definition coding pass up till now, have huge market prospects, cost is the raising of algorithm complex and the increase that realizes cost.

In order to improve the accuracy of inter prediction, in the draft of HEVC by the pattern of inter prediction at FME(Fractional Motion Estimate H.264, fraction movement is estimated) increased a kind of Merge(in frame foundation and merge) prediction, prediction piece is increased to 4 * 4,8 * 8,16 * 16,32 * 32 and 64 * 64 5 layers by H.264 4 * 4,8 * 8 and 16 * 16 3 layers.

Inter prediction is as one of major part of HEVC, and the accuracy of prediction directly has influence on the effect of video compression coding, and FME and Merge are the major parts of inter prediction.In order to improve the precision of predict pixel, FME carries out the search of 1/4 precision to brightness, colourity is carried out the search of 1/8 precision, between two integer luminance pixels, interpolation obtains 3 fraction pixel points (mainly by each 4 integer pixel points of left and right, by 3 groups of filters, obtain respectively), between two integer chroma pixels, interpolation obtains 7 fraction pixel points (mainly by each 2 integer pixel points of left and right, by 7 groups of filters, obtain respectively), need to consume tens Horizontal interpolation unit and vertical interpolating unit.Merge is mainly by the MV/CandIdx(Motion Vector/Candidate Index of contiguous block (spatial domain and time domain): motion vector/candidate index) the MV/CandIdx information of information substitution current block, according to brightness MV and colourity MV, respectively select 1 optimum some output from 3 brightness fraction pixel points and 7 colourity fraction pixel points respectively again, Interpolation Process also needs to consume a large amount of Horizontal interpolation unit and vertical interpolating unit.

Known based on introducing above: no matter be FME or Merge, using logic hardware to realize all needs to use a large amount of interpolating unit, and the logical resource of its amount of calculation and consumption accounts for 25% of whole HEVC project proportion, and the cost of logic realization is higher.

Adopt above scheme, in order to complete the interpolation of 3 brightness fraction pixel points and 7 colourity fraction pixel points, need 3 independently brightness interpolating filter and 7 chroma interpolation filters, each interpolating unit of each interpolation filter is separate.In order to improve the real-time of HEVC video compression coding, need to be at FPGA(Field Programmable Gate Array, field programmable gate array) or ASIC(Application-Specific Integrated Circuit, application-specific integrated circuit (ASIC)) upper logic realization HEVC video compression coding; And FME and Merge need to consume a large amount of interpolating unit, due to separate between each group filter, consume logical resource more, be unfavorable for hardware realization.

Summary of the invention

The embodiment of the present invention provides a kind of HEVC interframe interpolation device, for reducing the consumption of logical resource.

The embodiment of the present invention provides a kind of HEVC interframe brightness multiple spot interpolating apparatus, comprising: 14 shift registers and 22 adders;

Wherein, in described 14 shift registers, comprise: four are followed successively by the move right shift register of 1 of input data: the one one zero one shift register A101, the one one zero two shift register A102, the one one zero three shift register A103, the one one zero four shift register A104, four are followed successively by the move right shift register of 2 of input data: the 2101 shift register B101, the 2102 shift register B102, the 2103 shift register B103, the 2104 shift register B104, four are followed successively by the move right shift register of 3 of input data: the 3101 shift register C101, the 3102 shift register C102, the 3103 shift register C103, the 3104 shift register C104, two are followed successively by the move right shift register of 4 of input data: the 4101 shift register D101, the 4102 shift register D102,

Wherein, in described 22 adders, comprise, 16 adders that input data are added, are followed successively by: the one one zero three adder E103, the one one zero four adder E104, the one one zero slender acanthopanax musical instruments used in a Buddhist or Taoist mass E105, the one one zero six adder E106, the one one zero seven adder E107, the one one zero eight adder E108, the one one zero nine adder E109, the first zero adder E110 one by one, the one one adder E111 one by one, the first two adder E112 one by one, the first three adder E113 one by one, the first slender acanthopanax musical instruments used in a Buddhist or Taoist mass E115 one by one, the first six adder E116 one by one, the first seven adder E117 one by one, the first nine adder E119 one by one, the one one two two adder E122, six have the adder that input data-conversion is added later to function, are followed successively by: the 2101 adder E101, the 2102 adder E102, the second four adder E114 one by one, the second eight adder E118 one by one, the 2120 adder E120, the 2121 adder E121,

Eight brightness integral points are followed successively by X ₀, X ₁, X ₂, X ₃, X ₄, X ₅, X ₆, X ₇;

X ₀as data input the 2101 adder E101, X ₁as data, input the 2101 shift register B101 and first zero adder E110 one by one, X ₂as data input the one one zero one shift register A101, the one one zero three adder E103 and the one one zero four adder E104, X ₃as data input the one one zero three shift register A103, the one one zero slender acanthopanax musical instruments used in a Buddhist or Taoist mass E105, the one one zero seven adder E107 and the one one zero eight adder E108, X ₃also as integral point output, X ₄as data input the one one zero six adder E106, the one one zero seven adder E107, the one one zero four shift register A104 and the one one zero nine adder E109, X ₅as data input the one one two two adder E122, the one one zero three adder E103 and the one one zero two shift register A102, X ₆as data, input the 2102 shift register (B102) and the 1 adder E111 one by one, X ₇as input data input the 2102 adder E102;

The output of the 2101 shift register B101 connects the input of the 2101 adder E101, and the output connection the 1 of the 2101 adder E101 is adder E111 and first two adder E112 one by one one by one; The output of the 2102 shift register (B102) connects the 2102 adder E102, the output of the 2102 adder E102 connects the first zero adder E110 and first, two adder E112 one by one one by one, first one by one the output of zero adder E110 connect the 2121 adder E121, first one by one the output of two adder E112 connect the 2120 adder E120;

The output of the one one zero one shift register A101 connects the one one two two adder E122, the output of the one one two two adder E122 connects the 2103 shift register B103, first three adder E113 and first slender acanthopanax musical instruments used in a Buddhist or Taoist mass E115 one by one one by one, the output of the 2103 shift register B103 connects the first three adder E113 one by one, first one by one the output of three adder E113 connect the second four adder E114 one by one; The output of the one one zero two shift register A102 connects the one one zero four adder E104, and output connection the 2104 shift register B104, first of the one one zero four adder E104 is slender acanthopanax musical instruments used in a Buddhist or Taoist mass E115 and first six adder E116 one by one one by one; The output connection first of the 2104 shift register B104 is six adder E116 one by one, the output of the one one zero three adder E103 connects the 3101 shift register C101, and the output connection first of the 3101 shift register C101 is slender acanthopanax musical instruments used in a Buddhist or Taoist mass E115 one by one; First one by one the output of slender acanthopanax musical instruments used in a Buddhist or Taoist mass E115 connect the 2120 adder E120, the first output connection the 2121 adder E121 of six adder E116 one by one;

The output of the one one zero three shift register A103 connects the one one zero six adder E106 and the one one zero slender acanthopanax musical instruments used in a Buddhist or Taoist mass E105, the output of the one one zero slender acanthopanax musical instruments used in a Buddhist or Taoist mass E105 connects the 3102 shift register C102, and the output connection first of the 3102 shift register C102 is seven adder E117 one by one; The output of the one one zero six adder E106 connects the 4101 shift register D101 and first seven adder E117 one by one, and the output connection first of the 4101 shift register D101 is seven adder E117 and second, eight adder E118 one by one one by one; The output of the one one zero seven adder E107 connects the 3103 shift register C103, and the output connection second of the 3103 shift register C103 is eight adder E118 one by one; The output of the one one zero four shift register A104 connects the one one zero eight adder E108 and the one one zero nine adder E109, the output of the one one zero nine adder E109 connects the 3104 shift register C104, and the output connection first of the 3104 shift register C104 is nine adder E119 one by one; The output of the one one zero eight adder E108 connects the 4102 shift register D102 and first nine adder E119 one by one, and the output connection second of the 4102 shift register D102 is eight adder E118 and first, nine adder E119 one by one one by one; The 1 one by one the output of adder E111 connect the second four adder E114 one by one, first one by one the output of seven adder E117 connect the second four adder E114 one by one, second one by one the output of eight adder E118 connect the 2120 adder E120, the first output connection the 2121 adder E121 of nine adder E119 one by one;

Wherein, the X of the 2101 adder E101 to input ₀negate, the X of the 2102 adder E102 to input ₇negate, second one by one four adder E114 to from first one by one three adder E113 inputs data-conversion, second one by one eight adder E118 to the data-conversion from the 3103 shift register C103 input, the 2120 adder E120 to from the first data-conversion that slender acanthopanax musical instruments used in a Buddhist or Taoist mass E115 inputs one by one, the 2121 adder E121 to from the first data-conversion that six adder E116 input one by one;

Second one by one four adder E114 export first fractional point FLT1, second fractional point FLT2 of the 2120 adder E120 output, the 3rd fractional point FLT3 of the 2121 adder E121 output.

An interframe colourity multiple spot interpolating apparatus, comprising: 14 shift registers, 24 adders and five SYN register;

Wherein, described 14 shift registers comprise: five are followed successively by the move right shift register of 1 of input data: the one one zero five shift register A105, the one one zero six shift register A106, the one one zero seven shift register A107, the one one zero eight shift register A108, the one one zero nine shift register A109; Three are followed successively by the move right shift register of 2 of input data: the 2105 shift register B105, the 2106 shift register B106, the 2107 shift register B107, two are followed successively by the move right shift register of 3 of input data: the 3105 shift register C105, the 3106 shift register C106, and two are followed successively by inputting the move right shift register of 4 of data: the 4103 shift register D103, the 4104 shift register D104; Two are followed successively by the move right shift register of 5 of input data: May Day 01 shift register F101, May Day 02 shift register F102;

Wherein, in described 24 adders, comprise, 17 adders that input data are added, are followed successively by: the one one two three adder E123, the one one two four adder E124, the one one two slender acanthopanax musical instruments used in a Buddhist or Taoist mass E125, the one one two six adder E126, the one one two seven adder E127, the one one sixteen adder E128, the one one two nine adder E129, the one one three zero adder E130, the one one three one adder E131, the one one three two adder E132, the one one three three adder E133, the one one three four adder E134, the one one three slender acanthopanax musical instruments used in a Buddhist or Taoist mass E135, the one one three six adder E136, the one one pseudo-ginseng adder E137, the one one three eight adder E138, the one one four six adder E146, seven have the adder that input data-conversion is added later to function, are followed successively by: the 21 three nine-day periods after the winter solstice adder E139, the 2140 adder E140, the 2141 adder E141, the 2142 adder E142, the 2143 adder E143, the 2144 adder E144, the 214 slender acanthopanax musical instruments used in a Buddhist or Taoist mass E145,

Five SYN register with clock synchronous function, are followed successively by: the first 01 SYN register H101, the first 02 SYN register H102, the first 03 SYN register H103, the first 04 SYN register H104, the first 05 SYN register H105;

Four colourity integral points are followed successively by X ₀, X ₁, X ₂, X ₃;

X ₀as data input the one one zero six shift register A106 and the one one four six adder E146, X ₁as data inputs the one one zero five shift register A105, the 2105 shift register B105, the 3105 shift register C105, the 4103 shift register D103 and May Day 01 shift register F101, X ₁also as integral point output, X ₂as data inputs the one one zero nine shift register A109, the 2107 shift register B107, the 3106 shift register C106, the 4104 shift register D104 and May Day 02 shift register F102, X ₃as data input the one one four six adder E146 and the one one zero eight shift register A108;

The output of the one one zero five shift register A105 connects the one one two three adder E123, the one one two four adder E124, the one one two slender acanthopanax musical instruments used in a Buddhist or Taoist mass E125 and the one one sixteen adder E128, the output of the 2105 shift register B105 connects the one one two four adder E124, the one one two slender acanthopanax musical instruments used in a Buddhist or Taoist mass E125, the one one two six adder E126 and the one one two seven adder E127, the output of the 3105 shift register C105 connects the one one two three adder E123, the one one two slender acanthopanax musical instruments used in a Buddhist or Taoist mass E125, the one one two seven adder E127 and the one one sixteen adder E128, the output of the 4103 shift register D103 connects the one one two three adder E123, the one one two four adder E124, the one one two seven adder E127 and the first 01 SYN register H101, May Day 01, the output of shift register F101 connected the one one two three adder E123, the one one two four adder E124, the one one two slender acanthopanax musical instruments used in a Buddhist or Taoist mass E125 and the one one two six adder E126, the output of the one one two three adder E123 connects the 21 three nine-day periods after the winter solstice adder E139, the output of the one one two four adder E124 connects the 2140 adder E140, the output of the one one two slender acanthopanax musical instruments used in a Buddhist or Taoist mass E125 connects the 2141 adder E141, the output of the one one two six adder E126 connects the 2142 adder E142, the output of the one one two seven adder E127 connects the 2143 adder E143, the output of the first 01 SYN register H101 connects the 2144 adder E144, the output of the one one sixteen adder E128 connects the 214 slender acanthopanax musical instruments used in a Buddhist or Taoist mass E145,

The output of the one one zero six shift register A106 connects the one one two nine adder E129 and the one one three zero adder E130, the output of the one one four six adder E146 connects the one one zero seven shift register A107 and the 2106 shift register B106, the output of the one one zero eight shift register A108 connects the one one three one adder E131 and the one one three two adder E132, the output of the one one zero seven shift register A107 connects the first 02 SYN register H102, the one one two nine adder E129, the one one three two adder E132 and the first 04 SYN register H104, the output of the one one zero six shift register A106 connects the one one three zero adder E130, the first 03 SYN register H103 and the one one three one adder E131, the output of the first 02 SYN register H102 connects the 21 three nine-day periods after the winter solstice adder E139, the output of the one one two nine adder E129 connects the 2140 adder E140, the output of the one one three zero adder E130 connects the 2141 adder E141, the output of the first 03 SYN register H103 connects the 2142 adder E142, the output of the one one three one adder E131 connects the 2143 adder E143, the output of the one one three two adder E132 connects the 2144 adder E144, the output of the first 04 SYN register H104 connects the 214 slender acanthopanax musical instruments used in a Buddhist or Taoist mass E145,

The output of the one one zero nine shift register A109 connects the one one three three adder E133, the one one three six adder E136, the one one pseudo-ginseng adder E137 and the one one three eight adder E138, the output of the 2107 shift register B107 connects the one one three four adder E134, the one one three slender acanthopanax musical instruments used in a Buddhist or Taoist mass E135, the one one three six adder E136 and the one one pseudo-ginseng adder E137, the output of the 3106 shift register C106 connects the one one three three adder E133, the one one three four adder E134, the one one three six adder E136 and the one one three eight adder E138, the output of the 4104 shift register D104 connects the first 05 SYN register H105, the one one three four adder E134, the one one pseudo-ginseng adder E137 and the one one three eight adder E138, May Day 02, the output of shift register F102 connected the one one three slender acanthopanax musical instruments used in a Buddhist or Taoist mass E135, the one one three six adder E136, the one one pseudo-ginseng adder E137 and the one one three eight adder E138,

The output of the one one three three adder E133 connects the 21 three nine-day periods after the winter solstice adder E139, the output of the first 05 SYN register H105 connects the 2140 adder E140, the output of the one one three four adder E134 connects the 2141 adder E141, the output of the one one three slender acanthopanax musical instruments used in a Buddhist or Taoist mass E135 connects the 2142 adder E142, the output of the one one three six adder E136 connects the 2143 adder E143, the output of the one one pseudo-ginseng adder E137 connects the 2144 adder E144, the output of the one one three eight adder E138 connects the 214 slender acanthopanax musical instruments used in a Buddhist or Taoist mass E145,

The 21 three nine-day periods after the winter solstice adder E139 is to the data-conversion from the first 02 SYN register H102 input, the 2140 adder E140 is to the data-conversion from the one one two nine adder E129 input, the 2141 adder E141 is to the data-conversion from the one one three zero adder E130 input, the 2142 adder E142 is to the data-conversion from the first 03 SYN register H103 input, the 2143 adder E143 is to the data-conversion from the one one three one adder E131 input, the 2144 adder E144 is to the data-conversion from the one one three two adder E132 input, the 214 slender acanthopanax musical instruments used in a Buddhist or Taoist mass E145 is to the data-conversion from the first 04 SYN register H104 input,

The output of the 21 three nine-day periods after the winter solstice adder E139 is exported first fractional point FLT1, second fractional point FLT2 of output output of the 2140 adder E140, the 3rd the fractional point FLT3 of output output of the 2141 adder E141, the 4th the fractional point FLT4 of output output of the 2142 adder E142, the 5th the fractional point FLT5 of output output of the 2143 adder E143, the 6th the fractional point FLT6 of output output of the 2144 adder E144, the 7th the fractional point FLT7 of output output of the 214 slender acanthopanax musical instruments used in a Buddhist or Taoist mass E145.

An interframe brightness single-point interpolating apparatus, comprising: 16 shift registers, 16 adders and 18 selection circuit;

Wherein, described 16 shift registers comprise: four are followed successively by the move right shift register of 1 of input data: the first zero shift register A110 one by one, the one one shift register A111 one by one, the one one First Five-Year Plan shift register A115, the first six shift register A116 one by one, four are followed successively by the move right shift register of 2 of input data: the 2108 shift register B108, the 2109 shift register B109, the second zero shift register B110 one by one, the second four shift register B114 one by one, four are followed successively by the move right shift register of 3 of input data: the 3107 shift register C107, the 3108 shift register C108, the 3rd zero shift register C110 one by one, the 31 shift register C111 one by one, two by the move right shift register of 4 of input data: the 4105 shift register D105, the 4107 shift register D107, two by the move right shift register of 5 of input data: May Day 03 shift register F103, May Day 05 shift register F105,

Described 16 adders comprise: 14 adders that input data are added, be followed successively by: the one one four seven adder E147, the one one four eight adder E148, the one one four nine adder E149, the 1 May Day adder E151, the first First Five-Year Plans two adder E152, the one one the May 4th adder E154, the first First Five-Year Plan slender acanthopanax musical instruments used in a Buddhist or Taoist mass E155, the first First Five-Year Plans six adder E156, the one one six four adder E164, the first parathion adder E165, the one one six six adder E166, the one one six seven adder E167, the one one six eight adder E168, the one one six nine adder E169, two have the adder that input data-conversion is added later to function, be followed successively by: the second First Five-Year Plan zero adder E150, the second First Five-Year Plans three adder E153,

Select circuit to be followed successively by for 18: first 01 selects circuit G101, first 02 selects circuit G102, first 03 selects circuit G103, first 04 selects circuit G104, first 05 selects circuit G105, first 06 selects circuit G106, first 07 selects circuit G107, first 08 selects circuit G108, first 09 selects circuit G109, the one one zero option circuit G110, first selects circuit G111 one by one, the one two one selects circuit G121, the one two two selects circuit G122, the one two three selects circuit G123, the one two four selects circuit G124, the one two five selects circuit G125, the one two six selects circuit G126, the one two seven selects circuit G127,

X ₀as data input first 01, select circuit G101, X ₁as data input first 03, select circuit G103 and the 2108 shift register B108, X ₂as data inputs the 3108 shift register C108, second zero shift register B110, the 1 shift register A111 and the one one zero option circuit G110 one by one one by one, X ₅as data input the 31 one by one shift register C111, second one by one four shift register B114, first one by one six shift register A116 and the 1 select circuit G127, X ₃as data, input shift register F103 on May Day 03, the 3107 shift register C107, the 4105 shift register D105, first zero shift register A110 and the first 06 selection circuit G106 one by one, X ₄zero shift register C110, the 4107 shift register D107, the one one First Five-Year Plan shift register A115 and the 1 select circuit G122, X one by one as data, to input shift register F105 on May Day 03, the 3rd ₆as data input first 04, select circuit G104 and the 2109 shift register B109, X ₇as input data input first 02, select circuit G102, constant 0 is also inputted respectively first 01 and is selected circuit G101, first 02 selects circuit G102, first 05 selects circuit G105, first 06 selects circuit G106, first 07 selects circuit G107, first 08 selects circuit G108, first 09 selects circuit G109, the one one zero option circuit G110 and first selects circuit G111 one by one, the one two one selects circuit G121, the one two two selects circuit G122, the one two four selects circuit G124, the one two five selects circuit G125, the one two six selects circuit G126, the one two seven selects circuit G127 and the 1 to select circuit G123,

The output of the 2108 shift register B108 connects first 03 and selects circuit G103, the output of the 2109 shift register B109 connects first 04 and selects circuit G104, first 01 selects the output of circuit G101 to connect the one one four seven adder E147, first 02 selects the output of circuit G102 to connect the one one four seven adder E147, the output of the one one four seven adder E147 connects the second First Five-Year Plan zero adder E150, first 03 selects the output of circuit G103 to connect the one one four eight adder E148, first 04 selects the output of circuit G104 to connect the one one four eight adder E148, the output of the one one four eight adder E148 connects the second First Five-Year Plan zero adder E150, the second First Five-Year Plan output of zero adder E150 connects the second First Five-Year Plans three adder E153,

May Day 03, the output of shift register F103 connected the one one four nine adder E149, the output of the 3107 shift register C107 connects the one one four nine adder E149, the output of the 4105 shift register D105 connects first 05 and selects circuit G105, first one by one the output of zero shift register A110 connect the first 06 selection circuit G106, the output of the one one four nine adder E149 connects first and selects one by one circuit G111, first 05 selects the output connection adder E151 on the one one May Day of circuit G105, first 06 selects the output connection adder E151 on the one one May Day of circuit G106, first selects the output of circuit G111 to connect the first First Five-Year Plans two adder E152 one by one, the 1 May Day adder E151 output connect the first First Five-Year Plans two adder E152, the output of the first First Five-Year Plan two adder E152 connects the second First Five-Year Plans three adder E153,

May Day 05, the output of shift register F105 connected the one one six four adder E164, the 3rd one by one the output of zero shift register C110 connect the one one six four adder E164, the output of the 4107 shift register D107 connects the 1 and selects circuit G121, the output of the one one First Five-Year Plan shift register A115 connects the 1 and selects circuit G122, the output of the one one six four adder E164 connects the 1 and selects circuit G123, the one two one selects the output of circuit G121 to connect the first parathion adder E165, the one two two selects the output of circuit G122 to connect the first parathion adder E165, the one two three selects the output of circuit G123 to connect the one one six six adder E166, the 1 May Day adder E151 output connect the one one six six adder E166, the output of the one one six six adder E166 connects the second First Five-Year Plans three adder E153,

The output of the 3108 shift register C108 connects first 07 and selects circuit G107, second one by one the output of zero shift register B110 connect the first 08 selection circuit G108, the 1 one by one the output of shift register A111 connect the first 09 selection circuit G109, first 07 selects the output of circuit G107 to connect the one one the May 4th adder E154, first 08 selects the output of circuit G108 to connect the one one the May 4th adder E154, first 09 selects the output of circuit G109 to connect the first First Five-Year Plan slender acanthopanax musical instruments used in a Buddhist or Taoist mass E155, the output of the one one zero option circuit G110 connects the first First Five-Year Plan slender acanthopanax musical instruments used in a Buddhist or Taoist mass E155, the output of the one one the May 4th adder E154 connects the first First Five-Year Plans six adder E156, the output of the first First Five-Year Plan slender acanthopanax musical instruments used in a Buddhist or Taoist mass E155 connects the first First Five-Year Plans six adder E156, the output of the first First Five-Year Plan six adder E156 connects the second First Five-Year Plans three adder E153,

The 31 one by one the output of shift register C111 connect the 1 and select circuit G124, second one by one the output of four shift register B114 connect the 1 and select circuit G125, first one by one the output of six shift register A116 connect the 1 and select circuit G126, the one two four selects the output of circuit G124 to connect the one one six seven adder E167, the one two five selects the output of circuit G125 to connect the one one six seven adder E167, the one two six selects the output of circuit G126 to connect the one one six eight adder E168, the output of the one one zero option circuit G110 connects the one one six eight adder E168, the output of the one one six seven adder E167 connects the one one six nine adder E169, the output of the one one six eight adder E168 connects the one one six nine adder E169, the output of the one one six nine adder E169 connects the second First Five-Year Plans three adder E153,

The second First Five-Year Plan zero adder E150 to the data-conversion from the one one four seven adder E147 input, the second First Five-Year Plans three adder E153 to the data-conversion from the first First Five-Year Plans six adder E156 input;

The output data of the second First Five-Year Plans three adder E153 are as brightness fraction pixel point.

An interframe colourity single-point interpolating apparatus, comprising: 14 shift registers, ten adders and 14 selection circuit;

Wherein, described 14 shift registers comprise: four are followed successively by the move right shift register of 1 of input data: the first two shift register A112 one by one, the first three shift register A113 one by one, the first four shift register A114 one by one, the first seven shift register A117 one by one, four are followed successively by the move right shift register of 2 of input data: the 21 shift register B111 one by one, the second two shift register B112 one by one, the second three shift register B113 one by one, the 21 First Five-Year Plan shift register B115, two by the move right shift register of 3 of input data: the 3109 shift register C109, the 3rd two shift register C112 one by one, two by the move right shift register of 4 of input data: the 4106 shift register D106, the 4108 shift register D108, two by the move right shift register of 5 of input data: May Day 04 shift register F104, May Day 06 shift register F106,

Described ten adders comprise: six adders that input data are added, be followed successively by: the first First Five-Year Plans seven adder E157, the first First Five-Year Plans eight adder E158, the first First Five-Year Plans nine adder E159, the one one six zero adder E160, the one one six one adder E161, the one one six two adder E162, one has the adder that input data-conversion is added later to function: the 2163 adder E163, the one one seven zero adder E170, the first 171 adder E171, the one one seven two adder E172;

Select circuit to be followed successively by for 14: the one one two selects circuit G112, the one one three selects circuit G113, the one one four selects circuit G114, the first First Five-Year Plan was selected circuit G115, the one one six selects circuit G116, the one one seven selects circuit G117, the one one eight selects circuit G118, the one one nine selects circuit G119, the one or two zero option circuit G120, the one sixteen selects circuit G128, the one two nine selects circuit G129, the one or three zero option circuit G130, the one three one selects circuit G131, the one three two selects circuit G132,

Four colourity integral points are followed successively by: X ₀, X ₁, X ₂, X ₃;

X ₀as data input first three shift register A113 and second, two shift register B112 one by one one by one, X ₁as data, input shift register F104 on May Day 04, the 4106 shift register D106, the 3109 shift register C109, the 21 shift register B111 and first two shift register A112 one by one one by one, X ₂as data, input shift register F106 on May Day 06, the 4108 shift register D108, the 3rd two shift register C112, the 21 First Five-Year Plan shift register B115 and first seven shift register A117 one by one one by one, X ₃as data input first four shift register A114 and second, three shift register B113 one by one one by one, constant 0 is also inputted respectively the 1 and is selected circuit G112, the one one three selects circuit G113, the one one four selects circuit G114, the first First Five-Year Plan was selected circuit G115, the one one six selects circuit G116, the one one four selects circuit G114, the one one eight selects circuit G118, the one one nine selects circuit G119, , the one sixteen selects circuit G128, the one two nine selects circuit G129, the one or three zero option circuit G130, the one three one selects circuit G131, the one three two selects circuit G132 and the one or two zero option circuit G120,

May Day 04, the output of shift register F104 connected the one one two selection circuit G112, the output of the 4106 shift register D106 connects the 1 and selects circuit G113, the output of the 3109 shift register C109 connects the 1 and selects circuit G114, the 21 one by one the output of shift register B111 connected for the first First Five-Year Plan and select circuit G115, first one by one the output of two shift register A112 connect the 1 and select circuit G116, the one one two selects the output of circuit G112 to connect the first First Five-Year Plans seven adder E157, the one one three selects the output of circuit G113 to connect the first First Five-Year Plans seven adder E157, the one one four selects the output of circuit G114 to connect the one one six one adder E161, the first First Five-Year Plan selected the output of circuit G115 to connect the first First Five-Year Plans eight adder E158, the one one six selects the output of circuit G116 to connect the first First Five-Year Plans eight adder E158, the output of the first First Five-Year Plans seven adder E157 connects the one one six one adder E161, the output of the first First Five-Year Plans eight adder E158 connects the one one six one adder E161,

May Day 06, the output of shift register F106 connected the one sixteen selection circuit G128, the output of the 4108 shift register D108 connects the 1 and selects circuit G129, the 3rd one by one the output of two shift register C112 connect the one or three zero option circuit G130, the output of the 21 First Five-Year Plan shift register B115 connects the 1 and selects circuit G131, first one by one the output of seven shift register A117 connect the 1 and select circuit G132, the one sixteen selects the output of circuit G128 to connect the one one seven zero adder E170, the one two nine selects the output of circuit G129 to connect the one one seven zero adder E170, the output of the one or three zero option circuit G130 connects the one one seven two adder E172, the one three one selects the output of circuit G131 to connect the first 171 adder E171, the one three two selects the output of circuit G132 to connect the first 171 adder E171, the output of the first 171 adder E171 connects the one one seven two adder E172, the output of the first 171 adder E171 connects the one one seven two adder E172,

First one by one the output of three shift register A113 connect the 1 and select circuit G117, second one by one the output of two shift register B112 connect the 1 and select circuit G118, the one one seven selects the output of circuit G117 to connect the first First Five-Year Plans nine adder E159, and the one one eight selects the output of circuit G118 to connect the first First Five-Year Plans nine adder E159; First one by one the output of four shift register A114 connect the 1 and select circuit G119, second one by one the output of three shift register B113 connect the one or two zero option circuit G120, the one one nine selects the output of circuit G119 to connect the one one six zero adder E160, and the output of the one or two zero option circuit G120 connects the one one six zero adder E160; The output of the first First Five-Year Plans nine adder E159 connects the one one six two adder E162, and the output of the one one six zero adder E160 connects the one one six two adder E162;

The output of the output of the one one six one adder E161 and the one one seven two adder E172 connects the 2163 adder E163, the output of the one one six two adder E162 connects the 2163 adder E163, the 2163 adder E163 is to the data-conversion from the one one six two adder E162 input, and the output data of the 2163 adder E163 are as colourity fraction pixel point.

As can be seen from the above technical solutions, the embodiment of the present invention has the following advantages: by use, be shifted and added replacement multiply operation, and multiplexing logical resource, compare the brightness interpolating scheme in background technology, (in background technology, Horizontal interpolation needs are 6 not need to consume multiplier unit, vertical interpolation needs 18), and register has reduced by 25%, combinational logic has reduced by 10% resource consumption.If FME carries out the mark search of 5x5, need to call 10 sub-level interpolation and 17 vertical interpolating unit, background technology need to consume 10488 register resources, 9156 combination logic resource, embodiment of the present invention scheme consumes 7866 register resources, 8240 combination logic resource.Greatly reduced the consumption of logical resource.

Accompanying drawing explanation

In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing of required use during embodiment is described is briefly introduced, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.

Fig. 1 is three fractional point schematic diagrames of the embodiment of the present invention;

Fig. 2 is seven fractional point schematic diagrames of the embodiment of the present invention;

Fig. 3 is embodiment of the present invention logic circuit structure schematic diagram;

Fig. 4 is embodiment of the present invention logic circuit structure schematic diagram;

Fig. 5 is embodiment of the present invention logic circuit structure schematic diagram;

Fig. 6 is embodiment of the present invention logic circuit structure schematic diagram;

Fig. 7 is embodiment of the present invention logic circuit structure schematic diagram;

Fig. 8 is embodiment of the present invention logic circuit structure schematic diagram;

Fig. 9 is embodiment of the present invention logic circuit structure schematic diagram;

Figure 10 is embodiment of the present invention logic circuit structure schematic diagram;

Figure 11 is embodiment of the present invention logic circuit structure schematic diagram;

Figure 12 A is embodiment of the present invention logic circuit structure schematic diagram;

Figure 12 B is embodiment of the present invention logic circuit structure schematic diagram;

Figure 13 A is embodiment of the present invention logic circuit structure schematic diagram;

Figure 13 B is embodiment of the present invention logic circuit structure schematic diagram;

Figure 14 is embodiment of the present invention logic circuit structure schematic diagram;

Figure 15 A is embodiment of the present invention logic circuit structure schematic diagram;

Figure 15 B is embodiment of the present invention logic circuit structure schematic diagram;

Figure 16 A is embodiment of the present invention logic circuit structure schematic diagram;

Figure 16 B is embodiment of the present invention logic circuit structure schematic diagram;

Figure 17 is embodiment of the present invention logic circuit structure schematic diagram.

Embodiment

In order to make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, the present invention is described in further detail, and obviously, described embodiment is only a part of embodiment of the present invention, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making all other embodiment that obtain under creative work prerequisite, belong to the scope of protection of the invention.

For luminance pixel, always have 3 kind of 8 tap filter, as shown in table 1 below:

The filter tap coefficients that table 1 luminance pixel is relevant

FLT1	-1	4	-10	58	17	-5	1	0
									FLT2	-1	4	-11	40	40	-11	4	-1
FLT3	0	1	-5	17	58	-10	4	-1

FLT1～FLT3 is respectively 1/4,2/4 and 3/4 3 fractional point, as shown in Figure 1, and 1/4 corresponding FLT1, so-3～4 coefficients that corresponding FLT1 is expert at successively; 2/4 corresponding FLT2, so-3～4 coefficients that corresponding FLT2 is expert at successively; 3/4 corresponding FLT3, so-3～4 coefficients that corresponding FLT3 is expert at successively.

For chroma pixel, always have 7 kind of 4 tap filter, as shown in table 2 below:

The filter tap coefficients that table 2 chroma pixel is relevant

FLT1	-2	58	10	-2
					FLT2	-4	54	16	-2
FLT3	-6	46	28	-4
					FLT4	-4	36	36	-4
FLT5	-4	28	46	-6
					FLT6	-2	16	54	-4
FLT7	-2	10	58	-2

In FLT1～FLT7 shown in Fig. 2, during value FLT1～FLT7 ,-1～2 coefficients that corresponding above FLT1～FLT7 is expert at respectively.

Following examples are the embodiment of interframe multiple spot interpolation, comprise two parts, are respectively brightness part and the chrominance section of interframe multiple spot interpolation, specific as follows:

One, the brightness part of interframe multiple spot interpolation.

First, extract interframe brightness interpolating filter factor general character, specific as follows:

1st, two coefficients identical (in table 3, circle marker location in FLT1 and FLT7) of the 2nd liang of group filter, latter two coefficient identical (in table 3, FLT2 and FLT3 circle marker location) of the 2nd, the 3rd liang of group filter; Refer to shown in table 3:

Table 3

Obtain circuit as shown in Figure 3.Fig. 3 is a part of Fig. 6, refers to illustrating of Fig. 6.X ₂and x ₅corresponding coefficient 5,10,11 has public part, as follows:

10x ₂+5x ₅=(2x ₂+x ₅)*4+(2x ₂+x ₅)；

10x ₅+5x ₂=(2x ₅+x ₂)*4+(2x ₅+x ₂)；

The public part of above three formulas:

\begin{matrix} ({2 x}_{2} + x_{5}) \\ ({2 x}_{5} + x_{2}) \end{matrix},

Obtain circuit as shown in Figure 4.Fig. 4 is a part of Fig. 6, refers to illustrating of Fig. 6.

X ₃and x ₄corresponding coefficient 58,40,17 has public part:

58x ₃+17x ₄=(x ₃+2x ₃)*8+(2x ₃+x ₄)+(2x ₃+x ₄)*16；

40x ₃+40x ₄=(2x ₃+x ₄)*16+(2x ₄+x ₃)*16-(x ₃+x ₃)*8；

17x ₃+58x ₄=(x ₄+2x ₄)*8+(2x ₄+x ₃)+(2x ₄+x ₃)*16；

The public part of above three formulas is:

\begin{matrix} ({2 x}_{3} + x_{4}) \\ ({2 x}_{4} + x_{3}) \end{matrix},

Obtain logical circuit as shown in Figure 5.Fig. 5 is a part of Fig. 6, refers to illustrating of Fig. 6.

The embodiment of the present invention provides a kind of HEVC interframe interpolation device, and for the brightness part of multiple spot interpolation between achieve frame, comprehensive above Fig. 3～5 obtain the circuit diagram of integral point and three fractional point, as shown in Figure 6.Comprise: 14 shift registers and 22 adders;

A～t shown in Fig. 6 is the median of each logical device output.

Two, the chrominance section of interframe multiple spot interpolation.

Secondly, extract interframe chroma interpolation filter factor general character:

The the 1st, the 4th coefficient of 7 groups of filters is all 2,4, the 6 wherein combinations of 2 data, can obtain circuit as shown in Figure 8, and circuit shown in Fig. 8 is a part for circuit shown in Figure 10, refers to illustrating of Figure 10.

The the 2nd, the 3rd coefficient of 7 groups of filters has public part:

58x=2x +8x+16x+32x；

54x=2x+4x +16x+32x；

46x=2x+4x+8x +32x；

36x= 4x +32x；

28x= 4x+8x+16x；

16x= 16x；

10x=2x +8x；

Public part refers to as above four row of 7 formulas.Can obtain circuit as shown in Figure 7 and Figure 8, shown in Fig. 7 and Fig. 8, circuit is a part for circuit shown in Figure 10, refers to illustrating of Figure 10.

The embodiment of the present invention provides a kind of HEVC interframe interpolation device, and for the chrominance section of multiple spot interpolation between achieve frame, comprehensive above Fig. 7～9 obtain the circuit diagram of integral point and seven fractional point, as shown in Figure 6.Comprise: 14 shift registers, 24 adders and five SYN register;

Above embodiment scheme, by use, be shifted and add replacement multiply operation, and multiplexing logical resource, compare the brightness interpolating scheme in background technology, (in background technology, Horizontal interpolation needs are 6 not need to consume multiplier unit, vertical interpolation needs 18), and register has reduced by 25%, combinational logic has reduced by 10% resource consumption.If FME carries out the mark search of 5x5, need to call 10 sub-level interpolation and 17 vertical interpolating unit, background technology need to consume 10488 register resources, 9156 combination logic resource, embodiment of the present invention scheme consumes 7866 register resources, 8240 combination logic resource.Greatly reduced the consumption of logic.

Following examples are the embodiment of interframe single-point interpolation, comprise two parts, are respectively brightness part and the chrominance section of interframe multiple spot interpolation, specific as follows:

One, the brightness part of interframe single-point interpolation.

First, extract interframe brightness interpolating filter factor general character:

The coefficient that x0, x1, x6 and x7 are corresponding has moiety (in table 4 ,-1 and 4), as shown in table 4 below:

Table 4

Can obtain structure shown in Figure 11, Figure 11 is a part of Figure 14, refers to the detailed description of Figure 14.

Wherein mux is depicted as the selection circuit of multiselect one, except the importation shown in Figure 14, each mux also has a LPFSel as input value, and LPFSel represents 2/4ths pixels of selecting 1/4th pixels of FLT1, still selecting FLT2 or 3/4ths pixels of selecting FLT3; Corresponding to limit selecting which in table 1 or table 4, take first 01, to select circuit G101 be example: 1/4 selects coefficient and the X0～X7 of this line of FLT1 to take advantage of, and then the cumulative value of obtaining conduct is exported.

The coefficient 5,10,11 that x2 and x5 are corresponding has public part (in table 5, each row), as shown in table 5 below:

Table 5

5x	1x		4x
					10x	2x	8x
11x	1x	2x		8x

Can obtain structure shown in Figure 12 A and Figure 12 B, Figure 12 A and Figure 12 B are all parts of Figure 14, refer to the detailed description of Figure 14.

Figure 12 A is two independent circuits that structure is identical with Figure 12 B, and just the data of input are different, in Figure 14 in order only to have illustrated for simplicity the structure of Figure 12 A wherein.

The coefficient 58,40,17 that x3 and x4 are corresponding has public part (in table 6, each row), as shown in table 6 below:

Table 6

58x

2x

8x

16x

32x

40x

8x

32x

17x

1x

16x

Can obtain structure shown in Figure 13 A and Figure 13 B, Figure 13 A and Figure 13 B are all parts of Figure 14, refer to the detailed description of Figure 14.

Figure 13 A is two independent circuits that structure is identical with Figure 13 B, and just the data of input are different, in Figure 14 in order only to have illustrated for simplicity the structure of Figure 13 A wherein.

The embodiment of the present invention provides a kind of HEVC interframe interpolation device, and for the brightness part of single-point interpolation between achieve frame, comprehensive above Figure 11～13 obtain the circuit diagram of fraction pixel point, as shown in figure 14.Comprise: 16 shift registers, 16 adders and 18 selection circuit;

Two, the chrominance section of interframe single-point interpolation.

Secondly, extract interframe chroma interpolation filter factor general character.

The coefficient that x0 and x3 are corresponding has public part (each row in table 7), as shown in table 7 below:

Table 7

2x	2x
			4x	4x
6x	2x	4x

Can obtain structure shown in Figure 15 A and Figure 15 B, Figure 15 A and Figure 15 B are parts of Figure 17, refer to the detailed description of Figure 17.

The coefficient that x1 and x2 are corresponding has public part (each row in table 8), as shown in table 8 below:

Table 8

58x

2x

8x

16x

32x

54x

2x

4x

16x

32x

46x

2x

4x

8x

32x

36x

4x

32x

28x

4x

8x

16x

10x

2x

8x

Can obtain structure shown in Figure 16 A and Figure 16 B, Figure 16 A and Figure 16 B are all parts of Figure 17, refer to saying of Figure 17 and describe in detail bright.

Figure 16 A is two independent circuits that structure is identical with Figure 16 B, and just the data of input are different, in Figure 17 in order only to have illustrated for simplicity the structure of Figure 16 A wherein.

The embodiment of the present invention provides a kind of HEVC interframe interpolation device, and for the chrominance section of single-point interpolation between achieve frame, comprehensive above Figure 15 A～16 obtain the circuit diagram of fraction pixel point, as shown in figure 17.Comprise: 14 shift registers, ten adders and 14 selection circuit;

In above embodiment scheme, with displacement, add and replaced multiply operation, and well multiplexing logical resource; Only need to calculate the fractional point that mark MV is corresponding, reduce the complexity that algorithm is realized, than the interpolation of background technology, obtain the structure of all fractional point, brightness interpolating aspect, register has reduced by 50%, combinational logic has reduced by 40% resource consumption; And well met the requirement that a fractional point is only exported in Merge prediction.Luminance level/vertical interpolation and 12 colourity horizontal/vertical interpolating unit need to be respectively called in Merge prediction 24 times, background technology scheme need to consume 36179 register resources, 37739 combination logic resource, embodiment of the present invention scheme consumes 15195 register resources, 20379 combination logic resource.

These are only preferably embodiment of the present invention; but protection scope of the present invention is not limited to this; anyly be familiar with those skilled in the art in the technical scope that the embodiment of the present invention discloses, the variation that can expect easily or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.

Claims

1. a HEVC interframe brightness multiple spot interpolating apparatus, is characterized in that, comprising: 14 shift registers and 22 adders;

Wherein, in described 14 shift registers, comprise: four are followed successively by the move right shift register of 1 of input data: the one one zero one shift register (A101), the one one zero two shift register (A102), the one one zero three shift register (A103), the one one zero four shift register (A104), four are followed successively by the move right shift register of 2 of input data: the 2101 shift register (B101), the 2102 shift register (B102), the 2103 shift register (B103), the 2104 shift register (B104), four are followed successively by the move right shift register of 3 of input data: the 3101 shift register (C101), the 3102 shift register (C102), the 3103 shift register (C103), the 3104 shift register (C104), two are followed successively by the move right shift register of 4 of input data: the 4101 shift register (D101), the 4102 shift register (D102),

Wherein, in described 22 adders, comprise, 16 adders that input data are added, are followed successively by: the one one zero three adder (E103), the one one zero four adder (E104), the one one zero slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E105), the one one zero six adder (E106), the one one zero seven adder (E107), the one one zero eight adder (E108), the one one zero nine adder (E109), the first zero adder (E110) one by one, the one one adder (E111) one by one, the first two adders (E112) one by one, the first three adders (E113) one by one, the first slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E115) one by one, the first six adders (E116) one by one, the first seven adders (E117) one by one, the first nine adders (E119) one by one, the one one two two adder (E122), six have the adder that input data-conversion is added later to function, are followed successively by: the 2101 adder (E101), the 2102 adder (E102), the second four adders (E114) one by one, the second eight adders (E118) one by one, the 2120 adder (E120), the 2121 adder (E121),

X ₀as data input the 2101 adder (E101), X ₁as data, input the 2101 shift register (B101) and first zero adder (E110) one by one, X ₂as data input the one one zero one shift register (A101), the one one zero three adder (E103) and the one one zero four adder (E104), X ₃as data input the one one zero three shift register (A103), the one one zero slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E105), the one one zero seven adder (E107) and the one one zero eight adder (E108), X ₃also as integral point output, X ₄as data input the one one zero six adder (E106), the one one zero seven adder (E107), the one one zero four shift register (A104) and the one one zero nine adder (E109), X ₅as data input the one one two two adder (E122), the one one zero three adder (E103) and the one one zero two shift register (A102), X ₆as data, input the 2102 shift register (B102) and the 1 adder (E111) one by one, X ₇as input data input the 2102 adder (E102);

The output of the 2101 shift register (B101) connects the input of the 2101 adder (E101), and the output connection the 1 of the 2101 adder (E101) is adder (E111) and first two adders (E112) one by one one by one; The output of the 2102 shift register (B102) connects the 2102 adder (E102), the output of the 2102 adder (E102) connects the first zero adder (E110) and first, two adders (E112) one by one one by one, first one by one the output of zero adder (E110) connect the 2121 adder (E121), first one by one the output of two adders (E112) connect the 2120 adder (E120);

The output of the one one zero one shift register (A101) connects the one one two two adder (E122), the output of the one one two two adder (E122) connects the 2103 shift register (B103), first three adders (E113) and first slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E115) one by one one by one, the output of the 2103 shift register (B103) connects the first three adders (E113) one by one, first one by one the output of three adders (E113) connect the second four adders (E114) one by one; The output of the one one zero two shift register (A102) connects the one one zero four adder (E104), and output connection the 2104 shift register (B104), first of the one one zero four adder (E104) is slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E115) and first six adders (E116) one by one one by one; The output connection first of the 2104 shift register (B104) is six adders (E116) one by one, the output of the one one zero three adder (E103) connects the 3101 shift register (C101), and the output connection first of the 3101 shift register (C101) is slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E115) one by one; First one by one the output of slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E115) connect the 2120 adder (E120), first output connection the 2121 adder (E121) of six adders (E116) one by one;

The output of the one one zero three shift register (A103) connects the one one zero six adder (E106) and the one one zero slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E105), the output of the one one zero slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E105) connects the 3102 shift register (C102), and the output connection first of the 3102 shift register (C102) is seven adders (E117) one by one; The output of the one one zero six adder (E106) connects the 4101 shift register (D101) and first seven adders (E117) one by one, and the output connection first of the 4101 shift register (D101) is seven adders (E117) and second, eight adders (E118) one by one one by one; The output of the one one zero seven adder (E107) connects the 3103 shift register (C103), and the output connection second of the 3103 shift register (C103) is eight adders (E118) one by one; The output of the one one zero four shift register (A104) connects the one one zero eight adder (E108) and the one one zero nine adder (E109), the output of the one one zero nine adder (E109) connects the 3104 shift register (C104), and the output connection first of the 3104 shift register (C104) is nine adders (E119) one by one; The output of the one one zero eight adder (E108) connects the 4102 shift register (D102) and first nine adders (E119) one by one, and the output connection second of the 4102 shift register (D102) is eight adders (E118) and first, nine adders (E119) one by one one by one; The 1 one by one the output of adder (E111) connect the second four adders (E114) one by one, first one by one the output of seven adders (E117) connect the second four adders (E114) one by one, second one by one the output of eight adders (E118) connect the 2120 adder (E120), first output connection the 2121 adder (E121) of nine adders (E119) one by one;

Wherein, the X of the 2101 adder (E101) to input ₀negate, the X of the 2102 adder (E102) to input ₇negate, second one by one four adders (E114) to from first one by one three adders (E113) inputs data-conversion, second one by one eight adders (E118) to the data-conversion from the 3103 shift register (C103) input, the 2120 adder (E120) to from the first data-conversion that slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E115) is inputted one by one, the 2121 adder (E121) to from the first data-conversion that six adders (E116) are inputted one by one;

Second one by one four adders (E114) export first fractional point FLT1, the 2120 adder (E120) is exported second fractional point FLT2, the 2121 adder (E121) is exported the 3rd fractional point FLT3.

2. a HEVC interframe colourity multiple spot interpolating apparatus, is characterized in that, comprising: 14 shift registers, 24 adders and five SYN register;

Wherein, described 14 shift registers comprise: five are followed successively by the move right shift register of 1 of input data: the one one zero five shift register (A105), the one one zero six shift register (A106), the one one zero seven shift register (A107), the one one zero eight shift register (A108), the one one zero nine shift register (A109); Three are followed successively by the move right shift register of 2 of input data: the 2105 shift register (B105), the 2106 shift register (B106), the 2107 shift register (B107), two are followed successively by the move right shift register of 3 of input data: the 3105 shift register (C105), the 3106 shift register (C106), and two are followed successively by inputting the move right shift register of 4 of data: the 4103 shift register (D103), the 4104 shift register (D104); Two are followed successively by the move right shift register of 5 of input data: shift registers on May Day 01 (F101), shift registers on May Day 02 (F102);

Wherein, in described 24 adders, comprise, 17 adders that input data are added, are followed successively by: the one one two three adder (E123), the one one two four adder (E124), the one one two slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E125), the one one two six adder (E126), the one one two seven adder (E127), the one one sixteen adder (E128), the one one two nine adder (E129), the one one three zero adder (E130), the one one three one adder (E131), the one one three two adder (E132), the one one three three adder (E133), the one one three four adder (E134), the one one three slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E135), the one one three six adder (E136), the one one pseudo-ginseng adder (E137), the one one three eight adder (E138), the one one four six adder (E146), seven have the adder that input data-conversion is added later to function, are followed successively by: the 21 three nine-day periods after the winter solstice adder (E139), the 2140 adder (E140), the 2141 adder (E141), the 2142 adder (E142), the 2143 adder (E143), the 2144 adder (E144), the 214 slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E145),

Five SYN register with clock synchronous function, are followed successively by: the first 01 SYN register (H101), the first 02 SYN register (H102), the first 03 SYN register (H103), the first 04 SYN register (H104), the first 05 SYN register (H105);

X ₀as data input the one one zero six shift register (A106) and the one one four six adder (E146), X ₁as data input the one one zero five shift register (A105), the 2105 shift register (B105), the 3105 shift register (C105), the 4103 shift register (D103) and shift registers on May Day 01 (F101), X ₁also as integral point output, X ₂as data input the one one zero nine shift register (A109), the 2107 shift register (B107), the 3106 shift register (C106), the 4104 shift register (D104) and shift registers on May Day 02 (F102), X ₃as data input the one one four six adder (E146) and the one one zero eight shift register (A108);

The output of the one one zero five shift register (A105) connects the one one two three adder (E123), the one one two four adder (E124), the one one two slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E125) and the one one sixteen adder (E128), the output of the 2105 shift register (B105) connects the one one two four adder (E124), the one one two slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E125), the one one two six adder (E126) and the one one two seven adder (E127), the output of the 3105 shift register (C105) connects the one one two three adder (E123), the one one two slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E125), the one one two seven adder (E127) and the one one sixteen adder (E128), the output of the 4103 shift register (D103) connects the one one two three adder (E123), the one one two four adder (E124), the one one two seven adder (E127) and the first 01 SYN register (H101), the output of shift registers on May Day 01 (F101) connects the one one two three adder (E123), the one one two four adder (E124), the one one two slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E125) and the one one two six adder (E126), the output of the one one two three adder (E123) connects the 21 three nine-day periods after the winter solstice adder (E139), the output of the one one two four adder (E124) connects the 2140 adder (E140), the output of the one one two slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E125) connects the 2141 adder (E141), the output of the one one two six adder (E126) connects the 2142 adder (E142), the output of the one one two seven adder (E127) connects the 2143 adder (E143), the output of the first 01 SYN register (H101) connects the 2144 adder (E144), the output of the one one sixteen adder (E128) connects the 214 slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E145),

The output of the one one zero six shift register (A106) connects the one one two nine adder (E129) and the one one three zero adder (E130), the output of the one one four six adder (E146) connects the one one zero seven shift register (A107) and the 2106 shift register (B106), the output of the one one zero eight shift register (A108) connects the one one three one adder (E131) and the one one three two adder (E132), the output of the one one zero seven shift register (A107) connects the first 02 SYN register (H102), the one one two nine adder (E129), the one one three two adder (E132) and the first 04 SYN register (H104), the output of the one one zero six shift register (A106) connects the one one three zero adder (E130), the first 03 SYN register (H103) and the one one three one adder (E131), the output of the first 02 SYN register (H102) connects the 21 three nine-day periods after the winter solstice adder (E139), the output of the one one two nine adder (E129) connects the 2140 adder (E140), the output of the one one three zero adder (E130) connects the 2141 adder (E141), the output of the first 03 SYN register (H103) connects the 2142 adder (E142), the output of the one one three one adder (E131) connects the 2143 adder (E143), the output of the one one three two adder (E132) connects the 2144 adder (E144), the output of the first 04 SYN register (H104) connects the 214 slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E145),

The output of the one one zero nine shift register (A109) connects the one one three three adder (E133), the one one three six adder (E136), the one one pseudo-ginseng adder (E137) and the one one three eight adder (E138), the output of the 2107 shift register (B107) connects the one one three four adder (E134), the one one three slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E135), the one one three six adder (E136) and the one one pseudo-ginseng adder (E137), the output of the 3106 shift register (C106) connects the one one three three adder (E133), the one one three four adder (E134), the one one three six adder (E136) and the one one three eight adder (E138), the output of the 4104 shift register (D104) connects the first 05 SYN register (H105), the one one three four adder (E134), the one one pseudo-ginseng adder (E137) and the one one three eight adder (E138), the output of shift registers on May Day 02 (F102) connects the one one three slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E135), the one one three six adder (E136), the one one pseudo-ginseng adder (E137) and the one one three eight adder (E138),

The output of the one one three three adder (E133) connects the 21 three nine-day periods after the winter solstice adder (E139), the output of the first 05 SYN register (H105) connects the 2140 adder (E140), the output of the one one three four adder (E134) connects the 2141 adder (E141), the output of the one one three slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E135) connects the 2142 adder (E142), the output of the one one three six adder (E136) connects the 2143 adder (E143), the output of the one one pseudo-ginseng adder (E137) connects the 2144 adder (E144), the output of the one one three eight adder (E138) connects the 214 slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E145),

The 21 three nine-day periods after the winter solstice adder (E139) is to the data-conversion from the first 02 SYN register (H102) input, the 2140 adder (E140) is to the data-conversion from the one one two nine adder (E129) input, the 2141 adder (E141) is to the data-conversion from the one one three zero adder (E130) input, the 2142 adder (E142) is to the data-conversion from the first 03 SYN register (H103) input, the 2143 adder (E143) is to the data-conversion from the one one three one adder (E131) input, the 2144 adder (E144) is to the data-conversion from the one one three two adder (E132) input, the 214 slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E145) is to the data-conversion from the first 04 SYN register (H104) input,

The output of the 21 three nine-day periods after the winter solstice adder (E139) is exported first fractional point FLT1, second fractional point FLT2 of output output of the 2140 adder (E140), the 3rd the fractional point FLT3 of output output of the 2141 adder (E141), the 4th the fractional point FLT4 of output output of the 2142 adder (E142), the 5th the fractional point FLT5 of output output of the 2143 adder (E143), the 6th the fractional point FLT6 of output output of the 2144 adder (E144), the 7th the fractional point FLT7 of output output of the 214 slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E145).

3. a HEVC interframe brightness single-point interpolating apparatus, is characterized in that, comprising: 16 shift registers, 16 adders and 18 selection circuit;

Wherein, described 16 shift registers comprise: four are followed successively by the move right shift register of 1 of input data: the first zero shift register (A110) one by one, the one one shift register (A111) one by one, the one one First Five-Year Plan shift register (A115), the first six shift registers (A116) one by one, four are followed successively by the move right shift register of 2 of input data: the 2108 shift register (B108), the 2109 shift register (B109), the second zero shift register (B110) one by one, the second four shift registers (B114) one by one, four are followed successively by the move right shift register of 3 of input data: the 3107 shift register (C107), the 3108 shift register (C108), the 3rd zero shift register (C110) one by one, the 31 shift register (C111) one by one, two by the move right shift register of 4 of input data: the 4105 shift register (D105), the 4107 shift register (D107), two by the move right shift register of 5 of input data: shift registers on May Day 03 (F103), shift registers on May Day 05 (F105),

Described 16 adders comprise: 14 adders that input data are added, be followed successively by: the one one four seven adder (E147), the one one four eight adder (E148), the one one four nine adder (E149), the one one adder on May Day (E151), the first First Five-Year Plans two adders (E152), the one one the May 4th adder (E154), the first First Five-Year Plan slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E155), the first First Five-Year Plans six adders (E156), the one one six four adder (E164), the first parathion adder (E165), the one one six six adder (E166), the one one six seven adder (E167), the one one six eight adder (E168), the one one six nine adder (E169), two have the adder that input data-conversion is added later to function, be followed successively by: the second First Five-Year Plan zero adder (E150), the second First Five-Year Plans three adders (E153),

Select circuit to be followed successively by for 18: first 01 selects circuit (G101), first 02 selects circuit (G102), first 03 selects circuit (G103), first 04 selects circuit (G104), first 05 selects circuit (G105), first 06 selects circuit (G106), first 07 selects circuit (G107), first 08 selects circuit (G108), first 09 selects circuit (G109), the one one zero option circuit (G110), first selects circuit (G111) one by one, the one two one selects circuit G(121), the one two two selects circuit (G122), the one two three selects circuit (G123), the one two four selects circuit (G124), the one two five selects circuit (G125), the one two six selects circuit (G126), the one two seven selects circuit (G127),

X ₀as data input first 01, select circuit (G101), X ₁as data input first 03, select circuit (G103) and the 2108 shift register (B108), X ₂as data inputs the 3108 shift register (C108), second zero shift register (B110), the 1 shift register (A111) and the one one zero option circuit (G110) one by one one by one, X ₅as data input the 31 shift register (C111), second four shift registers (B114), first six shift registers (A116) and the one two seven selection circuit (G127) one by one one by one one by one, X ₃as data, input shift register on May Day 03 (F103), the 3107 shift register (C107), the 4105 shift register (D105), first zero shift register (A110) and the first 06 selection circuit (G106) one by one, X ₄zero shift register (C110), the 4107 shift register (D107), the one one First Five-Year Plan shift register (A115) and the 1 are selected circuit (G122), X one by one as data, to input shift register on May Day 03 (F105), the 3rd ₆as data input first 04, select circuit (G104) and the 2109 shift register (B109), X ₇as input data input first 02, select circuit (G102), constant 0 is also inputted respectively first 01 and is selected circuit (G101), first 02 selects circuit (G102), first 05 selects circuit (G105), first 06 selects circuit (G106), first 07 selects circuit (G107), first 08 selects circuit (G108), first 09 selects circuit (G109), the one one zero option circuit (G110) and first is selected circuit (G111) one by one, the one two one selects circuit (G121), the one two two selects circuit (G122), the one two four selects circuit (G124), the one two five selects circuit (G125), the one two six selects circuit (G126), the one two seven selects circuit (G127) and the 1 to select circuit (G123),

The output of the 2108 shift register (B108) connects first 03 and selects circuit (G103), the output of the 2109 shift register (B109) connects first 04 and selects circuit (G104), first 01 selects the output of circuit (G101) to connect the one one four seven adder (E147), first 02 selects the output of circuit (G102) to connect the one one four seven adder (E147), the output of the one one four seven adder (E147) connects the second First Five-Year Plan zero adder (E150), first 03 selects the output of circuit (G103) to connect the one one four eight adder (E148), first 04 selects the output of circuit (G104) to connect the one one four eight adder (E148), the output of the one one four eight adder (E148) connects the second First Five-Year Plan zero adder (E150), the second First Five-Year Plan output of zero adder (E150) connects the second First Five-Year Plans three adders (E153),

The output of shift registers on May Day 05 (F105) connects the one one six four adder (E164), the 3rd one by one the output of zero shift register (C110) connect the one one six four adder (E164), the output of the 4107 shift register (D107) connects the 1 and selects circuit (G121), the output of the one one First Five-Year Plan shift register (A115) connects the 1 and selects circuit (G122), the output of the one one six four adder (E164) connects the 1 and selects circuit (G123), the one two one selects the output of circuit (G121) to connect the first parathion adder (E165), the one two two selects the output of circuit (G122) to connect the first parathion adder (E165), the one two three selects the output of circuit (G123) to connect the one one six six adder (E166), the output of the one one adder on May Day (E151) connects the one one six six adder (E166), the output of the one one six six adder (E166) connects the second First Five-Year Plans three adders (E153),

The output of shift registers on May Day 03 (F103) connects the one one four nine adder (E149), the output of the 3107 shift register (C107) connects the one one four nine adder (E149), the output of the 4105 shift register (D105) connects first 05 and selects circuit (G105), first one by one the output of zero shift register (A110) connect the first 06 selection circuit (G106), the output of the one one four nine adder (E149) connects first and selects one by one circuit (G111), first 05 selects the output of circuit (G105) to connect the one one adder on May Day (E151), first 06 selects the output of circuit (G106) to connect the one one adder on May Day (E151), first selects the output of circuit (G111) to connect the first First Five-Year Plans two adders (E152) one by one, the output of the one one adder on May Day (E151) connects the first First Five-Year Plans two adders (E152), the output of the first First Five-Year Plans two adders (E152) connects the second First Five-Year Plans three adders (E153),

The 31 one by one the output of shift register (C111) connect the 1 and select circuit (G124), second one by one the output of four shift registers (B114) connect the 1 and select circuit (G125), first one by one the output of six shift registers (A116) connect the 1 and select circuit (G126), the one two four selects the output of circuit (G124) to connect the one one six seven adder (E167), the one two five selects the output of circuit (G125) to connect the one one six seven adder (E167), the one two six selects the output of circuit (G126) to connect the one one six eight adder (E168), the output of the one one zero option circuit (G110) connects the one one six eight adder (E168), the output of the one one six seven adder (E167) connects the one one six nine adder (E169), the output of the one one six eight adder (E168) connects the one one six nine adder (E169), the output of the one one six nine adder (E169) connects the second First Five-Year Plans three adders (E153),

The output of the 3108 shift register (C108) connects first 07 and selects circuit (G107), second one by one the output of zero shift register (B110) connect the first 08 selection circuit (G108), the 1 one by one the output of shift register (A111) connect the first 09 selection circuit (G109), first 07 selects the output of circuit (G107) to connect the one one the May 4th adder (E154), first 08 selects the output of circuit (G108) to connect the one one the May 4th adder (E154), first 09 selects the output of circuit (G109) to connect the first First Five-Year Plan slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E155), the output of the one one zero option circuit (G110) connects the first First Five-Year Plan slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E155), the output of the one one the May 4th adder (E154) connects the first First Five-Year Plans six adders (E156), the output of the first First Five-Year Plan slender acanthopanax musical instruments used in a Buddhist or Taoist mass (E155) connects the first First Five-Year Plans six adders (E156), the output of the first First Five-Year Plans six adders (E156) connects the second First Five-Year Plans three adders (E153),

The second First Five-Year Plan zero adder (E150) to the data-conversion from the one one four seven adder (E147) input, the second First Five-Year Plans three adders (E153) to the data-conversion from the first First Five-Year Plans six adders (E156) input;

The output data of the second First Five-Year Plans three adders (E153) are as brightness fraction pixel point.

4. a HEVC interframe colourity single-point interpolating apparatus, is characterized in that, comprising: 14 shift registers, ten adders and 14 selection circuit;

Wherein, described 14 shift registers comprise: four are followed successively by the move right shift register of 1 of input data: the first two shift registers (A112) one by one, the first three shift registers (A113) one by one, the first four shift registers (A114) one by one, the first seven shift registers (A117) one by one, four are followed successively by the move right shift register of 2 of input data: the 21 shift register (B111) one by one, the second two shift registers (B112) one by one, the second three shift registers (B113) one by one, the 21 First Five-Year Plan shift register (B115), two by the move right shift register of 3 of input data: the 3109 shift register (C109), the 3rd two shift registers (C112) one by one, two by the move right shift register of 4 of input data: the 4106 shift register D106, the 4108 shift register (D108), two by the move right shift register of 5 of input data: May Day 04 shift register F104, shift registers on May Day 06 (F106),

Described ten adders comprise: six adders that input data are added, be followed successively by: the first First Five-Year Plans seven adders (E157), the first First Five-Year Plans eight adders (E158), the first First Five-Year Plans nine adders (E159), the one one six zero adder (E160), the one one six one adder (E161), the one one six two adder (E162), one has the adder that input data-conversion is added later to function: the 2163 adder (E163), the one one seven zero adder (E170), the first 171 adder (E171), the one one seven two adder (E172),

Select circuit to be followed successively by for 14: the one one two selects circuit (G112), the one one three selects circuit (G113), the one one four selects circuit (G114), the first First Five-Year Plan was selected circuit (G115), the one one six selects circuit (G116), the one one seven selects circuit (G117), the one one eight selects circuit (G118), the one one nine selects circuit (G119), the one or two zero option circuit (G120), the one sixteen selects circuit (G128), the one two nine selects circuit (G129), the one or three zero option circuit (G130), the one three one selects circuit (G131), the one three two selects circuit (G132),

X ₀as data input first three shift registers (A113) and second, two shift registers (B112) one by one one by one, X ₁as data, input shift register on May Day 04 (F104), the 4106 shift register (D106), the 3109 shift register (C109), the 21 shift register (B111) and first two shift registers (A112) one by one one by one, X ₂as data, input shift register on May Day 06 (F106), the 4108 shift register (D108), the 3rd two shift registers (C112), the 21 First Five-Year Plan shift register (B115) and first seven shift registers (A117) one by one one by one, X ₃as data input first four shift registers (A114) and second, three shift registers (B113) one by one one by one, constant 0 is also inputted respectively the 1 and is selected circuit (G112), the one one three selects circuit (G113), the one one four selects circuit (G114), the first First Five-Year Plan was selected circuit (G115), the one one six selects circuit (G116), the one one four selects circuit (G114), the one one eight selects circuit (G118), the one one nine selects circuit (G119), the one sixteen selects circuit (G128), the one two nine selects circuit (G129), the one or three zero option circuit (G130), the one three one selects circuit (G131), the one three two selects circuit (G132) and the one or two zero option circuit (G120),

The output of shift registers on May Day 04 (F104) connects the 1 and selects circuit (G112), the output of the 4106 shift register (D106) connects the 1 and selects circuit (G113), the output of the 3109 shift register (C109) connects the 1 and selects circuit (G114), the 21 one by one the output of shift register (B111) connected for the first First Five-Year Plan and select circuit (G115), first one by one the output of two shift registers (A112) connect the 1 and select circuit (G116), the one one two selects the output of circuit (G112) to connect the first First Five-Year Plans seven adders (E157), the one one three selects the output of circuit (G113) to connect the first First Five-Year Plans seven adders (E157), the one one four selects the output of circuit (G114) to connect the one one six one adder (E161), the first First Five-Year Plan selected the output of circuit (G115) to connect the first First Five-Year Plans eight adders (E158), the one one six selects the output of circuit (G116) to connect the first First Five-Year Plans eight adders (E158), the output of the first First Five-Year Plans seven adders (E157) connects the one one six one adder (E161), the output of the first First Five-Year Plans eight adders (E158) connects the one one six one adder (E161),

The output of shift registers on May Day 06 (F106) connects the 1 and selects circuit (G128), the output of the 4108 shift register (D108) connects the 1 and selects circuit (G129), the 3rd one by one the output of two shift registers (C112) connect the one or three zero option circuit (G130), the output of the 21 First Five-Year Plan shift register (B115) connects the 1 and selects circuit (G131), first one by one the output of seven shift registers (A117) connect the 1 and select circuit (G132), the one sixteen selects the output of circuit (G128) to connect the one one seven zero adder (E170), the one two nine selects the output of circuit (G129) to connect the one one seven zero adder (E170), the output of the one or three zero option circuit (G130) connects the one one seven two adder (E172), the one three one selects the output of circuit (G131) to connect the first 171 adder (E171), the one three two selects the output of circuit (G132) to connect the first 171 adder (E171), the output of the first 171 adder (E171) connects the one one seven two adder (E172), the output of the first 171 adder (E171) connects the one one seven two adder (E172),

First one by one the output of three shift registers (A113) connect the 1 and select circuit (G117), second one by one the output of two shift registers (B112) connect the 1 and select circuit (G118), the one one seven selects the output of circuit (G117) to connect the first First Five-Year Plans nine adders (E159), and the one one eight selects the output of circuit (G118) to connect the first First Five-Year Plans nine adders (E159); First one by one the output of four shift registers (A114) connect the 1 and select circuit (G119), second one by one the output of three shift registers (B113) connect the one or two zero option circuit (G120), the one one nine selects the output of circuit (G119) to connect the one one six zero adder (E160), and the output of the one or two zero option circuit (G120) connects the one one six zero adder (E160); The output of the first First Five-Year Plans nine adders (E159) connects the one one six two adder (E162), and the output of the one one six zero adder (E160) connects the one one six two adder (E162);

The output of the output of the one one six one adder (E161) and the one one seven two adder (E172) connects the 2163 adder (E163), the output of the one one six two adder (E162) connects the 2163 adder (E163), the 2163 adder (E163) is to the data-conversion from the one one six two adder (E162) input, and the output data of the 2163 adder (E163) are as colourity fraction pixel point.