CN105245798B - The CCD video compress measurement imaging system and control method perceived based on splits' positions - Google Patents
The CCD video compress measurement imaging system and control method perceived based on splits' positions Download PDFInfo
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- 238000005259 measurement Methods 0.000 title claims abstract description 49
- 238000003384 imaging method Methods 0.000 title claims abstract description 36
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Abstract
The invention discloses a kind of CCD video compress measurement imaging system and control method perceived based on splits' positions, system includes FPGA controller, ccd image sensor, CCD drive circuits, correlated double sampling circuit CDS, programmable gain amplifier PGA circuits, sampling holding/capacitor array, randomizer, multiway analog switch MUX, analog adder, A/D converter (ADC), memory and encoder.Method includes：System initialization, randomizer produce the random number matrix of a M rows N row；The charging of 1st simulation sub-block；The wheel current charge of two simulation sub-blocks；The alternate compression measurement of two simulation sub-blocks.The system has the features such as versatility, encryption, robustness and the scalability of compressed sensing imaging system.By the alternating unloading of series analog memory electric signal, picture is compressed into CCD frame rate completion video scene.Measurement number is the method reduce, effectively reduces biosensor power consumption, and reduces the speed and bandwidth requirement of A/D converter (ADC), also reduces cost.
Description
Technical field
The present invention relates to image, video signal treatment technique field, and neck is realized more particularly to compression image system hardware
The compression measured value in domain obtains system and control method.
Background technology
Compressed sensing (compressive sensing, CS) is the new theory and technology that last decade grows up.Pass
System signal sampling must comply with nyquist sampling theorem, and its sample frequency is at least twice of signal highest frequency；Tradition
Image/video is based on nyquist sampling, then carries out data compression with the compression method such as H.264, therefore conventional compression treats
Journey abandons bulk redundancy information, wastes substantial amounts of memory space and computing resource.And compressed sensing is theoretical with sparse signal representation
Premised on, it is openness to take full advantage of the structure of signal in itself, by selecting suitable calculation matrix, with far below Nyquist
Sample rate realizes signal while compression and sampling.Compression sensing theory brings the theoretical change of signal acquisition, in analog information
Change, be compressed into the fields such as picture, radar imagery, biomedical imaging, radio sensing network and Internet of Things there is wide application
Prospect.
In recent years, domestic and foreign scholars have carried out numerous studies to the imaging system based on compressed sensing, and these researchs are mostly
Deploy around how to realize space light modulation.2006, rice university Baraniuk etc. was proposed and realized a kind of single
Pixel camera, utilize DMD (Digital Micromirror Device, DMD), single pixel detector and A/D
Converter obtains compression measurement.The imaging system control system is complicated, cost is high, and picking rate is slow, it is difficult to realizes Real Time Compression
Imaging.
MIT Fergus etc. proposes random lens camera model, and the camera lens use random reflected minute surface, random anti-
Mirror is penetrated to control by calculation matrix.The camera has super-resolution and estimation of Depth ability, but the complicated consumption of lens calibration of camera
When, storage demand is big, image taking speed is low.
The COMP-I seminar of Duke universities proposes multiple aperture imaging system, and the camera completes pressure using code aperture technology
Contracting sampling, then original image is reconstructed, but the system architecture is complex, it is difficult to realize.
Robucci in 2008 etc. proposes CMOS compression imaging devices, and it divides the image into not overlapping sub-block, by mould
Intend the random summation of pixel progress and realize compression sampling with A/D conversions.The system needs simulation register to store random matrix, deposits
Storage demand is big, power consumption is larger, realizes complicated.
Jacques in 2009 etc. proposes the CMOS compression imaging methods based on random convolution, and it passes through shift register pair
Simulation pixel carries out random convolutional calculation, realizes compression sampling.The system is realized simply, but to be carried out repeatedly during acquisition measured value
Shifting function, image acquisition efficiency is low, power consumption is big.
In a word, it is existing to be compressed into as system complex, compression sampling speed are slow, it is impossible to be used in Real-time Video Compression samples.It is many
Well known, CCD is better than cmos imaging effect, but it is all to use serial output signal to be limited to CCD structures, causes compression sampling process
In be difficult carry out linear projection.Therefore, there is more technical bottleneck for video compress imaging field.
The content of the invention
Based on above-mentioned technical problem, the present invention propose it is a kind of it is new based on the CCD video compress that splits' positions perceive into
As measured value acquisition system and its control method, this method are first sensed ccd image based on splits' positions perception theory
Every frame simulation pixel of device Serial output is divided into number of pixels identical simulation sub-block, then by introducing sampling holding/electric capacity
Array replaces the simulation pixel sub-block of unloading Serial output, then carries out analog compression calculating to simulation pixel sub-block, then use A/D
Converter obtains the digital measured value that compression calculates the analog signal of output, is surveyed by the compression respectively to all simulation sub-blocks
Amount, the final compression sampling for obtaining frame of video.
The purpose of the present invention is realized by following technical proposals.
Present invention firstly provides a kind of CCD compression measurement video imaging systems perceived based on splits' positions, the system
Including ccd image sensor, CCD drive circuits, FPGA controller, correlated double sampling circuit CDS, programmable automation controller PGA
Circuit, sampling holding/capacitor array, randomizer, analog multichannel switch MUX circuit, analog adder, A/D converter
(ADC), memory, encoder and communication interface, wherein：
FPGA controller, for producing CCD vertical clock signals, sampling keeps array signal and A/D changeover control signals；
Ccd image sensor, for perceiving the light intensity signal of video scene, and electric signal is converted into, in ccd image
The scenario simulation picture element matrix that generation is represented with voltage signal on sensor；
CCD drive circuits, for CCD vertical clock signals to be entered into row buffering and driving；
Correlated double sampling circuit CDS, for completing the demodulation of CCD output voltage signals；
Programmable gain amplifier PGA circuits, for the amplification of CCD output voltage signals, and meanwhile correlated-double-sampling is electric
High-frequency noise in the CCD voltage signals exported after the CDS of road filters out；
Holding/capacitor array is sampled, for storing the simulation pixels of CCD Serial outputs to capacitor array；
Randomizer, for producing two-value random measurement matrix；
Multiway analog switch MUX circuit, calculated for controlling simulation pixel to complete compression；
Analog adder, calculated for completing simulation pixel compression；
A/D converter (ADC), compression result of calculation is converted into digital quantity；
Memory, store the data signal being converted to；
Encoder, every frame compression imaging data is encoded；
The FPGA controller connects ccd image sensor, CCD drive circuits, A/D converter (ADC), sampling guarantor respectively
Hold/capacitor array, memory and encoder；The drive circuit, ccd image sensor are connected with each other, and ccd image sensor connects
Correlated double sampling circuit is connect, correlated double sampling circuit is connected to sampling holding/electric capacity battle array by programmable gain amplifier PGA
Row, sampling holding/capacitor array pass through multiway analog switch MUX connection analog adders and randomizer, analog addition
Device is connected to A/D converter (ADC).
Further, the system provides simulation pixel matrix using ccd image sensor to the system.
Further, the programmable gain amplifier PGA circuits are LPF amplifying circuit, programmable automation controller
Device PGA and correlated double sampling circuit CDS completes the processing of CCD output voltage signals jointly.
Further, the CCD video compress perceived based on splits' positions measures imaging system, it is characterised in that
Sampling holding/the capacitor array is made up of 2 simulation sub-blocks, the simulation of two simulation sub-blocks unloading CCD Serial outputs in turn
Picture element signal.
Further, described random number generator circuit produces the two-value random measurement matrix of M rows N row, with these with
Machine signal controls the instantaneous break-make of multiway analog switch MUX circuit.
Further, described multiway analog switch MUX circuit and analog adder circuit, in random number generator circuit
Under the control of output signal, the partial simulation pixel in random selection simulation sub-block is sent to analog adder circuit and completes mould simultaneously
Intend compression to calculate, then result is sent to A/D converter and converts analog signals into digital quantity.
Further, described encoder is provided with USB interface, SD card and Gige gigabit network interfaces, completes data communication.
, should present invention also offers a kind of control method of the CCD video compress measurement imaging perceived based on splits' positions
Method comprises the following steps：
System initialization：For L × C simulation pixel, it is assumed that be classified as T simulation sub-block, each sub-block has N number of mould
Intend pixel, sub-block sum T=L × C/N；N is made to represent unit number in block, t is the simulation sub-block sequence number currently to charge, and tt is completion
The sub-block number of measurement is compressed, m is that the sub-block of current compression measurement compresses pendulous frequency；Make n=1, t=1, x=(t-1) * N+
N, tt=0, m=1；
Step 1：Randomizer produces the random number matrix of a M rows N row；Start FPGA controller and produce reading
The cycle clock signal of ccd image sensor pixel video frame, then ccd image sensor start Serial output simulation pixel；Just
Beginningization A/D converter mode of operation；
Step 2：FPGA controller produces the charging control signal S1 of xth unit, makes n=n+1；
Step 3：Judge n>N, step 2 is repeated if condition is invalid；If condition is set up, first analog submodule is represented
Block charging is finished, and measurement is then compressed to simulation pixel, then makes t=t+1, n=1, goes to step 4；
Step 4：5 and step 9 are gone to step simultaneously, step 5-8 and step 9-13 are performed parallel：
Step 5：FPGA controller produces the charging control signal S1 of xth unit, then makes n=n+1；
Step 6：Judge n>N, condition is invalid to be gone to step 5 and continues to charge to current sub-block；If condition, which is set up, represents current
Simulation sub-block charging finishes, then makes t=t+1, n=1, go to step 7；
Step 7：Judge t>2, if condition is invalid to go to step 5；T=1, n=1 are made if condition is set up, goes to step 8；
Step 8：5 execution are gone to step, then repeat to charge to two simulation sub-blocks in turn；
Step 9：FPGA controller produces the gating signal S2 in turn of two simulation sub-blocks；
Step 10：M row random sequences are output to multiway analog switch MUX control terminal；
Step 11：Start A/D converter, read A/D transformation results again after the enough time that is delayed, and send memory cell to protect
Deposit；Make m=m+1；
Step 12：Judge m>M, if condition is invalid to represent that current sub-block compression measurement does not complete, go to step 10 execution；
If condition sets up current sub-block, compression is measured, and is made tt=tt+1, m=1, is gone to step 13, starts to compress next sub-block
Measurement；
Step 13：Judge tt>T, if condition is invalid, represents that present frame compression measurement does not complete, go to step 9 execution；If
Condition is set up, then current video frame compression measurement has finished, then makes tt=1, goes to step 9 execution.
Data slot flow in the control method that the CCD video compress perceived based on splits' positions is imaged by the present invention
It is divided into：Step 2-3 realizes the charging of the 1st simulation sub-block；Step 5-8 realizes the wheel current charge of two simulation sub-blocks；Step
9-13 realizes the alternate compression measurement of two simulation sub-blocks；Step 5-8 and step 9-13 parallel processings, the 1st simulation sub-block charging
While the 2nd simulation sub-block compression measurement, and the 2nd simulation sub-block charging while the 1st simulation sub-block compression measurement, two
The different disposal of sub-block forms parallel time piece handling process.
Compared with prior art, the system has the versatility of compressed sensing imaging system, encryption, robustness and can stretched
The features such as contracting.Compared to other compression sampling systems, the system turns the simulation electrical pixel of ccd image sensor Serial output
Deposit, by carrying out analog compression calculating to N number of simulation pixel in sub-block, realize the splits' positions of ccd image sensor frame of video
Perceive, picture is compressed into ccd image sensor frame rate completion video scene.Compared to conventional imaging method, greatly reduce
Measurement number, effectively reduces biosensor power consumption, and reduces the speed and bandwidth requirement of A/D converter, also reduces into
This.
Brief description of the drawings
Fig. 1 is the system structure diagram of the CCD perceived based on splits' positions the compression measurement video imagings of the present invention；
Fig. 2 is the sampling holding capacitor array structure schematic diagram of the present invention；
Fig. 3 is the control method flow of the CCD perceived based on splits' positions the compression measurement video imagings of the present invention；
Fig. 4 is the data slot in the control method for the CCD video compress imaging that the present invention is perceived based on splits' positions
Flow.
Embodiment
Fig. 1 is the system structure diagram of the CCD perceived based on splits' positions the compression measurement video imagings of the present invention, this
System is by ccd image detecting sensor, and for providing series analog memory pixel source to the system, the system includes：
FPGA controller, its function include:(1) all control signals needed for CCD are produced, start CCD Serial output moulds
Intend pixel modulated signal；(2) produce sampling and keep array frame pixel synchronization and clock signal；(3) A/D conversion and controls letter is produced
Number, start A/D conversions, and read A/D transformation results；(4) compressed encoding is completed；(5) data Control on Communication is completed.
Ccd image sensor, perceives the light intensity signal of video scene, and is converted into electric signal, and use is produced on CCD
The scenario simulation picture element matrix that voltage signal represents；
CCD drive circuits, buffering and driving for CCD vertical clock signals；
One of correlated double sampling circuit CDS, ccd signal process circuit.CDS circuits keep pulse with two samplings, adopt in advance
Sample pulse (SHP) and data sampling pulse (SHD), priority double sampling is carried out to each pixel in CCD output voltage signals.
When pre-sampling pulse is effective, first the floating grid level portions in each pixel are carried out with a pre-sampling and is kept；Work as data
When sampling pulse is effective, then to video signal sampling and keep.Double sampling difference is real CCD vision signals.
One of programmable gain amplifier PGA circuits, ccd signal process circuit.PGA is usually LPF amplification electricity
Road, for the amplification of CCD output voltage signals, while the height in the CCD voltage signals that will be exported after correlated double sampling circuit CDS
Frequency noise filtering.
Holding/capacitor array is sampled, as shown in Fig. 2 each frame simulation pixel of Serial output is divided into by the structure member
Many sub-blocks are stored in sampling and kept on the electric capacity of array respectively.If ccd image sensor has L rows, C to show effect pixel, i.e., should
Promising L × C valid pixel.Capacitor array by 2 × N number of unit forms, be divided into 2 simulation sub-blocks, each sub-block has N number of list
Member.Each unit connection analog switch K1 and K2, K1 conducting under signal S1 controls is charged to electric capacity.In each simulation sub-block
The analog switch K2 of N number of unit is simultaneously turned under sub-block gating signal S2 controls, and the simulation pixel in the sub-block is sent simultaneously
To multiway analog switch MUX.Signal S1, S2 are produced by internal logic circuit, and S1 effective times are 1 CCD master clock cycle；S2
Time duration is relevant with compression pendulous frequency M.
Randomizer, produce and meet uncorrelated two-value random number matrix of the M length for N points, as calculation matrix,
Send in calculation matrix memory and preserve, sampled as M second compressions.Meanwhile often row random number it will send multichannel mould under FPGA controls
Intend switch MUX control terminals.With the instantaneous break-make of these random signals control multiway analog switch MUX circuit.
Multiway analog switch MUX circuit, built-in N number of analog switch, the simulation pixel of control simulation sub-block are output to addition
Device computing.Multiway analog switch MUX circuit and analog adder circuit, in the control of random number generator circuit output signal
Under, the partial simulation pixel in random selection simulation sub-block is sent to analog adder circuit and completes analog compression calculating simultaneously, then
Result is sent to A/D converter and converts analog signals into digital quantity.
Analog adder, the N roads simulation pixel that analog multichannel switch MUX is exported carry out analog compression calculating, input
High input impedance, output end low output impedance, operation result send A/D converter；
A/D converter (ADC), under FPGA controls, analog-to-digital conversion is carried out to the analog signal of analog operating unit output, and
Memory is sent to preserve.
Memory, store the data signal being converted to；
Encoder, every frame compression imaging data is encoded；
SD card, coded data is stored, realizes plug and play；
USB interface, USB driver interface, realize USB high-speed data communications；
Gige gigabit network interfaces, realize gigabit networking interface communication；
In system, FPGA controller connects ccd image sensor, CCD drive circuits, A/D converter (ADC), adopted respectively
Sample holding/capacitor array, memory and encoder；The drive circuit, ccd image sensor are connected with each other, ccd image sensing
Device connects correlated double sampling circuit, and correlated double sampling circuit is connected to sampling holding/electric capacity by programmable gain amplifier PGA
Array, sampling holding/capacitor array are added by multiway analog switch MUX connection analog adders and randomizer, simulation
Musical instruments used in a Buddhist or Taoist mass is connected to A/D converter (ADC).
For the simulation pixel of ccd image sensor Serial output, by sample keep any analog submodule in capacitor array
After block storage, it becomes possible to the N number of simulation pixel of parallel output；When any sub-block gating signal works, by the mould of sub-block output
Intend signal and be expressed as column vector Xt；
M rows N row two-value random number matrix φ caused by randomizerB=[φ1；φ2；…；φM] measured for piecemeal
Matrix, wherein φi(i=1 ..., M) is the row vector of N number of element；Randomizer exports the N number of two-value random number of any row
When, sub-block output analog signal is compressed and calculates to obtain y by analog multichannel switch MUXi=φiXt(i=1 ..., M)；M second compressions
The column vector Y of M element is obtained after measurementt=[y1；y2,…,yM]T；
It is L × C pixel for whole frame of video, it is assumed that T sub-block can be divided into, T values are more than or equal to [L*C/N]
Smallest positive integral, remember NN=T × N, then video frame pixel is represented by the column vector Y=[X of NN element1,X2,…,XT]T.For
The calculation matrix Ф of frame of video all pixels is T piecemeal calculation matrix φBThe diagonal matrix of composition, and the compression of frame of video is adopted
Sample result is the column vector of M × T element, i.e. Y=[Y1,Y2,…,YT]T；Finally, the compression measurement result of frame of video can represent
For Y=Ф X；Known video compresses measurement result Y and calculation matrix Ф, it becomes possible to reconstructing video frame X.
The system perceives visual field optical signal using ccd image sensor, exports the scene mould serially represented with voltage signal
Intend pixel；And then the simulation pixel of every frame video of CCD Serial outputs is divided into the sub-block of many same pixel numbers, alternating is deposited
Store up in two simulation sub-blocks inside sampling holding/capacitor array, realize the high speed unloading and storage of analog voltage signal；Again
By the circuit such as calculation matrix, multiway analog switch MUX on-off circuits and analog adder caused by randomizer to storage
Keep the analog voltage signal on array to carry out analog compression calculating in turn in the presence of two groups of samplings, complete to perceive based on splits' positions
Theoretical stochastic linear projection；Then the output signal for simulating calculating is converted into data signal using A/D converter to be stored in
In memory, the final splits' positions imaging data obtained per frame video scene.
As shown in figure 3, the invention also provides a kind of controlling party of the CCD video compress imaging perceived based on splits' positions
Method, this method comprise the following steps：
Initialization：For L × C simulation pixel, it is assumed that be classified as T simulation sub-block, each sub-block has N number of photofit picture
Element, sub-block sum T=L × C/N；N is made to represent unit number in block, t is the simulation sub-block sequence number currently to charge, and tt compresses for completion
The sub-block number of measurement, m are that the sub-block of current compression measurement compresses pendulous frequency；Make n=1, t=1, x=(t-1) * N+n, tt
=0, m=1.
Step 1：Randomizer produces the random number matrix of a M rows N row；Start FPGA controller and produce reading
The cycle clock signal of ccd image sensor pixel video frame, then ccd image sensor start Serial output simulation pixel；Just
Beginningization A/D converter mode of operation；
Step 2：FPGA controller produces the charging control signal S1 of xth unit, makes n=n+1；
Step 3：Judge n>N, step 2 is repeated if condition is invalid；If condition is set up, represent that first sub-block is filled
Electricity finishes, and can start simulation sub-block pixel and be compressed calculating, then make t=t+1, n=1, go to step 4；
Step 4：5 and step 9 are gone to step simultaneously, step 5-8 and step 9-13 are performed parallel：
Step 5：FPGA controller produces the charging control signal S1 of xth unit, then makes n=n+1；
Step 6：Judge n>N, condition is invalid to be gone to step 5 and continues to charge to current sub-block；If condition, which is set up, represents current
Simulation sub-block charging finishes, then makes t=t+1, n=1, go to step 7；
Step 7：Judge t>2, if condition is invalid to go to step 5；T=1, n=1 are made if condition is set up, goes to step 8；
Step 8：5 execution are gone to step, then repeat to charge to two simulation sub-blocks in turn；
Step 9：FPGA controller produces the gating signal S2 in turn of two simulation sub-blocks；
Step 10：M row random sequences are output to multiway analog switch MUX control terminal；
Step 11：Start A/D converter, read A/D transformation results again after the enough time that is delayed, and send memory cell to protect
Deposit；Make m=m+1；
Step 12：Judge m>M, if condition is invalid to represent that current sub-block compression measurement does not complete, go to step 10 execution；
If condition sets up current sub-block, compression is measured, and is made tt=tt+1, m=1, is gone to step 13, starts to compress next sub-block
Measurement；
Step 13：Judge tt>T, if condition is invalid, represents that present frame compression measurement does not complete, go to step 9 execution；If
Condition is set up, and is represented that current video frame compression measurement has finished, is then made tt=1, goes to step 9 execution.
Fig. 4 is that the present invention is proposed in a kind of control method of the CCD video compress imaging perceived based on splits' positions
Data slot flow：
Step 2-3 realizes the charging of the 1st simulation sub-block；
Step 5-8 realizes the wheel current charge of two simulation sub-blocks；Step 9-13 realizes the alternate compression of two simulation sub-blocks
Measurement；Wherein step 5-8 and step 9-13 parallel processings, the 2nd simulation sub-block compression survey while the 1st simulation sub-block charges
Amount, and the 1st simulation sub-block compression measurement while the 2nd simulation sub-block charging, when the different disposal of two sub-blocks forms parallel
Between piece handling process, improve the speed and efficiency of processing.
Claims (8)
1. imaging system is measured based on the CCD video compress that splits' positions perceive, it is characterised in that the system includes：
FPGA controller, for producing CCD vertical clock signals, sampling keeps array signal and A/D changeover control signals；
Ccd image sensor, for perceiving the light intensity signal of video scene, and electric signal is converted into, is sensed in ccd image
The scenario simulation picture element matrix that generation is represented with voltage signal on device；
CCD drive circuits, for buffering and driving CCD vertical clock signals；
Correlated double sampling circuit CDS, for completing the demodulation of CCD output voltage signals；
Programmable gain amplifier PGA circuits, amplify for CCD output voltage signals, at the same correlated double sampling circuit CDS is defeated
High-frequency noise in the CCD voltage signals gone out filters out；
Holding/capacitor array is sampled, for storing the simulation pixel of CCD Serial outputs；Sampling holding/the capacitor array is by 2
Individual simulation sub-block is formed, the analog pixel signal of two simulation sub-blocks unloading CCD Serial outputs in turn；
Randomizer, for producing two-value random measurement matrix；
Multiway analog switch MUX circuit, calculated for controlling simulation pixel to complete compression；
Analog adder, calculated for completing simulation pixel compression；
A/D converter, compression result of calculation is converted into digital quantity；
Memory, store the data signal being converted to；
Encoder, coding is compressed to every frame compression imaging data；
The FPGA controller connects ccd image sensor, CCD drive circuits, A/D converter, sampling holding/electric capacity battle array respectively
Row, memory and encoder；The drive circuit, ccd image sensor are connected with each other, and ccd image sensor connection is related double
Sample circuit, correlated double sampling circuit are connected to sampling holding/capacitor array by programmable gain amplifier PGA, and sampling is protected
Hold/capacitor array is connected to A/ by multiway analog switch MUX connection analog adders and randomizer, analog adder
D converters.
2. the CCD video compress according to claim 1 perceived based on splits' positions measures imaging system, its feature exists
In the system provides simulation pixel matrix using ccd image sensor to the system.
3. the CCD video compress according to claim 1 perceived based on splits' positions measures imaging system, its feature exists
In the programmable gain amplifier PGA circuits are LPF amplifying circuit, and programmable gain amplifier PGA and correlation are double
Sample circuit CDS completes the processing of CCD output voltage signals jointly.
4. the CCD video compress according to claim 1 perceived based on splits' positions measures imaging system, its feature exists
In the random number generator circuit produces the two-value random measurement matrix of M rows N row, and multichannel mould is controlled with these random signals
Intend the instantaneous break-make of switch MUX circuit.
5. the CCD video compress according to claim 1 perceived based on splits' positions measures imaging system, its feature exists
In the multiway analog switch MUX circuit and analog adder circuit, in the control of random number generator circuit output signal
Under, the partial simulation pixel in random selection simulation sub-block is sent to analog adder circuit and completes analog compression calculating simultaneously, then
Result is sent to A/D converter and converts analog signals into digital quantity.
6. the CCD video compress according to claim 1 perceived based on splits' positions measures imaging system, its feature exists
In the encoder is provided with USB interface, SD card and Gige gigabit network interfaces, completes data communication.
A kind of 7. control method of the CCD video compress measurement imaging perceived based on splits' positions, it is characterised in that this method bag
Include following steps：
System initialization：For L × C simulation pixel, it is assumed that be classified as T simulation sub-block, each sub-block has N number of photofit picture
Element, sub-block sum T=L × C/N；N is made to represent unit number in block, t is the simulation sub-block sequence number currently to charge, and tt compresses for completion
The sub-block number of measurement, m are that the sub-block of current compression measurement compresses pendulous frequency；Make n=1, t=1, x=(t-1) * N+n, tt
=0, m=1；
Step 1：Randomizer produces the random number matrix of a M rows N row；Start FPGA controller and produce reading CCD figures
As the cycle clock signal of sensor pixel frame of video, then ccd image sensor starts Serial output simulation pixel；Initialize A/
D converter mode of operations；
Step 2：FPGA controller produces the charging control signal S1 of xth unit, makes n=n+1；
Step 3：Judge n>N, step 2 is repeated if condition is invalid；If condition is set up, represent that first simulation sub-block is filled
Electricity is finished, and measurement is then compressed to simulation pixel, then makes t=t+1, n=1, goes to step 4；
Step 4：5 and step 9 are gone to step simultaneously, step 5-8 and step 9-13 are performed parallel：
Step 5：FPGA controller produces the charging control signal S1 of xth unit, then makes n=n+1；
Step 6：Judge n>N, condition is invalid to be gone to step 5 and continues to charge to current sub-block；If condition, which is set up, represents present day analog
Sub-block charging finishes, then makes t=t+1, n=1, go to step 7；
Step 7：Judge t>2, if condition is invalid to go to step 5；T=1, n=1 are made if condition is set up, goes to step 8；
Step 8：5 execution are gone to step, then repeat to charge to two simulation sub-blocks in turn；
Step 9：FPGA controller produces the gating signal S2 in turn of two simulation sub-blocks；
Step 10：M row random sequences are output to multiway analog switch MUX control terminal；
Step 11：Start A/D converter, read A/D transformation results again after the enough time that is delayed, and send memory cell to preserve；
Make m=m+1；
Step 12：Judge m>M, if condition is invalid to represent that current sub-block compression measurement does not complete, go to step 10 execution；If bar
Part is set up current sub-block compression and is measured, then makes tt=tt+1, m=1, go to step 13, starts to compress measurement to next sub-block；
Step 13：Judge tt>T, if condition is invalid, represents that present frame compression measurement does not complete, go to step 9 execution；If condition
Set up, then current video frame compression measurement has finished, then makes tt=1, goes to step 9 execution.
8. the control method for the CCD video compress measurement imaging that splits' positions according to claim 7 perceive, its feature exist
In the data slot flow in control method is that step 2-3 realizes the charging of the 1st simulation sub-block；Step 5-8 realizes two
The wheel current charge of individual simulation sub-block；Step 9-13 realizes the alternate compression measurement of two simulation sub-blocks；Step 5-8 and step 9-13
Parallel processing, the 2nd simulation sub-block compression measurement while the 1st simulation sub-block charging, and the while the 2nd simulation sub-block charging
1 simulation sub-block compression measurement, the different disposal of two sub-blocks form parallel time piece handling process.
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Application publication date: 20160113 Assignee: SHAANXI ZHONGKE TRENCHLESS TECHNOLOGY Co.,Ltd. Assignor: Xi'an University Contract record no.: X2023980054277 Denomination of invention: CCD video compression measurement imaging system and control method based on block compression perception Granted publication date: 20180223 License type: Common License Record date: 20231228 |