CN103532498A - Low-detuning sensor detection circuit - Google Patents
Low-detuning sensor detection circuit Download PDFInfo
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- CN103532498A CN103532498A CN201310501369.6A CN201310501369A CN103532498A CN 103532498 A CN103532498 A CN 103532498A CN 201310501369 A CN201310501369 A CN 201310501369A CN 103532498 A CN103532498 A CN 103532498A
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- effect transistor
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Abstract
The invention discloses a low-detuning sensor detection circuit. The low-detuning sensor detection circuit comprises a field-effect tube MOS2, a field-effect tube MOS3, a field-effect tube MOS 5, a field-effect tube MOS 6, a capacitor C1, a capacitor C2, a capacitor C3, a clock control circuit, an amplifier and a DA converter. The low-detuning sensor detection circuit has the advantages that offset voltage at the two ends of the amplifier can be eliminated, the detection accuracy is high, and the circuit structure is simple.
Description
Technical field
The present invention relates to integrated circuit fields, relate in particular a kind of sensor detection circuit of low imbalance.
Background technology
Sensor detection circuit has multiple circuit mode to realize.Because the signal that transducer produces is extremely faint, generally, all in PF magnitude, its capacitance change is generally 10
-15-10
-18f, detect so small capacitance change, particularly important to choosing of each several part circuit in testing circuit.Circuit adopts waveform generator, C-V change-over circuit, inverter, adder, rectification circuit, low pass filter etc. to build circuit at present, and its minimum differential magnitude reaches 10 only
-16f, and its circuit structure is complicated.
Summary of the invention
The invention provides a kind of sensor detection circuit of low imbalance, the offset voltage that they can erase amplifier two ends, accuracy of detection is high, and circuit structure is simple.
For solving above-mentioned technical problem, the present invention by the following technical solutions:
A kind of sensor detection circuit of low imbalance, it comprises field effect transistor MOS2, field effect transistor MOS3, field effect transistor MOS5, field effect transistor MOS6, capacitor C 1, capacitor C 2, capacitor C 3, clock control circuit, amplifier and DA transducer, and the grid of described field effect transistor MOS2, field effect transistor MOS3, field effect transistor MOS5 and field effect transistor MOS6 is all connected on clock control circuit; The drain electrode of the drain electrode of described field effect transistor MOS2 and field effect transistor MOS5 is all connected with power supply; One end ground connection of described capacitor C 1, the other end is connected with the source electrode of field effect transistor MOS2; One end ground connection of described capacitor C 2, the other end is connected with the source electrode of field effect transistor MOS5; Two inputs of described amplifier are connected with the source electrode of field effect transistor MOS5 with the source electrode of field effect transistor MOS2 respectively, and output is connected on DA converter; The two ends of described capacitor C 3 are connected on two inputs of amplifier; The source ground of described field effect transistor MOS3, drain electrode is connected with the source electrode of field effect transistor MOS2; The source ground of described field effect transistor MOS6, drain electrode is connected with the source electrode of field effect transistor MOS5.
Further technical scheme is:
As preferably, between described field effect transistor MOS2, field effect transistor MOS5 and power supply, be also connected with respectively field effect transistor MOS1 and field effect transistor MOS4, the source electrode of described field effect transistor MOS1, the source electrode of field effect transistor MOS4 are connected with the drain electrode of field effect transistor MOS2, the drain electrode of field effect transistor MOS5 respectively, and the drain electrode of the drain electrode of described field effect transistor MOS1 and field effect transistor MOS4 is all connected on power supply.
Compared with prior art, the invention has the beneficial effects as follows:
The present invention comprises field effect transistor, electric capacity, amplifier, DA amplifier and clock control chip, and its circuit structure is simple; And at the two ends of amplifier, be connected with capacitor C 3, the offset voltage of amplifier two inputs can be eliminated, increased accuracy of detection.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is the circuit diagram of embodiment 1.
Fig. 2 is the circuit diagram of embodiment 2.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further illustrated.Embodiments of the present invention include but not limited to the following example.
[embodiment 1]
The sensor detection circuit of a kind of low imbalance as shown in Figure 1, it comprises field effect transistor MOS2, field effect transistor MOS3, field effect transistor MOS5, field effect transistor MOS6, capacitor C 1, capacitor C 2, capacitor C 3, clock control circuit, amplifier and DA transducer, and the grid of described field effect transistor MOS2, field effect transistor MOS3, field effect transistor MOS5 and field effect transistor MOS6 is all connected on clock control circuit; The drain electrode of the drain electrode of described field effect transistor MOS2 and field effect transistor MOS5 is all connected with power supply; One end ground connection of described capacitor C 1, the other end is connected with the source electrode of field effect transistor MOS2; One end ground connection of described capacitor C 2, the other end is connected with the source electrode of field effect transistor MOS5; Two inputs of described amplifier are connected with the source electrode of field effect transistor MOS5 with the source electrode of field effect transistor MOS2 respectively, and output is connected on DA converter; The two ends of described capacitor C 3 are connected on two inputs of amplifier; The source ground of described field effect transistor MOS3, drain electrode is connected with the source electrode of field effect transistor MOS2; The source ground of described field effect transistor MOS6, drain electrode is connected with the source electrode of field effect transistor MOS5.
By clock control circuit, controlled the alternation switch of field effect transistor MOS2, field effect transistor MOS3, field effect transistor MOS5 and field effect transistor MOS6, the folding of field effect transistor MOS2 and field effect transistor MOS3 is synchronous, the folding of field effect transistor MOS5 and field effect transistor MOS6 is synchronous, realizes two electric capacity staggered discharged and recharged to employing.Electric capacity is carried out to identical charging of time, and capacitance size is just relevant to the voltage after charging, and amplifier detects the voltage difference of two electric capacity, amplifies laggard row digital-to-analogue conversion output digit signals, is convenient to follow-up equipment and calculates acceleration.Field effect transistor MOS3, field effect transistor MOS6 are respectively capacitor C 1, capacitor C 2 branch road of living in provides path.On two inputs of amplifier, connect capacitor C 3, the offset voltage at two ends can be eliminated, increase the precision of monitoring.
[embodiment 2]
The sensor detection circuit of a kind of low imbalance as shown in Figure 2, for fear of the phenomenon that is short-circuited between VDD-to-VSS, the present embodiment is on the basis of embodiment 1, between being on the scene effect pipe MOS2, field effect transistor MOS5 and power supply, be also connected with respectively field effect transistor MOS1 and field effect transistor MOS4, the source electrode of described field effect transistor MOS1, the source electrode of field effect transistor MOS4 are connected with the drain electrode of field effect transistor MOS2, the drain electrode of field effect transistor MOS5 respectively, and the drain electrode of the drain electrode of described field effect transistor MOS1 and field effect transistor MOS4 is all connected on power supply.Field effect transistor MOS1 is connected bias voltage with the grid of field effect transistor MOS4, can be provided by external equipment.
Be as mentioned above embodiments of the invention.The present invention is not limited to above-mentioned execution mode, and anyone should learn the structural change of making under enlightenment of the present invention, and every have identical or close technical scheme with the present invention, within all falling into protection scope of the present invention.
Claims (2)
1. the sensor detection circuit of a low imbalance, it is characterized in that: it comprises field effect transistor MOS2, field effect transistor MOS3, field effect transistor MOS5, field effect transistor MOS6, capacitor C 1, capacitor C 2, capacitor C 3, clock control circuit, amplifier and DA transducer, the grid of described field effect transistor MOS2, field effect transistor MOS3, field effect transistor MOS5 and field effect transistor MOS6 is all connected on clock control circuit; The drain electrode of the drain electrode of described field effect transistor MOS2 and field effect transistor MOS5 is all connected with power supply; One end ground connection of described capacitor C 1, the other end is connected with the source electrode of field effect transistor MOS2; One end ground connection of described capacitor C 2, the other end is connected with the source electrode of field effect transistor MOS5; Two inputs of described amplifier are connected with the source electrode of field effect transistor MOS5 with the source electrode of field effect transistor MOS2 respectively, and output is connected on DA converter; The two ends of described capacitor C 3 are connected on two inputs of amplifier; The source ground of described field effect transistor MOS3, drain electrode is connected with the source electrode of field effect transistor MOS2; The source ground of described field effect transistor MOS6, drain electrode is connected with the source electrode of field effect transistor MOS5.
2. the sensor detection circuit of a kind of low imbalance according to claim 1, it is characterized in that: between described field effect transistor MOS2, field effect transistor MOS5 and power supply, be also connected with respectively field effect transistor MOS1 and field effect transistor MOS4, the source electrode of described field effect transistor MOS1, the source electrode of field effect transistor MOS4 are connected with the drain electrode of field effect transistor MOS2, the drain electrode of field effect transistor MOS5 respectively, and the drain electrode of the drain electrode of described field effect transistor MOS1 and field effect transistor MOS4 is all connected on power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310501369.6A CN103532498A (en) | 2013-10-23 | 2013-10-23 | Low-detuning sensor detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310501369.6A CN103532498A (en) | 2013-10-23 | 2013-10-23 | Low-detuning sensor detection circuit |
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| CN103532498A true CN103532498A (en) | 2014-01-22 |
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| CN201310501369.6A Pending CN103532498A (en) | 2013-10-23 | 2013-10-23 | Low-detuning sensor detection circuit |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1256757A (en) * | 1998-02-19 | 2000-06-14 | 住友金属工业株式会社 | Capacitance detection system and method |
| TWI235242B (en) * | 2000-01-13 | 2005-07-01 | Infineon Technologies Ag | Circuit-arrangement to measure capacitances of the structures in an integrated circuit |
| EP2104143A2 (en) * | 2008-03-21 | 2009-09-23 | Commissariat A L'energie Atomique | Structure for testing MOS capacitance and method for measuring a capacitance curve according to the associated voltage |
| CN101742180A (en) * | 2008-11-10 | 2010-06-16 | 康佳集团股份有限公司 | Circuit for realizing two-way sound transmission on same port |
| CN203522653U (en) * | 2013-10-23 | 2014-04-02 | 成都市宏山科技有限公司 | Detection circuit for low-offset sensor |
-
2013
- 2013-10-23 CN CN201310501369.6A patent/CN103532498A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1256757A (en) * | 1998-02-19 | 2000-06-14 | 住友金属工业株式会社 | Capacitance detection system and method |
| TWI235242B (en) * | 2000-01-13 | 2005-07-01 | Infineon Technologies Ag | Circuit-arrangement to measure capacitances of the structures in an integrated circuit |
| EP2104143A2 (en) * | 2008-03-21 | 2009-09-23 | Commissariat A L'energie Atomique | Structure for testing MOS capacitance and method for measuring a capacitance curve according to the associated voltage |
| CN101742180A (en) * | 2008-11-10 | 2010-06-16 | 康佳集团股份有限公司 | Circuit for realizing two-way sound transmission on same port |
| CN203522653U (en) * | 2013-10-23 | 2014-04-02 | 成都市宏山科技有限公司 | Detection circuit for low-offset sensor |
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Application publication date: 20140122 |