CN103532201B - Quick charge circuit for battery - Google Patents
Quick charge circuit for battery Download PDFInfo
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- CN103532201B CN103532201B CN201310517982.7A CN201310517982A CN103532201B CN 103532201 B CN103532201 B CN 103532201B CN 201310517982 A CN201310517982 A CN 201310517982A CN 103532201 B CN103532201 B CN 103532201B
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Abstract
The invention discloses a quick charge circuit for a battery. The quick charge circuit comprises a charge module and a detection module, wherein the detection module is used for comparing a battery voltage with a first threshold voltage and a third threshold voltage lower than the first threshold voltage respectively, outputting a first comparison result when the battery voltage is higher than the third threshold voltage and lower than the first threshold voltage and outputting a second comparison result when the battery voltage is higher than the first threshold voltage; the charge module is used for charging the battery with a first current value according to the first comparison result and alternately charging the battery with different current values according to the second comparison result and a periodic pulse signal. According to the quick charge circuit, the constant-voltage charging time of the battery can be shortened, so that the charging speed of the battery is increased.
Description
Technical field
The present invention relates to field of power management, particularly relate to a kind of Quick charge circuit for battery.
Background technology
Current most of battery charger carries out three sections of chargings and controls: precharge, constant current charge and constant voltage charge.Wherein, constant current charge is all charge to lithium battery with larger current usually, but larger current can produce very large voltage drop in the internal resistance of lithium battery, just easily cause the voltage recording lithium battery in constant current charge process to reach thus and be full of voltage, but the virtual voltage of lithium battery but reaches far away and is full of voltage.For this situation, make after lithium battery virtual voltage reach a certain height by constant current charge, then adopt constant voltage charge just to seem very important.
Fig. 1 is the battery charger of prior art.When cell voltage VBAT is less than the 3rd threshold voltage VPRE (such as 3V), the PRENB signal that the 3rd comparator C3_pre exports is low level, and PREN signal is high level, and switch S 3 conducting, switch S 1 turns off.First operational amplifier IA take 0.1V as reference input voltage, adjustment makes PROG voltage equal 0.1V, now reference current (flows through the electric current of PMOS transistor MP1, also the electric current flowing through resistance RPROG is equaled) equal 0.1V/RPROG, wherein RPROG is the resistance value of resistance Rprog, second operational amplifier MA adjustment allows the electric current of PMOS transistor MP2 equal 1000 times of the electric current of PMOS transistor MP1, namely equals 100/RPROG, is now precharge.When cell voltage VBAT be greater than the 3rd threshold voltage VPRE and cell voltage VBAT lower than first threshold voltage VREG time, feedback control loop controls primarily of the first operational amplifier IA, now PREN signal is low level, PRENB is high level, switch S 1 conducting, switch S 3 turns off, first operational amplifier IA take 1V as reference input voltage, adjustment makes PROG voltage equal 1V, now reference current (flows through the electric current of PMOS transistor MP1, also the electric current flowing through resistance RPROG is equaled) equal 1V/RPROG, wherein RPROG is the resistance value of resistance Rprog, second operational amplifier MA adjustment allows the electric current of MP2 equal 1000 times of the electric current of PMOS transistor MP1, namely 1000/RPROG is equaled, it is now constant current charge.When cell voltage VBAT voltage close to or when equaling first threshold voltage VREG, feedback control loop is controlled by the 3rd operational amplifier VA, cell voltage VBAT is adjusted to and equals first threshold voltage VREG (such as 4.2V), along with battery is continued charging, close to when being full of, charging current constantly declines, and is now constant voltage charge.
In constant voltage charge process, charging current can be reduced along with raising gradually of lithium battery virtual voltage till the virtual voltage of lithium battery reaches and is full of voltage thereupon.But, conventional constant voltage charging all adopts the mode continuing charging, there is not voltage during voltage drop in virtual voltage, i.e. the lithium battery internal resistance that thus cannot record lithium battery in constant voltage charge process, thus in order to avoid over-charge of lithium battery, the charging current mean value just needing constant voltage charge to adopt is very little, and then the process of constant voltage charge also will be caused extremely very long.
In order to shorten the time needed for constant voltage charge, be necessary to improve conventional constant voltage charge mode.
Summary of the invention
The object of the present invention is to provide a kind of circuit of quickly charging battery, to solve above-mentioned prior art battery Problems existing in constant voltage charge process.
To achieve these goals, the invention provides a kind of Quick charge circuit for battery, comprising: charging module and detection module,
Cell voltage compares with first threshold voltage and the 3rd threshold voltage by described detection module respectively, and described first threshold voltage is greater than described 3rd threshold voltage;
When described cell voltage is greater than described 3rd threshold voltage and is less than first threshold voltage, described detection module exports the first comparative result, and described charging module charges to described battery with the first current value according to described first comparative result;
When described cell voltage is greater than described first threshold voltage, described detection module exports the second comparative result, and described charging module alternately charges to described battery with different current value according to described second comparative result and cyclic pulse signal.
According to battery charger of the present invention, the time of battery needed for constant voltage charge process can be shortened, thus accelerate battery charge time.
Accompanying drawing explanation
Fig. 1 is the battery charger structural representation of prior art;
A kind of Quick charge circuit for battery structural representation that Fig. 2 provides for the embodiment of the present invention;
Fig. 3 is the change schematic diagram of cell voltage and charging current in the charging process of circuit shown in Fig. 1;
Fig. 4 is the change schematic diagram of cell voltage and charging current in Fig. 2 illustrated circuit charging process.
Embodiment
After being described in detail embodiments of the present invention by way of example below in conjunction with accompanying drawing, other features of the present invention, feature and advantage will be more obvious.
A kind of Quick charge circuit for battery structural representation that Fig. 2 provides for the embodiment of the present invention.As shown in Figure 2, this circuit comprises charging module 100 and detection module 200.
Particularly, detection module 200 comprises the first comparator Com1, the second comparator Com2, the 3rd comparator Com3, d type flip flop FFDR1 and arithmetic logic unit 210.
The normal phase input end of the first comparator Com1 is connected with cell voltage VBAT, its inverting input is connected with first threshold voltage VREG, its output is connected with the input of d type flip flop FFDR1 and arithmetic logic unit 210 respectively, the output QCPB of d type flip flop FFDR1 is connected with the 3rd or door OR3 mono-input, 3rd or another input of door OR3 input INVENTIONPeriodic digital signals PWM, 3rd or door OR3 output be connected with charging module 100, replace charged state id signal VS4 for exporting large/small area analysis to it.
The positive input of the second comparator Com2 is connected with cell voltage VBAT, its inverting input is connected with Second Threshold voltage VRCG, its output is connected with arithmetic logic unit 210, when cell voltage VBAT is less than Second Threshold voltage VRCG, then export high level VB signal to arithmetic logic unit 210.
The positive input of the 3rd comparator Com3 is connected with cell voltage VBAT, its inverting input is connected with the 3rd threshold voltage VPRE, its output exports PRENB signal, when cell voltage VBAT is less than the 3rd threshold voltage VPRE, the PRENB signal that then the 3rd comparator Com3 exports is electronegative potential, and PREN signal is high potential, now, switch S 1 turns off, switch S 3 conducting.
Arithmetic logic unit 210 comprises first or door OR1 and the first NOR gate NOR2, first and door AND1, the 4th inverter INV4 and the 5th inverter INV5.Wherein, first or the first input end of door OR1 be connected with the output of the second comparator Com2, second input is connected with the output of the first NOR gate NOR2, and its output is connected with the input of the 5th inverter INV5 and an input of the first NOR gate NOR2 respectively; Second input of the first NOR gate NOR2 is connected with the output of door AND1 with first; First is connected with the output of the first comparator Com1 with the first input end of door AND1, and the second input is connected with the output of the 4th inverter INV4; The input input INVENTIONPeriodic digital signals PWM of the 4th inverter INV4, the 5th inverter INV5 exports battery complete charge signal QEND.
Particularly, charging module 100 comprises current mirror, and this current mirror comprises the first branch road be made up of the first MOS transistor MP1, the 3rd MOS transistor MP3 and resistance Rprog and the second branch road be made up of the second MOS transistor MP2 and the 3rd branch road be made up of the 4th MOS transistor MP4.First branch road provides reference current, and the second branch road and the 3rd branch road provide the electric current charged to battery BAT1.
The drain electrode of MOS transistor MP1 is connected the first input end of the second operational amplifier MA with the source of MOS transistor MP3, the drain electrode of MOS transistor MP2 connects second input of the second operational amplifier MA, the output of the second operational amplifier MA is connected with the grid of MOS transistor MP3, and the second operational amplifier MA is equal for the drain voltage of the drain voltage and MOS transistor MP2 that adjust MOS transistor MP1.
Further, charging module 100 also comprises the 4th switch S 4, the 5th switch S 5 and the first inverter INV1, the grid of MOS transistor MP2 and the grid of MOS transistor MP4 are connected by switch S 4 or disconnect, and the 4th switch S 4 is connected with the output of the 3rd or door OR3; The source electrode of MOS transistor MP4 is connected with grid by the 5th switch S 5 or is disconnected, 5th switch S 5 is connected with the output of the 3rd or door OR3 by the 1st inverter INV1, and the 4th switch S 4 and the 5th switch S 5 are controlled by the VS4 signal exported by the 3rd or door OR3 jointly.
The quick-charging circuit that the embodiment of the present invention provides also comprises the first switch S 1, second switch S3 and the first operational amplifier IA, the first input end of the first operational amplifier IA is connected to one end of resistance Rprog, its second input connects the first switch S 1 and second switch S3, the output of the first operational amplifier IA is connected on the first branch road, makes the first operational amplifier IA form a negative feedback relation.First operational amplifier IA determines one of them switch connection in the first switch S 1 and second switch S3 or disconnection according to the comparative result of the 3rd comparator Com3.
The Proportionality design of the ratio of the wide length of MOS transistor MP1, MP3 and MP4 is 1:100:900 in the foregoing description, also can design 1:50:950.
The quickly charging battery road course of work shown in Fig. 2 is as follows:
Detecting unit 200 detects cell voltage VBAT value, when cell voltage VBAT is lower than the 3rd threshold voltage VPRE (such as 3V), 3rd comparator Com3 exports PRENB signal (low level), PRENB signal is after the second anti-phase INV2, export PREN signal (high level), now, switch S 3 conducting, switch S 1 turns off, the reference voltage of 0.1V is connected to the reverse input end of the first operational amplifier IA, the loop formed is controlled by the first operational amplifier IA, by PROG Voltage Cortrol to equaling 0.1V, circuit charges to battery with the pre-charge current of 100/RPROG.When cell voltage VBAT is greater than the 3rd threshold value VPRE, but when being less than first threshold voltage VREG, charging circuit is in constant current charge state, and circuit charges with the constant current charge current versus cell of 1000/RPROG.Control same as the prior art for above-mentioned precharge and constant current charge.After cell voltage VBAT is higher than first threshold voltage VREG, the current charging circuit that the embodiment of the present invention provides enters greatly/small area analysis and replaces charged state (and prior art is constant voltage charge state).When under constant current charge state, when there is cell voltage VBAT higher than first threshold voltage VREG, the VA signal that first comparator Com1 exports becomes high level from low level, produce a rising edge, d type flip flop FFDR1 is the d type flip flop that rising edge triggers, and d is held (i.e. vcc voltage: supply voltage.Represent high level) lock output QCP, namely QCP becomes high level.Sized by QCP, electric current replaces charged state id signal, and when it is high level, indication circuit enters greatly/small area analysis and replaces charged state.Pwm signal is an INVENTIONPeriodic digital signals, and such as its cycle is 50uS, and its duty ratio is 90%, and namely its high level time is 45uS, and its low level time is 5uS.When QCP is high level, QCPB is its inversion signal, and be low level, VS4 signal is identical with pwm signal, and when VS4 signal is high level, switch S 4 conducting in charging module 100, switch S 5 turns off.Therefore, large/under small area analysis replaces charged state, when PWM is high level, still maintains and charge with the current versus cell of 1000/RPROG (equaling the charging current under constant current charge state); When PWM is low level, only with the current versus cell charging of 100/RPROG (equaling 1/10th of charging current under constant current charge state).Its reason is, is the MPOS transistor MP1 electric current that 100, MPOS transistor MP2 copies 100 times by designing MPOS transistor MP2 with the ratio of the breadth length ratio of MPOS transistor MP1; Be the MPOS transistor MP1 electric current that 900, MPOS transistor MP2 copies 900 times by design MPOS transistor MP4 with the ratio of the breadth length ratio of MPOS transistor MP1.When PWM be low level and be in large/small area analysis replace under charged state time, MPOS transistor MP4 is turned off, and now, only MPOS transistor MP2 charges to battery.In Fig. 2, MP1, MP2, MP4 form current mirror, when they participate in work (when S4 conducting, their grid voltage is all equal, copy operational amplifier adjustment makes the drain voltage DMP1 of MP1 equal the drain voltage (VBAT) of MP2 and MP4 simultaneously, the source voltage of three is all equal (vcc voltage), and its current ratio equals the ratio of its breadth length ratio.
When circuit be in greatly/small area analysis replace charged state time, along with continuous charging, cell voltage VBAT continues to rise, when cell voltage VBAT rise to still to be greater than first threshold voltage VREG when pwm signal is the low level stage time, then show that battery is close to being full of, now, VA signal is high level, 4th inverter INV4 exports high level, the first signal VC then exported with door is high level, and the VB signal that the second comparator Com2 exports is low level, VRCG is again charge threshold (being generally about 100mV lower than VREG, such as 4.1V).When VC signal is high level, when VB signal is low level, the QEND signal that logical operation circuit 210 exports becomes high level, represents and enters charging done state.
Second comparator Com2 is used for comparing cell voltage VBAT and Second Threshold voltage VRCG (charge threshold again, such as 4.1V, generally be about 100mV lower than VREG), when causing cell voltage VBAT lower than Second Threshold voltage VRCG due to outside power consumption, VB signal becomes high level, d type flip flop FFDR1 is that high level resets, when VB is high level, QCP is reset to low level, QEND is also reset to low level simultaneously, thus make circuit exit charging done state, be in constant current charge state.
Fig. 3 describes the change in voltage of cell voltage VBAT and the change of charging current IBAT in the charging process of prior art.The T1 time period is pre-charge state, and the T2 time period is constant current charge state, and T3 is constant voltage charge state.
Fig. 4 describes the battery change in voltage of cell voltage VBAT and the change of charging current IBAT in charging process that provide according to the embodiment of the present invention.The T1 time period is pre-charge state, and the T2 time period is constant current charge state, and sized by T3, electric current replaces charged state.Large/under small area analysis replaces charged state, when big current is reduced to small area analysis, due to the existence of the internal resistance of cell, little during VBAT voltage ratio big current during small area analysis.When cell voltage VBAT when small area analysis is greater than the 3rd threshold voltage VREG, then battery charging terminates, and charging current is reduced to zero.In embodiments of the present invention, in the T3 time period, small area analysis value during low current charge can be set to 5% or 10% of constant current charge electric current.It should be noted that, do not occur zero charging current in the T3 time period, cause to avoid zero charging current stopping charging, cause lithium battery memory effect, reduce the problem of battery life.
The battery charger that the embodiment of the present invention provides, can shorten the time of battery needed for constant voltage charge process, thus accelerates battery charging.
Obviously, under the prerequisite not departing from true spirit of the present invention and scope, the present invention described here can have many changes.Therefore, all changes that it will be apparent to those skilled in the art that, all should be included within scope that these claims contain.The present invention's scope required for protection is only limited by described claims.
Claims (10)
1. a Quick charge circuit for battery, is characterized in that, comprising: charging module (100) and detection module (200),
Cell voltage (VBAT) compares with first threshold voltage (VREG) and the 3rd threshold voltage (VPRE) by described detection module (200) respectively, and described first threshold voltage (VREG) is greater than described 3rd threshold voltage (VPRE);
When described cell voltage (VBAT) is greater than described 3rd threshold voltage (VPRE) and is less than first threshold voltage (VREG), described detection module (200) exports the first comparative result, and described charging module (100) charges to described battery (BAT1) with the first current value according to described first comparative result;
When described cell voltage (VBAT) is greater than described first threshold voltage (VREG), described detection module (200) exports the second comparative result, and described charging module (100) alternately charges to described battery (BAT1) with different current value according to described second comparative result and cyclic pulse signal (PWM).
2. circuit according to claim 1, it is characterized in that: when described cell voltage (VBAT) is less than described 3rd threshold voltage (VPRE), export the 3rd comparative result, the first operational amplifier (IA) controls described charging module (100) according to described 3rd comparative result and charges to battery (BAT1) with the second current value; Described second current value is less than described first current value.
3. circuit according to claim 1, it is characterized in that: described detection module (200) comprises the first comparator (Com1) and the 3rd comparator (Com3), described first comparator (Com1) is compared with described first threshold voltage (VREG) cell voltage (VBAT), and described 3rd comparator (Com3) compares with the 3rd threshold voltage (VPRE) cell voltage (VBAT).
4. circuit according to claim 1, it is characterized in that: described charging module (100) comprises current mirror, described current mirror comprises the first branch road and at least one second branch road, described first branch road provides reference current, and described second branch road provides the charging current of charging to battery (BAT1).
5. circuit according to claim 4, it is characterized in that: also comprise the first switch (S1) and the first operational amplifier (IA), described charging module (100) also comprises resistance (Rprog), described resistance (Rprog) is connected on described first branch road, the first input end of described first operational amplifier (IA) is connected to one end of described resistance (Rprog), second input of described first operational amplifier (IA) is connected by described first switch (S1) by reference voltage, when the first comparative result connects described first switch (S1) effective time, the output of described first operational amplifier (IA) is connected on the first branch road, makes the first operational amplifier (IA) form a negative feedback relation.
6. circuit according to claim 4, it is characterized in that: described charging module (100) also comprises the 4th switch (S4) and the 5th switch (S5), at least one second branch road also comprises the 3rd branch road, described detection module (200) is gating cyclic pulse signal (PWM) signal when the second comparative result is effective, described cyclic pulse signal (PWM) controls described 4th switch (S4) and the 5th switch (S5), makes described 3rd branch road alternately access current mirror and disconnect from current mirror.
7. circuit according to claim 3, it is characterized in that, described detection module (200) also comprises d type flip flop (FFDR1),
Described d type flip flop (FFDR1) is connected with the output of described first comparator (Com1), described detection module (200) exports charging signals (VS4) according to the output signal of described d type flip flop (FFDR1) and cyclic pulse signal (PWM), and described charging signals (VS4) alternately charges to described battery (BAT1) with different current value for controlling described charging module (100).
8. the circuit according to claim 3 or 7, is characterized in that, described detection module (200) also comprises arithmetic logic unit (210) and the second comparator (Com2),
Described arithmetic logic unit (210) is connected with the output of described first comparator (Com1) and the output of described second comparator (Com2), and described arithmetic logic unit (210) exports battery complete charge signal (QEND) according to the comparative result of described first comparator (Com1) and described second comparator (Com2) and cyclic pulse signal (PWM).
9. circuit according to claim 4, it is characterized in that: described first branch road comprises the first MOS transistor (MP1) and the 3rd MOS transistor (MP3), described second branch road comprises the second MOS transistor (MP2), the drain electrode of described first MOS transistor (MP1) is connected the first input end of the second operational amplifier (MA) with the source electrode of described 3rd MOS transistor (MP3), the drain electrode of described second MOS transistor (MP2) connects the second input of described second operational amplifier (MA), the output of described second operational amplifier (MA) is connected with the grid of described 3rd MOS transistor (MP3), described second operational amplifier (MA) is equal for the drain voltage of the drain voltage and described second MOS transistor (MP2) that adjust described first MOS transistor (MP1).
10. circuit according to claim 1, it is characterized in that: described circuit also comprises the first switch (S1) and the first operational amplifier (IA), described charging module (100) also comprises resistance (Rprog), described charging module (100) comprises current mirror, described current mirror comprises the first branch road, second branch road and the 3rd branch road, described first branch road utilizes the first operational amplifier (IA) to produce reference current, described second branch road and described 3rd branch road copy described reference current, and it is common or separately described battery (BAT1) is charged,
Described resistance (Rprog) is connected on described first branch road, the first input end of described first operational amplifier (IA) is connected to one end of described resistance (Rprog), second input of described first operational amplifier (IA) is connected, when the first comparative result connects described first switch (S1) effective time by described first switch (S1) by reference voltage; The output of described first operational amplifier (IA) is connected on the first branch road, makes the first operational amplifier (IA) form a negative feedback relation;
Described detection module (200) comprises the first comparator (Com1) and the 3rd comparator (Com3), described 3rd comparator (Com3) is for comparing described cell voltage (VBAT) and described 3rd threshold voltage (VPRE), and exporting described first comparative result, described first switch (S1) is controlled by described first comparative result; Described first comparator (Com1) compares described cell voltage (VBAT) and first threshold voltage (VREG), and exporting the second comparative result, described current mirror alternately charges to described battery (BAT1) with different current value according to described second comparative result.
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| CN103532201B true CN103532201B (en) | 2015-06-24 |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104410116A (en) * | 2014-11-18 | 2015-03-11 | 深圳市中兴移动通信有限公司 | Quick charging device and quick charging method |
| CN106549641B (en) * | 2015-09-16 | 2021-07-06 | 中兴通讯股份有限公司 | Protective circuit |
| CN205123326U (en) * | 2015-10-27 | 2016-03-30 | 无锡中感微电子股份有限公司 | Quick charging circuit |
| CN105244970B (en) * | 2015-11-06 | 2017-08-29 | 无锡中感微电子股份有限公司 | Charging circuit |
| CN105207323B (en) * | 2015-11-12 | 2018-05-08 | 无锡中感微电子股份有限公司 | Charger with thermal conditioning circuit |
| CN106208204A (en) * | 2016-07-29 | 2016-12-07 | 深圳市金立通信设备有限公司 | A kind of method for charging batteries and terminal |
| CN106253405A (en) * | 2016-08-30 | 2016-12-21 | 深圳市金立通信设备有限公司 | A kind of charging method and terminal |
| CN106602159B (en) * | 2016-12-02 | 2019-12-17 | 奇酷互联网络科技（深圳）有限公司 | Charging method and charging device |
| CN108462230B (en) * | 2018-03-21 | 2024-04-19 | 嘉兴飞童电子科技有限公司 | Lithium battery charging management circuit and management method |
| CN111245050B (en) * | 2020-01-17 | 2021-08-31 | 深圳市微源半导体股份有限公司 | Novel automatic charging control circuit |
| CN115765120B (en) * | 2023-01-10 | 2023-07-07 | 禹创半导体(深圳)有限公司 | Charging device |
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Address after: A 530 building 214135 Jiangsu Province, Wuxi city Wuxi District Taihu international science and Technology Park Qingyuan Road 10 Patentee after: WUXI ZHONGGAN MICROELECTRONIC CO., LTD. Address before: A 530 building 214135 Jiangsu Province, Wuxi city Wuxi District Taihu international science and Technology Park Qingyuan Road 10 Patentee before: Wuxi Vimicro Co., Ltd. |