CN103531627A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN103531627A CN103531627A CN201210232193.4A CN201210232193A CN103531627A CN 103531627 A CN103531627 A CN 103531627A CN 201210232193 A CN201210232193 A CN 201210232193A CN 103531627 A CN103531627 A CN 103531627A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 112
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 60
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 25
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 16
- 238000001312 dry etching Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 230000035755 proliferation Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
Abstract
The invention discloses a semiconductor device and a manufacturing method thereof. After a groove is formed through etching a semiconductor substrate in a source/drain electrode area, a backing layer is formed through use of chemical vapor deposition and etched so as to form diffusion impervious layers, which are identical with the semiconductor substrate in conduction type and have a higher impurity concentration than the semiconductor substrate, at the two side walls of the groove and source/drain electrode areas, which have an opposite conduction type with the diffusion impervious layers, are continued to be formed at the internal and external edges of the groove. Therefore, because the diffusion impervious layers which have the opposite conduction type with the source/drain electrode areas are arranged between the source/drain electrode areas and impurities which diffuse from the source/drain electrode areas to a channel region transversely are neutralized so that increase of thicknesses of grid side walls is not required and the volume of the whole device is reduced and a serial-connection resistance between source/drain electrodes is reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of semiconductor device and manufacture method thereof.
Background technology
Field-effect transistor (FET) is for manufacturing the leading semiconductor device of the products such as dedicated IC chip, static random access memory (SRAM) always.Miniaturization increasingly along with semiconductor device, FET short-channel effect is more serious, be subject to the impact of short-channel effect, in raceway groove, any slight impurity changes and all can cause that migration appears in the threshold voltage (Vt) of FET, one of reason that occurs impurity variation in raceway groove is because Implantation forms behind source/drain region, the impurity horizontal proliferation of source/drain region, to the channel region of FET, is the migration that causes FET threshold voltage, and then affects the performance of FET.
In existing FET manufacturing process, source/drain region is generally after forming grid curb wall, usings the offset side wall (offset spacer) of grid and both sides and grid curb wall semiconductor base is carried out to Implantation to form as shielding.Based on this, the channel region for fear of the impurity horizontal proliferation of source/drain region to FET, available technology adopting increases gate lateral wall thickness, so that the source area that Implantation forms and the distance between drain region increase.But owing to having increased the thickness of gate lateral wall, make the volume of whole FET become large, and due to the distance having zoomed out between source area and drain region, the series resistance between source-drain electrode also can increase, and then affect the performance of device.
Summary of the invention
In view of this, the invention provides a kind of semiconductor device and manufacture method thereof, with the impurity horizontal proliferation avoiding source/drain region, in channel region, reduce the volume of device, and reduce the series resistance between source-drain electrode.
The technology used in the present invention means are as follows: a kind of manufacture method of semiconductor device, comprising:
The semiconductor structure of source/drain region to be formed is provided, described semiconductor structure comprises that predefine has the semiconductor base of position, described source/drain region, and be formed on the gate stack on described semiconductor base, and described semiconductor base has the impurity of the first conduction type;
Utilization is dry-etched in the position etching semiconductor substrate of described predefined source/drain region to form groove;
Utilize and select chemical vapour deposition (CVD) at described groove inner surface, to form the laying with the first conductive type impurity, the concentration of the first conductive type impurity described in described laying is higher than the concentration of the first conductive type impurity in described semiconductor base;
Laying described in dry etching, removes the laying of described bottom portion of groove, with the sidewall at described groove, forms diffusion impervious layer;
Utilize chemical vapour deposition (CVD) in described groove, to fill the semiconductor layer doped with the second conductive type impurity, and using described semiconductor layer as source/drain region.
Further, provide the semiconductor structure of source/drain region to be formed to comprise:
The semiconductor base with the first conductive type impurity is provided, and described semiconductor base predefine has gate location and position, source/drain region;
On described semiconductor base, form successively insulating barrier, polysilicon layer and hard mask layer;
On described hard mask layer, form the patterning photoresist layer that only covers described predefined gate location, and with hard mask layer described in described patterning photoresist layer etching pattern;
Using the described hard mask layer of patterning as shielding, and polysilicon layer and insulating barrier described in etching form gate insulation layer and grid on described semiconductor base successively;
At described semiconductor base surface deposition first medium layer, and first medium layer described in dry etching, to form skew sidewall at described gate insulation layer and grid both sides;
The described grid of usining carries out Implantation as shielding to described semiconductor base with skew sidewall, forms lightly-doped source/drain region;
At described semiconductor base surface deposition second medium layer, and second medium layer described in dry etching, to form gate lateral wall in described skew sidewall surfaces.
Further, described the first conduction type is P-type conduction, and described the second conduction type is N-type conduction, and described the first conductive type impurity is one or both and the above combination in boron, indium or titanium; Or,
Described the first conduction type is N-type conduction, and described the second conduction type is P-type conduction, and described the first conductive type impurity is phosphorus or arsenic, or is the two combination.
The present invention also provides a kind of semiconductor device, comprise: the semiconductor base that comprises the first conductive type impurity and the gate stack forming on described semiconductor base, it is characterized in that, in the semiconductor base of described gate stack both sides, be formed with the source/drain region with the second conductive type impurity, and the both sides of source/drain region are formed with diffusion impervious layer described in each; Described diffusion impervious layer has the first conductive type impurity and impurity concentration higher than the first conductive type impurity concentration of described semiconductor base.
Further, described gate stack comprises the gate dielectric layer that is formed on semiconductor base, is positioned at grid on described gate dielectric layer, is positioned at the skew sidewall of described gate dielectric layer and grid both sides and the gate lateral wall that is positioned at described skew sidewall surfaces;
Described semiconductor base also comprises the lightly-doped source/drain region that is arranged in grid both sides, skew sidewall and the substrate of gate lateral wall base semiconductor.
Further, described the first conduction type is P-type conduction, and described the second conduction type is N-type conduction, and described the first conductive type impurity is one or both and the above combination in boron, indium or titanium; Or,
Described the first conduction type is N-type conduction, and described the second conduction type is P-type conduction, and described the first conductive type impurity is phosphorus or arsenic, or is the two combination.
Adopt semiconductor device provided by the invention and manufacture method thereof, by forming after groove in the etching semiconductor substrate of source/drain region, utilize and select chemical vapour deposition (CVD) to form laying etching, identical with semiconductor base to form conduction type at place, groove two side, and impurity concentration is higher than the diffusion impervious layer of semiconductor base, and continuation extension in groove forms and the source/drain region of described diffusion impervious layer conductivity type opposite, therefore, due to the diffusion impervious layer being provided with between source/drain region with source/drain region conductivity type opposite, neutralized the impurity to channel region horizontal proliferation by source/drain region, thereby without the thickness that increases gate lateral wall, reduced the volume of whole device, and reduced the series resistance between source-drain electrode.
Accompanying drawing explanation
Fig. 1 is the manufacture method flow chart of a kind of semiconductor device of the present invention;
Fig. 2 a ~ Fig. 2 e is the flowage structure figure of a kind of method, semi-conductor device manufacturing method exemplary embodiments of the present invention.
Embodiment
Below in conjunction with accompanying drawing, principle of the present invention and feature are described, example, only for explaining the present invention, is not intended to limit scope of the present invention.
As shown in Figure 1, the invention provides a kind of manufacture method of semiconductor device, comprise the steps:
The semiconductor structure of source/drain region to be formed is provided, described semiconductor structure comprises that predefine has the semiconductor base of position, described source/drain region, and be formed on the gate stack on described semiconductor base, and described semiconductor base has the impurity of the first conduction type;
Utilization is dry-etched in the position etching semiconductor substrate of described predefined source/drain region to form groove;
Utilize and select chemical vapour deposition (CVD) at described groove inner surface, to form the laying with the first conductive type impurity, the concentration of the first conductive type impurity described in described laying is higher than the concentration of the first conductive type impurity in described semiconductor base;
Laying described in dry etching, removes the laying of described bottom portion of groove, with the sidewall at described groove, forms diffusion impervious layer;
Utilize chemical vapour deposition (CVD) in described groove, to fill the semiconductor layer doped with the second conductive type impurity, and using described semiconductor layer as source/drain region.
In order further to elaborate feature of the present invention, as the exemplary embodiments of a kind of method, semi-conductor device manufacturing method of the present invention, below in conjunction with accompanying drawing, 2a ~ 2e is elaborated.
With reference to Fig. 2 a, in the present embodiment, first utilize prior art to manufacture the semiconductor structure of source/drain region to be formed, step comprises:
The semiconductor base 10 with the first conductive type impurity is provided, and semiconductor base 10 predefines have gate location and position, source/drain region;
On semiconductor base 10, form successively insulating barrier 11, polysilicon layer 12 and hard mask layer 13, wherein insulating barrier 11 can be silica, silicon oxynitride etc., and hard mask layer 13 is preferably silicon nitride;
On hard mask layer 13, form the patterning photoresist layer (not shown) that only covers predefined gate location, and still with former mark, mark in order to embody the continuity of technique with patterning photoresist layer etching pattern hard mask layer 13(, other structures are in like manner);
Using patterning hard mask layer 13 as shielding, etch polysilicon layer 12 and insulating barrier 11 form gate insulation layer 11 and grid 12 on semiconductor base 10 successively;
At semiconductor base 10 surface deposition first medium layers 14, and dry etching first medium layer 14, to form skew sidewall 14 at gate insulation layer 11 and grid 12 both sides, wherein the material of first medium layer 14 can be silica, silicon oxynitride etc.;
The grid 12 of usining carries out Implantation as shielding to semiconductor base 10 with skew sidewall 14, forms lightly-doped source/drain region 16;
At semiconductor base 10 surface deposition second medium layers 15, and dry etching second medium layer 15, to form gate lateral wall 15 on skew sidewall 14 surfaces, wherein, gate lateral wall 15 is preferably silicon nitride, is to have formed a gate stack with gate dielectric layer 11, grid 12, skew sidewall 14 and gate lateral wall 15;
As shown in Figure 2 b, after the structure in obtaining Fig. 2 a, using gate stack as shielding, utilize and be dry-etched in predefined source/drain region position etching semiconductor substrate 10 to form groove 17;
With reference to Fig. 2 c, utilize and select chemical vapour deposition (CVD) to form the laying 18 with the first conductive type impurity at groove 17 inner surfaces, in laying 18, the concentration of the first conductive type impurity is higher than the concentration of the first conductive type impurity in semiconductor base 10;
As shown in Figure 2 d, dry etching laying 18, removes the laying of groove 17 bottoms, with the sidewall at groove 17, forms diffusion impervious layer 18 ';
As shown in Figure 2 e, utilize chemical vapour deposition (CVD) in the interior filling of groove 17 semiconductor layer 19 doped with the second conductive type impurity, and using semiconductor layer 19 as source/drain region 19.
Therefore, adopt method, semi-conductor device manufacturing method provided by the invention, by forming after groove in the etching semiconductor substrate of source/drain region, utilize and select chemical vapour deposition (CVD) to form laying etching, identical with semiconductor base to form conduction type at place, groove two side, and impurity concentration is higher than the diffusion impervious layer of semiconductor base, and continuation extension in groove forms and the source/drain region of described diffusion impervious layer conductivity type opposite, therefore, due to the diffusion impervious layer being provided with between source/drain region with source/drain region conductivity type opposite, neutralized the impurity to channel region horizontal proliferation by source/drain region, thereby without the thickness that increases gate lateral wall, reduced the volume of whole device, and reduced the series resistance between source-drain electrode.
The present invention also provides a kind of semiconductor device, shown in Fig. 2 e, comprises a kind of semiconductor device, comprising: the semiconductor base 10 that comprises the first conductive type impurity and the gate stack forming on semiconductor base 10;
Wherein, gate stack comprises the gate dielectric layer 11 that is formed on semiconductor base 10, is positioned at the grid 12 on gate dielectric layer 11, the gate lateral wall 15 that is positioned at the skew sidewall 14 of gate dielectric layer 11 and grid 12 both sides and is positioned at skew sidewall 14 surfaces;
In the semiconductor base 10 of gate stack both sides, be formed with the source/drain region 19 with the second conductive type impurity, and be formed with diffusion impervious layer 18 ' in the both sides of each source/drain region 19; Diffusion impervious layer 18 ' has the first conductive type impurity and impurity concentration higher than the first conductive type impurity concentration of semiconductor base 10.
It should be noted that, in above-mentioned semiconductor device and manufacture method thereof, when the first conduction type is P-type conduction, when the second conduction type is N-type conduction, as when semiconductor device is nmos pass transistor, the first conductive type impurity is one or both and the above combination in boron, indium or titanium;
When the first conduction type is N-type conduction, the second conduction type is P-type conduction, if the first conductive type impurity as described in when semiconductor device is PMOS transistor is phosphorus or arsenic, or is the two combination.
Further, for etching in method, select the selection of material that chemical vapour deposition (CVD), chemical vapour deposition (CVD), impurity, impurity concentration etc. are concrete, numerical value, technological parameter, those skilled in the art can be according to factors such as the concrete semiconductor device type (as NMOS or PMOS) of making, sizes, according to prior art and common practise, selecting applicable material and technological parameter, is not limit at this.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (6)
1. a manufacture method for semiconductor device, comprising:
The semiconductor structure of source/drain region to be formed is provided, described semiconductor structure comprises that predefine has the semiconductor base of position, described source/drain region, and be formed on the gate stack on described semiconductor base, and described semiconductor base has the impurity of the first conduction type;
Utilization is dry-etched in the position etching semiconductor substrate of described predefined source/drain region to form groove;
Utilize and select chemical vapour deposition (CVD) at described groove inner surface, to form the laying with the first conductive type impurity, the concentration of the first conductive type impurity described in described laying is higher than the concentration of the first conductive type impurity in described semiconductor base;
Laying described in dry etching, removes the laying of described bottom portion of groove, with the sidewall at described groove, forms diffusion impervious layer;
Utilize chemical vapour deposition (CVD) in described groove, to fill the semiconductor layer doped with the second conductive type impurity, and using described semiconductor layer as source/drain region.
2. method according to claim 1, is characterized in that, provides the semiconductor structure of source/drain region to be formed to comprise:
The semiconductor base with the first conductive type impurity is provided, and described semiconductor base predefine has gate location and position, source/drain region;
On described semiconductor base, form successively insulating barrier, polysilicon layer and hard mask layer;
On described hard mask layer, form the patterning photoresist layer that only covers described predefined gate location, and with hard mask layer described in described patterning photoresist layer etching pattern;
Using the described hard mask layer of patterning as shielding, and polysilicon layer and insulating barrier described in etching form gate insulation layer and grid on described semiconductor base successively;
At described semiconductor base surface deposition first medium layer, and first medium layer described in dry etching, to form skew sidewall at described gate insulation layer and grid both sides;
The described grid of usining carries out Implantation as shielding to described semiconductor base with skew sidewall, forms lightly-doped source/drain region;
At described semiconductor base surface deposition second medium layer, and second medium layer described in dry etching, to form gate lateral wall in described skew sidewall surfaces.
3. method according to claim 1 and 2, is characterized in that, described the first conduction type is P-type conduction, and described the second conduction type is N-type conduction, and described the first conductive type impurity is one or both and the above combination in boron, indium or titanium; Or,
Described the first conduction type is N-type conduction, and described the second conduction type is P-type conduction, and described the first conductive type impurity is phosphorus or arsenic, or is the two combination.
4. a semiconductor device, comprise: the semiconductor base that comprises the first conductive type impurity and the gate stack forming on described semiconductor base, it is characterized in that, in the semiconductor base of described gate stack both sides, be formed with the source/drain region with the second conductive type impurity, and the both sides of source/drain region are formed with diffusion impervious layer described in each; Described diffusion impervious layer has the first conductive type impurity and impurity concentration higher than the first conductive type impurity concentration of described semiconductor base.
5. semiconductor device according to claim 4, it is characterized in that, described gate stack comprises the gate dielectric layer that is formed on semiconductor base, be positioned at grid on described gate dielectric layer, be positioned at the skew sidewall of described gate dielectric layer and grid both sides and the gate lateral wall that is positioned at described skew sidewall surfaces;
Described semiconductor base also comprises the lightly-doped source/drain region that is arranged in grid both sides, skew sidewall and the substrate of gate lateral wall base semiconductor.
6. according to the semiconductor device described in claim 3 or 4, it is characterized in that, described the first conduction type is P-type conduction, and described the second conduction type is N-type conduction, and described the first conductive type impurity is one or both and the above combination in boron, indium or titanium; Or,
Described the first conduction type is N-type conduction, and described the second conduction type is P-type conduction, and described the first conductive type impurity is phosphorus or arsenic, or is the two combination.
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| CN201210232193.4A CN103531627B (en) | 2012-07-05 | 2012-07-05 | Semiconductor device and manufacture method thereof |
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| CN201210232193.4A CN103531627B (en) | 2012-07-05 | 2012-07-05 | Semiconductor device and manufacture method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110047908A (en) * | 2018-01-16 | 2019-07-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and its manufacturing method |
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| US20070155142A1 (en) * | 2005-12-30 | 2007-07-05 | Been-Yih Jin | Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers |
| US20070235802A1 (en) * | 2006-04-05 | 2007-10-11 | Chartered Semiconductor Manufacturing Ltd | Method to control source/drain stressor profiles for stress engineering |
| CN101572269A (en) * | 2008-04-30 | 2009-11-04 | 台湾积体电路制造股份有限公司 | Source/drain carbon implant and rta anneal, pre-sige deposition |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070155142A1 (en) * | 2005-12-30 | 2007-07-05 | Been-Yih Jin | Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers |
| US20070235802A1 (en) * | 2006-04-05 | 2007-10-11 | Chartered Semiconductor Manufacturing Ltd | Method to control source/drain stressor profiles for stress engineering |
| CN101572269A (en) * | 2008-04-30 | 2009-11-04 | 台湾积体电路制造股份有限公司 | Source/drain carbon implant and rta anneal, pre-sige deposition |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110047908A (en) * | 2018-01-16 | 2019-07-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and its manufacturing method |
| CN110047908B (en) * | 2018-01-16 | 2023-02-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for manufacturing the same |
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