CN103531484A - Manufacturing method for chip-bearing substrate structure - Google Patents
Manufacturing method for chip-bearing substrate structure Download PDFInfo
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- CN103531484A CN103531484A CN201210233005.XA CN201210233005A CN103531484A CN 103531484 A CN103531484 A CN 103531484A CN 201210233005 A CN201210233005 A CN 201210233005A CN 103531484 A CN103531484 A CN 103531484A
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- Prior art keywords
- layer
- projection cube
- cube structure
- insulation material
- metallic substrate
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- 239000000758 substrate Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 35
- 238000003825 pressing Methods 0.000 claims abstract description 22
- 239000012774 insulation material Substances 0.000 claims description 50
- 230000004888 barrier function Effects 0.000 claims description 30
- 238000013461 design Methods 0.000 claims description 19
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 18
- 238000003466 welding Methods 0.000 claims description 18
- 229910052799 carbon Inorganic materials 0.000 claims description 11
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 10
- 239000004744 fabric Substances 0.000 claims description 10
- 239000000835 fiber Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 8
- 230000001680 brushing effect Effects 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000012546 transfer Methods 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 239000003365 glass fiber Substances 0.000 claims description 2
- 229910000765 intermetallic Inorganic materials 0.000 claims description 2
- 239000012528 membrane Substances 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 229910052718 tin Inorganic materials 0.000 claims description 2
- 239000011135 tin Substances 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract 7
- 239000002184 metal Substances 0.000 abstract 1
- 239000002365 multiple layer Substances 0.000 abstract 1
- 230000032798 delamination Effects 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- -1 after pressing Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention provides a manufacturing method for a chip-bearing substrate structure. The chip-bearing substrate structure includes a metal-substrate-structure manufacturing step, a photoresist-pattern-layer forming step, an etching step, a photoresist-pattern-layer removing step, an insulating-material-layer pressing step, a rubbing step, a circuit-layer manufacturing step and a soldermask-layer manufacturing step. The metal-substrate-structure manufacturing step is to manufacture a multiple-layer structure in which two metal substrate layers are provided with a block layer. In the etching step, an etching depth can be controlled effectively so that each position and each paddle structure formed at each time are identical in shape and depth and the substrate structure can be applied in a mass production process and problems, which exist in the prior art, of skewing, incapability of keeping the position fixed and fall-off, which are resulted from different depths, are solved effectively.
Description
Technical field
The present invention relates to a kind of manufacture method of chip bearing board structure, is mainly to utilize in substrate to increase barrier layer, to maintain the making constancy of projection (Paddle) structure, and makes chip bearing substrate be difficult for occurring delamination problems.
Background technology
With reference to Figure 1A and Figure 1B, be respectively the generalized section of prior art chip bearing board structure the first example and the second example.As shown in Figure 1A, prior art chip bearing board structure 100 comprises a metallic substrate layer 10, is formed on projection cube structure (paddle) 15, insulation material layer 30, line layer 40 and welding resisting layer 60 in metallic substrate layer 10, insulation material layer 30 is inserted the space between projection cube structure 15 and metallic substrate layer 10, but a plane of projection cube structure 15 is exposed from insulation material layer 30, and forms a coplanar flat.Line layer 40 is formed on this coplanar flat, be connected, and welding resisting layer 60 is formed on insulation material layer 30 and line layer 40 with projection cube structure 15, and covered section line layer 40, in order to avoid when forming weld pad (not shown), cause short circuit.
As shown in Figure 1B, prior art chip bearing board structure 150, in the structure of the first example as variation, in insulation material layer 30, to imbed carbon fibre initial rinse fabric 50 and conductive layer 55 formed thereon, circuit laminar is formed in a coplanar flat of projection cube structure 15, insulation material layer 30 and conductive layer 55, is connected with this projection cube structure 15 and this conductive layer 50.
The shortcoming of existing chip bearing plate structure is, projection cube structure 15 is normally with etching mode, directly from line layer 40, produce, owing to being all same material, the etched degree of depth is difficult for, the shape of projection cube structure 15 when volume production is, the degree of depth of vacancy is difficult to maintain certain, no matter this makes is that follow-up insulation material layer 30 is difficult to maintain flat surfaces, the position of carbon fibre initial rinse fabric 50 and conductive layer 55 formed thereon is also difficult to constant, easily there is the phenomenon of delamination in this chip bearing substrate when being subject to external force, makes yield be difficult to promote.
Summary of the invention
Main purpose of the present invention is to provide a kind of manufacture method of chip bearing board structure, the method comprises: a metallic substrates structure fabrication step, comprise a coating step and a pair of pressure step, this coating step is in a metallic substrate layer, to plate a barrier layer, this is by the pressing on this barrier layer of another metallic substrate layer to pressing step, and forms a multilayer structure; One photoresist design layer forms step, in this metallic substrate layer on upper strata, produces a photoresist design layer; One etching step, carries out etching with an etching solution, and the part that this metallic substrate layer on upper strata is not covered by this photoresist design layer is removed, and this metallic substrate layer on upper strata is formed to a projection cube structure, and wherein this etching solution does not react with this barrier layer; One photoresist design layer is removed step, and this photoresist design layer is removed; One insulation material layer pressing step, is pressure bonded to an insulation material layer on this projection cube structure, and this insulation material layer fills up the space between this barrier layer and this projection cube structure; One brushing step, the upper surface leveling by this insulation material layer, reveals the upper surface of this projection cube structure simultaneously, and makes the upper surface of this projection cube structure and this insulation material layer form a coplanar flat; One line layer making step, the mode with image transfer in this coplanar flat forms a line layer, this insulation material layer of this line layer cover part and the upper surface of this projection cube structure, and be connected with this projection cube structure; And a welding resisting layer making step, be in this coplanar flat, to form a welding resisting layer, this welding resisting layer is not covered this insulation material layer and this projection cube structure part by this line layer covers, and the line layer of part is covered.
Feature of the present invention is mainly to utilize barrier layer to control the etched degree of depth, and can control accurately wet etching, make each projection cube structure of same substrate, and shape and the degree of depth of each projection cube structure forming are in the same manner all identical, and can be widely used in the processing procedure of volume production, and effectively solve prior art because the degree of depth is not identical, the skew causing, position cannot be constant and the problem of delamination.
Accompanying drawing explanation
Figure 1A is the generalized section of prior art chip bearing board structure the first example;
Figure 1B is the generalized section of prior art chip bearing board structure the first example;
Fig. 2 is the flow chart of the manufacture method of chip bearing board structure of the present invention; And
Fig. 3 A to Fig. 3 I, Fig. 4 A and Fig. 4 B and Fig. 5 A to Fig. 5 C are the progressively generalized sections of the manufacture method of chip bearing board structure of the present invention.
Primary clustering symbol description
10 metallic substrate layer
11 metallic substrate layer
13 projection cube structures
15 projection cube structures
20 barrier layers
22 barrier layers
30 insulation material layers
40 line layers
50 carbon fibre initial rinse fabrics
55 conductive layers
60 welding resisting layers
100 chip bearing board structures
150 chip bearing board structures
200 photoresist design layers
The manufacture method of S1 chip bearing board structure
S10, S11, S13, S20, S30, S35, S40, S50, S60, S70, S80 step
Embodiment
Those skilled in the art below coordinate graphic and element numbers to do more detailed description to embodiments of the present invention, so that can implement according to this after studying this specification carefully.
With reference to figure 2, Fig. 3 A to Fig. 3 I, Fig. 4 A and Fig. 4 B, and Fig. 5 A to Fig. 5 C, be respectively the flow chart of the manufacture method of chip bearing board structure of the present invention, and the progressively generalized section of the manufacture method of chip bearing board structure of the present invention.As shown in Figure 2, the manufacture method S1 of chip bearing board structure of the present invention comprises a metallic substrates structure fabrication step S10, photoresist design layer forms step S20, etching step S30, photoresist design layer removal step S40, insulation material layer pressing step S50, brushing step S60, line layer making step S70 and welding resisting layer making step S80.
Simultaneously with reference to Fig. 2, Fig. 3 A and Fig. 3 B, metallic substrates structure fabrication step S10 comprises coating step S11 and to pressing step S13.Coating step S11 plates a barrier layer 20 in a metallic substrate layer 11, is by the pressing on this barrier layer 20 of another metallic substrate layer 11, and forms a multilayer structure to pressing step S13.As shown in Figure 3 C, photoresist design layer forms step S20 and produces photoresist design layer 200 in the metallic substrate layer 11 on upper strata, as shown in Figure 3 D, etching step S30 carries out etching with etching solution, the part that the metallic substrate layer on upper strata 11 is not covered by photoresist design layer 200 is removed, characteristic due to wet etching, the metallic substrate layer on upper strata 11 can be formed to projection cube structure (paddle) 13, because etching solution does not react with this barrier layer 20, therefore, etching step S30 arrives this just termination of barrier layer 20, then as shown in Fig. 3 E, photoresist design layer is removed step S40 the photoresist design layer on projection cube structure 13 200 is removed.
As shown in Fig. 3 F, insulation material layer pressing step S50 is pressure bonded to insulation material layer 30 on projection cube structure 13, and makes insulation material layer 30 fill up the space between barrier layer 20 and projection cube structure 13.As shown in Fig. 3 G, brushing step S60 is by the upper surface leveling of insulation material layer 30, the upper surface of projection cube structure 13 is revealed simultaneously, and makes projection cube structure 13 and the upper surface of this insulation material layer 30 form a coplanar flat.As shown in Fig. 3 H, line layer making step S70 is that the mode with image transfer forms a line layer 40 in this coplanar flat, the insulation material layer 30 of these line layer 40 cover parts and projection cube structure 13, and be connected with this projection cube structure 13.As shown in Fig. 3 I, welding resisting layer making step S80, in this coplanar flat, to form a welding resisting layer 60, this welding resisting layer 60 is not covered insulation material layer 30 and projection cube structure 13 part by line layer 40, and the line layer 40 of part covers, when preventing that rear time weld pad (not shown) from forming, produce the problem of short circuit.
Further, as shown in Fig. 3 and Fig. 4 A, can be after etching step S30, carry out one second etching step S35, the second etching step S35 is that the part of barrier layer 20 not being covered by projection cube structure 13 with one second etching solution is removed, and barrier layer 22, the second etching solutions that form as shown in Figure 4 A do not react with metallic substrate layer 11 and projection cube structure 13 generations, therefore, the second etching step S35 just stops in the metallic substrate layer 11 that arrives lower floor.And formation structure as shown in Figure 4 A.Then, sequentially carry out as described above photoresist design layer and remove step S40, insulation material layer pressing step S50, brushing step S60, line layer making step S70 and welding resisting layer making step S80, and form structure as shown in Figure 4 B, wherein insulation material layer 30 fills up the space between barrier layer 22 and metallic substrate layer 11 and projection cube structure 13.
Further, as shown in Figure 5A, in insulation material layer pressing step S50, by insulation material layer pressing step S50, be when insulation material layer 30 is pressure bonded to projection cube structure 13, at least one carbon fibre initial rinse fabric 50 of pressing simultaneously, and be arranged at least one conductive layer 55 on carbon fibre initial rinse fabric, after pressing, insulation material layer 30 fills up the space between barrier layer 20 and projection cube structure 13, thereby make at least one carbon fibre initial rinse fabric 50, and at least one conductive layer 55 edges that are arranged on carbon fibre initial rinse fabric are embedded among insulation material layer 30.
Then, sequentially carry out brushing step S60, this at least one conductive layer 55 and this projection cube structure 13 are exposed, and make surface co-planar on this insulation material layer 30, this at least one conductive layer 55 and this projection cube structure 13, and form a coplanar flat.Then carry out line layer making step S70, and formation structure as shown in Figure 5 B, wherein line layer 40 is formed in a coplanar flat of surface co-planar on projection cube structure 13, this at least one conductive layer 55 and this insulation material layer 30, the projection cube structure 13 of cover part, this at least one conductive layer 55 and this insulation material layer 30.Finally carry out welding resisting layer making step, the part that these welding resisting layer 60 covering insulating material layers 30, projection cube structure 13 and conductive layer 55 are not covered by line layer 40, and the line layer 40 of part.Further, if this mode, through the second etching step S35, forms structure as shown in Figure 5 C.
Wherein the material of metallic substrate layer 11, projection cube structure 13, line layer 40 and conductive layer 55 be copper, aluminium at least one of them, and the material of barrier layer 20 be tin, nickel, titanium, palladium at least one of them, further comprise Jie's metallic compound forming with the material of metallic substrate layer 11, and the scope of barrier layer thickness is 3 μ m～10 μ m.Insulation material layer 30 is BT resin, glass fibre, ABF (Ajinomoto Build-Up Film) glued membrane etc.
Feature of the present invention is mainly to utilize barrier layer to control the etched degree of depth, and can control accurately wet etching, shape and the degree of depth of the projection cube structure that makes each position male block structure and hold with the same terms shape are each time all identical, and can be widely used in the processing procedure of volume production, and effectively solve prior art because the degree of depth is not identical, the skew causing, position cannot be constant and the problem of delamination.
As described above is only in order to explain preferred embodiment of the present invention; not attempt is done any pro forma restriction to the present invention according to this; therefore, all have under identical invention spirit, do relevant any modification of the present invention or change, all must be included in the category that the invention is intended to protection.
Claims (6)
1. a manufacture method for chip bearing board structure, is characterized in that, comprises:
One metallic substrates structure fabrication step, comprises a coating step and a pair of pressure step, and this coating step is in a metallic substrate layer, to plate a barrier layer, and this is by the pressing on this barrier layer of another metallic substrate layer to pressing step, and forms a multilayer structure;
One photoresist design layer forms step, in this metallic substrate layer on upper strata, produces a photoresist design layer;
One etching step, carries out etching with an etching solution, and the part that this metallic substrate layer on upper strata is not covered by this photoresist design layer is removed, and this metallic substrate layer on upper strata is formed to a projection cube structure, and wherein this etching solution does not react with this barrier layer;
One photoresist design layer is removed step, and this photoresist design layer is removed;
One insulation material layer pressing step, is pressure bonded to an insulation material layer on this projection cube structure, and this insulation material layer fills up the space between this barrier layer and this projection cube structure;
One brushing step, the upper surface leveling by this insulation material layer, reveals the upper surface of this projection cube structure simultaneously, and makes the upper surface of this projection cube structure and this insulation material layer form a coplanar flat;
One line layer making step, the mode with image transfer in this coplanar flat forms a line layer, this insulation material layer of this line layer cover part and the upper surface of this projection cube structure, and be connected with this projection cube structure; And
One welding resisting layer making step, is in this coplanar flat, to form a welding resisting layer, and this welding resisting layer is not covered this insulation material layer and this projection cube structure part by this line layer covers, and the line layer of part is covered.
2. the method for claim 1, it is characterized in that, this insulation material layer pressing step is when this insulating material of pressing, further simultaneously at least one carbon fibre initial rinse fabric of pressing and be arranged at least one conductive layer on this at least one carbon fibre initial rinse fabric, make this at least one carbon fibre initial rinse fabric, and this at least one conductive layer edge is embedded among insulation material layer, then in this brushing step, the upper surface of this at least one conductive layer and this projection cube structure is exposed, make this coplanar flat for this insulation material layer, the plane of surface co-planar on this at least one conductive layer and this projection cube structure, and while making line layer making step, this projection cube structure of this line layer shape cover part, this at least one conductive layer and this insulation material layer, and when this welding resisting layer making step, make this welding resisting layer covering insulating material layer, the part that projection cube structure and conductive layer are not covered by this line layer, and the line layer of covering part.
3. the method for claim 1, it is characterized in that, further after this etching step, carry out one second etching step, this second etching step is not covered barrier layer with one second etching solution part by this projection cube structure is removed, wherein this second etching solution does not produce and reacts with this metallic substrate layer and this projection cube structure, and then, when this insulation material layer pressing step is carried out, this insulation material layer fills up the space between this barrier layer and this metallic substrate layer and this projection cube structure.
4. method as claimed in claim 2, it is characterized in that, further after this etching step, carry out one second etching step, this second etching step is not covered barrier layer with one second etching solution part by this projection cube structure is removed, wherein this second etching solution does not produce and reacts with this metallic substrate layer and this projection cube structure, and then, when this insulation material layer pressing step is carried out, this insulation material layer fills up the space between this barrier layer and this metallic substrate layer and this projection cube structure.
5. the method for claim 1, it is characterized in that, the material of this metallic substrate layer, this projection cube structure, this line layer be copper, aluminium at least one of them, and the material of this barrier layer be tin, nickel, titanium, palladium at least one of them, and Jie's metallic compound forming with the material of this metallic substrate layer, and the scope of this barrier layer thickness is 3 μ m～10 μ m, this insulation material layer be BT resin, glass fibre, ABF glued membrane at least one of them.
6. method as claimed in claim 2, is characterized in that, the material of this at least one conductive layer be copper, aluminium at least one of them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210233005.XA CN103531484B (en) | 2012-07-06 | 2012-07-06 | The manufacture method of chip bearing board structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210233005.XA CN103531484B (en) | 2012-07-06 | 2012-07-06 | The manufacture method of chip bearing board structure |
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| Publication Number | Publication Date |
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| CN103531484A true CN103531484A (en) | 2014-01-22 |
| CN103531484B CN103531484B (en) | 2016-12-21 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5492235A (en) * | 1995-12-18 | 1996-02-20 | Intel Corporation | Process for single mask C4 solder bump fabrication |
| CN1445824A (en) * | 2003-04-17 | 2003-10-01 | 威盛电子股份有限公司 | Method for preparing lugs and glue stuff layer |
| US20060258139A1 (en) * | 1999-10-12 | 2006-11-16 | Tessera Interconnect Materials, Inc. | Manufacturing method for wiring circuit substrate |
| TW200942762A (en) * | 2008-04-11 | 2009-10-16 | Unimicron Technology Corp | Circuit board and process for fabricating the same |
-
2012
- 2012-07-06 CN CN201210233005.XA patent/CN103531484B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5492235A (en) * | 1995-12-18 | 1996-02-20 | Intel Corporation | Process for single mask C4 solder bump fabrication |
| US20060258139A1 (en) * | 1999-10-12 | 2006-11-16 | Tessera Interconnect Materials, Inc. | Manufacturing method for wiring circuit substrate |
| CN1445824A (en) * | 2003-04-17 | 2003-10-01 | 威盛电子股份有限公司 | Method for preparing lugs and glue stuff layer |
| TW200942762A (en) * | 2008-04-11 | 2009-10-16 | Unimicron Technology Corp | Circuit board and process for fabricating the same |
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| CN103531484B (en) | 2016-12-21 |
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