CN103515211A - Method for manufacturing semiconductor device with air gap - Google Patents
Method for manufacturing semiconductor device with air gap Download PDFInfo
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- CN103515211A CN103515211A CN201210206475.7A CN201210206475A CN103515211A CN 103515211 A CN103515211 A CN 103515211A CN 201210206475 A CN201210206475 A CN 201210206475A CN 103515211 A CN103515211 A CN 103515211A
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- layer
- air gap
- semiconductor device
- etching
- mask layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
Abstract
The invention provides a method for manufacturing a semiconductor device with an air gap. The method comprises the steps of providing a semiconductor substrate, forming a hard mask layer with a trench on the semiconductor substrate, covering a flank wall film on the surfaces of the hard mask layer and the trench, etching the flank wall film to form gate flank walls on the side walls of the trench, covering a sacrificial film on the surfaces of the hard mask layer, the gate flank walls and the trench, etching the sacrificial film to form sacrificial layers on the gate flank walls, filling a gate layer in the trench and removing the hard mask layer and the sacrificial layers. The gate flank walls and the sacrificial layers are sequentially formed in the trench of the hard mask layer, and the sacrificial layers are removed by a wet etching or heating method after the hard mask layer is removed. Therefore, an air gap is formed between the gate layer and the gate flank walls, the dielectric capability of a gate is improved, and the performance of the semiconductor device is improved.
Description
Technical field
The present invention relates to the manufacture method of semiconductor device, relate in particular to a kind of manufacture method with the semiconductor device of air gap.
Background technology
Progress along with integrated circuit technique, the integrated level of semiconductor device is more and more higher, the principal element of the speed of restriction semiconductor device is no longer transistor delay, but the resistance-capacitance (RC) for example, being associated with electric conducting material (metal) interconnection postpones.After recognizing this point, thereby reduce RC delay in order to reduce the electric capacity of conductive interconnect material, those skilled in the art have carried out extensive work for researching and developing new material and manufacturing process.For example, using the dielectric substance in conductive interconnect material layer, select to adopt the dielectric substance with low-k.
All material medium dielectric constant microwave medium minimum surely belong to air, therefore, technical staff starts to focus between electric conducting material and makes air gap (Air Gap), further to reduce dielectric constant, thereby reduces the electric capacity between electric conducting material.Mainly contain following two kinds of methods and form the semiconductor device with air gap: a kind of method is to utilize the characteristic of the selectivity deposition of chemical vapour deposition (CVD) (CVD), between the metal interconnecting wires in metal interconnecting layer, forms air gap; Another kind method is in being configured with the metal interconnecting layer of one or more metal interconnecting wires, in the operating period of special process, removes preformed sacrifice layer, to form air gap.
For above-mentioned the second manufacture method, along with characteristic size is constantly dwindled, size between metal interconnecting wires and metal interconnecting layer is more and more less, therefore, is pre-formed the size of sacrifice layer and the control of the distance between sacrifice layer becomes the key factor that affects air gap performance.
Summary of the invention
The object of this invention is to provide a kind of manufacture method with the semiconductor device of air gap, improve the dielectric properties of grid, and then improve the performance of semiconductor device.
For addressing the above problem, the invention provides a kind of manufacture method with the semiconductor device of air gap, comprise the following steps:
Semiconductor substrate is provided, in described Semiconductor substrate, forms the fluted hard mask layer of tool;
At described hard mask layer and flute surfaces, cover side wall film;
Side wall film described in etching, to form grid curb wall on the sidewall of described groove;
In described hard mask layer, grid curb wall and flute surfaces, cover sacrificial film;
Sacrificial film described in etching, to form sacrifice layer on described grid curb wall;
In described groove, fill grid layer; And
Remove described hard mask layer and sacrifice layer.
Further, the material of described sacrifice layer is silica.
Further, adopt wet etching to remove described sacrifice layer, etching material is hydrofluoric acid.
Further, the material of described sacrifice layer is silicon nitride.
Further, adopt wet etching to remove described sacrifice layer, etching material is hot phosphoric acid.
Further, the material of described sacrifice layer is low dielectric constant material layer.
Further, the material of described sacrifice layer is porous silicon, fluorine silica, silicon oxide carbide, one or more in the Si oxide of the Si oxide of microminiature foamed plastics, silica-based insulator, doping carbon or doping chlorine.
Further, the material of described sacrifice layer be can thermal decomposition organic polymer.
Further, the material of described sacrifice layer is the copolymer of butyl norborene and the silica-based norborene of three ethoxies.
Further, described sacrifice layer adopts heating to remove.
Further, the material of described grid curb wall is silicon nitride, silica, silicon oxynitride, one or more in silicon oxide carbide, silicon nitride or amorphous carbon.
Further, the material of described hard mask layer is silicon nitride, silica, silicon oxynitride or amorphous carbon.
Further, the material of described hard mask layer is silicon nitride, and etching is removed in the process of described mask layer, and etching material comprises CH
3f and O
2, ambient pressure is 10mtorr～50mtorr, and energy is 300W～800W, and bias voltage is 200V～500V, CH
3the flow of F is 50sccm～300sccm, O
2flow be 50sccm～200sccm.
Further, the material of described hard mask layer is silica, and etching is removed in the process of described mask layer, and etching material comprises CH
3f and He, ambient pressure is 1mtorr ~ 5mtorr, and energy is 100W～600W, and bias voltage is 20V～200V, CH
3flow 10sccm～100sccm of F, the flow of He is 50sccm～200sccm.
Further, the material of described hard mask layer is amorphous carbon, and etching is removed in the process of described mask layer, etching material O
2, ambient pressure is 20mtorr～50mtorr, energy is 100W～500W, O
2flow be 300sccm～1000sccm.
Further, further comprising the steps of in removing described hard mask layer and wet etching and remove the step of described sacrifice layer: in the Semiconductor substrate of described grid layer both sides, to carry out source-drain area injection; And the Semiconductor substrate of described grid layer and grid layer both sides is carried out to metallization process.
In sum, the present invention by forming successively grid curb wall and sacrifice layer in the groove of described hard mask layer, remove after hard mask layer, utilize wet etching or heating to remove sacrifice layer, thereby between described grid layer and described grid curb wall, form air gap (Air Gap), improve the dielectric properties of grid, and then improve the performance of semiconductor device.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of manufacture method in one embodiment of the invention with the semiconductor device of air gap.
Fig. 2～Figure 10 is the cross-sectional view in one embodiment of the invention with device in the manufacture process of semiconductor device of air gap.
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention is described in detail in detail, for convenience of explanation, schematic diagram does not amplify according to general ratio is local, should not using this as limitation of the invention.
As shown in Figure 1, it is for having the schematic flow sheet of manufacture method of the semiconductor device of air gap in one embodiment of the invention.The invention provides a kind of manufacture method with the semiconductor device of air gap, comprise the following steps:
Step S01: Semiconductor substrate is provided, forms the fluted hard mask layer of tool in described Semiconductor substrate;
Step S02: cover side wall film at described hard mask layer and flute surfaces;
Step S03: side wall film described in etching, to form grid curb wall on the sidewall of described groove;
Step S04: cover sacrificial film in described hard mask layer, grid curb wall and flute surfaces;
Step S05: sacrificial film described in etching, to form sacrifice layer on described grid curb wall;
Step S06: fill grid layer in described groove;
Step S07: remove described hard mask layer and sacrifice layer.
Fig. 2～Figure 10 is the cross-sectional view in one embodiment of the invention with device in the manufacture process of semiconductor device of air gap.Below in conjunction with Fig. 2～Figure 10, describe the manufacture method with the semiconductor device of air gap of the present invention in detail.
As shown in Figure 2, in step S01, provide Semiconductor substrate 100, in described Semiconductor substrate 100, form the hard mask layer 102 with groove 200, the described concrete forming process of hard mask layer 102 with groove 200 comprises: first in Semiconductor substrate 100, deposit hard mask layer 102, then on described hard mask layer 102, apply photoresist (not indicating in figure), and described photoresist is exposed and developed with photoresist described in patterning, then the described photoresist that utilizes patterning is hard mask layer described in mask etching 102, to form groove 200 in described hard mask layer 102, the thickness of described hard mask layer 102 can be determined according to the thickness of follow-up formation grid layer, the shape of described groove 200 can be according to subsequent gate layer, the shape of grid curb wall and sacrifice layer, size defines, the present invention will not limit this.
Wherein, the material of described Semiconductor substrate 100 can be monocrystalline silicon, polysilicon, amorphous silicon, silicon Germanium compound or silicon-on-insulator (SOI) etc., and other semi-conducting materials also can be used as the material of Semiconductor substrate 100.In described Semiconductor substrate 100, can also there are other element separation, such as fleet plough groove isolation structure (STI) etc., said structure is determined according to actual semiconductor device process for making, is well known to those skilled in the art technology contents, therefore do not repeat them here.
As shown in Figure 3, in step S02, at described hard mask layer 102 and groove 200 surface coverage side wall film 104a; The material of described side wall film 104a can be silicon nitride, silica, silicon oxynitride, a kind of or its combination in silicon oxide carbide, silicon nitride or amorphous carbon, in preferred embodiment, the material of described side wall film 104a is silicon nitride, described side wall film 104a can adopt chemical vapour deposition (CVD) (CVD) to form, and described side wall film 104a preferably thickness is 100 dust～200 dusts.
As shown in Figure 4, in step S03, side wall film 104a described in etching, to form grid curb wall 104 on the sidewall at described groove 200; In etching process, etching is to being positioned at the side wall film 104a of the groove 200 bottoms removal that is first etched, remaining side wall film 104a stays on the sidewall of described groove 200, described grid curb wall 104 can covering groove 200 partial sidewall or whole sidewalls (being the partial sidewall of covering groove 200 in Fig. 4), can be by adjusting etching technics parameter, for example etch period and etching gas, control the shape of grid curb wall 104.
As shown in Figure 5, in step S04, at described hard mask layer 102, grid curb wall 104 and groove 200 surface coverage sacrificial film 106a, the material of described sacrificial film 106a can be silica or silicon nitride, it can also be low dielectric constant material layer, porous silicon for example, fluorine silica, silicon oxide carbide, microminiature foamed plastics, silica-based insulator, a kind of or above-mentioned several combination in the Si oxide of the Si oxide of doping carbon or doping chlorine, the material of described sacrificial film 106a can also be organic polymer that can thermal decomposition, such as copolymer (Copolymer of Copolymer of Butylnorbornene and Triethoxysilyl Norbornene) of butyl norborene and the silica-based norborene of three ethoxies etc., for organic polymer that can thermal decomposition, can adopt the method for coating to form.
As shown in Figure 6, in step S05, sacrificial film 106a described in etching, to form sacrifice layer 106 on the sidewall at described groove 200, described sacrifice layer 106 is covered on described grid curb wall 104; When the material of described sacrificial film 106a is silica, can wet etching described in sacrificial film 106a, etching material is for example hydrofluoric acid; When the material of described sacrificial film 106a is silicon nitride, can wet etching described in sacrificial film 106a, the hot phosphoric acid that etching material is for example 80%～90% for mass concentration; When the material of described sacrificial film 106a is low dielectric constant material layer, can dry etching described in sacrificial film 106a.Equally, because dry etching has anisotropic characteristic, in etching process, etching is to being positioned at the sacrificial film 106a of the groove 200 bottoms removal that is first etched, remaining sacrificial film 106a stays on the sidewall of described groove 200, thereby forms sacrifice layer 106 as shown in Figure 7.
As shown in Figure 7, in step S06, in described groove 200, fill grid layer 108; The material of described grid layer 108 is for example polysilicon, and the detailed process of its formation comprises: the grid layer film of deposit spathic silicon material (in figure do not indicate) first, and described grid layer film is filled described groove 200; Then utilize cmp to remove and be positioned at groove 200 grid layer film in addition, to form grid layer 108.
As shown in Figure 8, in step S07, remove described hard mask layer 102 and described sacrifice layer 106, concrete, hard mask layer 102 can profit be removed with the following method: when the material of described hard mask layer 102 is silicon nitride, etching is removed in the process of described mask layer 102, and etching material comprises CH
3f and O
2, ambient pressure is 10mtorr～50mtorr (millitorr), and energy is 300W～800W, and bias voltage is 200V～500V, CH
3the flow of F is 50sccm～300sccm, O
2flow be 50sccm～200sccm; When the material of described hard mask layer 102 is silica, etching is removed in the process of described mask layer 102, and etching material comprises CH
3f and He, ambient pressure is 1mtorr～5mtorr, and energy is 100W～600W, and bias voltage is 20V～200V, CHF
3flow 10sccm～100sccm, the flow of He is 50sccm～200sccm; When the material of described hard mask layer 102 is amorphous carbon, etching is removed in the process of described mask layer 102, and etching material comprises O
2, ambient pressure is 20mtorr～50mtorr, energy is 100W～500W, O
2flow be 300sccm～1000sccm.
Removing between described hard mask layer 102 and the step of described sacrifice layer 106, can also comprise the following steps: in the Semiconductor substrate 100 of described grid layer 108 both sides, carry out source-drain area injection; Semiconductor substrate 100 to described grid layer 108 and grid layer 108 both sides is carried out metallization process, and the routine techniques means that formation method is those skilled in the art, therefore do not repeat.
In removing the step of described sacrifice layer 106, particularly, when the material of described sacrifice layer 106 can be low dielectric constant material layer, for porous silicon, fluorine silica, silicon oxide carbide, a kind of or above-mentioned several combination in the Si oxide of the Si oxide of microminiature foamed plastics, silica-based insulator, doping carbon or doping chlorine, can adopt wet etching to remove; When the material of described sacrifice layer 106 is silica, can adopt sacrifice layer 106 described in wet etching, etching material is hydrofluoric acid; When the material of described sacrifice layer 106 is silicon nitride, can adopt sacrificial film 106a described in wet etching, etching material is that mass concentration is 80%～90% hot phosphoric acid; When the material of described sacrifice layer 106 is low dielectric constant material layer, can adopt sacrifice layer 106 described in dry etching; In addition, when described sacrifice layer 106 be can thermal decomposition organic polymer time, can adopt the method for thermal decomposition to remove.
Thereafter, proceed other processing steps, for example as shown in figure 10, deposition stressor layers 110 covers described Semiconductor substrate 100 and grid layer 108, carries out stress memory effect etc.
In sum, the present invention by forming successively grid curb wall and sacrifice layer in the groove of described hard mask layer, remove after hard mask layer, utilize wet etching or heating to remove sacrifice layer, thereby between described grid layer and described grid curb wall, form air gap (Air Gap), improve the dielectric properties of grid, and then improve the performance of semiconductor device.
Although the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; under any, in technical field, have and conventionally know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is when being as the criterion depending on claims person of defining.
Claims (15)
1. a manufacture method with the semiconductor device of air gap, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, forms the fluted hard mask layer of tool;
At described hard mask layer and flute surfaces, cover side wall film;
Side wall film described in etching, to form grid curb wall on the sidewall of described groove;
In described hard mask layer, grid curb wall and flute surfaces, cover sacrificial film;
Sacrificial film described in etching, to form sacrifice layer on described grid curb wall;
In described groove, fill grid layer; And
Remove described hard mask layer and sacrifice layer.
2. the manufacture method with the semiconductor device of air gap as claimed in claim 1, is characterized in that, the material of described sacrifice layer is silica or silicon nitride.
3. the manufacture method with the semiconductor device of air gap as claimed in claim 2, is characterized in that, the material of described sacrifice layer is silica, adopts wet etching to remove described sacrifice layer, and etching material is hydrofluoric acid.
4. the manufacture method with the semiconductor device of air gap as claimed in claim 2, is characterized in that, the material of described sacrifice layer is silicon nitride, adopts wet etching to remove described sacrifice layer, and etching material is hot phosphoric acid.
5. the manufacture method with the semiconductor device of air gap as claimed in claim 1, is characterized in that, the material of described sacrifice layer is low dielectric constant material layer.
6. the manufacture method with the semiconductor device of air gap as claimed in claim 1, it is characterized in that, the material of described sacrifice layer is porous silicon, fluorine silica, silicon oxide carbide, one or more in the Si oxide of the Si oxide of microminiature foamed plastics, silica-based insulator, doping carbon or doping chlorine.
7. the manufacture method with the semiconductor device of air gap as claimed in claim 6, is characterized in that, the material of described sacrifice layer be can thermal decomposition organic polymer.
8. the manufacture method with the semiconductor device of air gap as claimed in claim 7, is characterized in that, the material of described sacrifice layer is the copolymer of butyl norborene and the silica-based norborene of three ethoxies.
9. have as claimed in claim 7 or 8 the manufacture method of the semiconductor device of air gap, it is characterized in that, described sacrifice layer adopts heating to remove.
10. the manufacture method with the semiconductor device of air gap as claimed in claim 1, is characterized in that, the material of described grid curb wall is silicon nitride, silica, silicon oxynitride, one or more in silicon oxide carbide, silicon nitride or amorphous carbon.
11. manufacture methods with the semiconductor device of air gap as claimed in claim 1, is characterized in that, the material of described hard mask layer is silicon nitride, silica, silicon oxynitride or amorphous carbon.
12. manufacture methods with the semiconductor device of air gap as claimed in claim 11, is characterized in that, the material of described hard mask layer is silicon nitride, and etching is removed in the process of described mask layer, and etching material comprises CH
3f and O
2, ambient pressure is 10mtorr～50mtorr, and energy is 300W～800W, and bias voltage is 200V～500V, CH
3the flow of F is 50sccm～300sccm, O
2flow be 50sccm～200sccm.
13. manufacture methods with the semiconductor device of air gap as claimed in claim 11, is characterized in that, the material of described hard mask layer is silica, and etching is removed in the process of described mask layer, and etching material comprises CH
3f and He, ambient pressure is 1mtorr～5mtorr, and energy is 100W～600W, and bias voltage is 20V～200V, CH
3flow 10sccm～100sccm of F, the flow of He is 50sccm～200sccm.
14. manufacture methods with the semiconductor device of air gap as claimed in claim 11, is characterized in that, the material of described hard mask layer is amorphous carbon, and etching is removed in the process of described mask layer, etching material O
2, ambient pressure is 20mtorr～50mtorr, energy is 100W～500W, O
2flow be 300sccm～1000sccm.
15. manufacture methods with the semiconductor device of air gap as claimed in claim 1, is characterized in that, at the described hard mask layer of removal and wet etching, remove in the step of described sacrifice layer, also comprise:
In the Semiconductor substrate of described grid layer both sides, carry out source-drain area injection; And
Semiconductor substrate to described grid layer and grid layer both sides is carried out metallization process.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210206475.7A CN103515211A (en) | 2012-06-20 | 2012-06-20 | Method for manufacturing semiconductor device with air gap |
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|---|---|---|---|
| CN201210206475.7A CN103515211A (en) | 2012-06-20 | 2012-06-20 | Method for manufacturing semiconductor device with air gap |
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| CN201210206475.7A Pending CN103515211A (en) | 2012-06-20 | 2012-06-20 | Method for manufacturing semiconductor device with air gap |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9419091B1 (en) | 2015-02-04 | 2016-08-16 | International Business Machines Corporation | Trenched gate with sidewall airgap spacer |
| CN106898597A (en) * | 2015-12-18 | 2017-06-27 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its manufacture method |
| CN109390402A (en) * | 2017-08-10 | 2019-02-26 | 长鑫存储技术有限公司 | A kind of semiconductor transistor construction and preparation method thereof |
| CN111192823A (en) * | 2018-11-14 | 2020-05-22 | 东京毅力科创株式会社 | Method for manufacturing device |
| CN112151443A (en) * | 2020-09-25 | 2020-12-29 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9419091B1 (en) | 2015-02-04 | 2016-08-16 | International Business Machines Corporation | Trenched gate with sidewall airgap spacer |
| CN106898597A (en) * | 2015-12-18 | 2017-06-27 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its manufacture method |
| US10164029B2 (en) | 2015-12-18 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and manufacturing method thereof |
| CN106898597B (en) * | 2015-12-18 | 2020-10-30 | 台湾积体电路制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| US10879364B2 (en) | 2015-12-18 | 2020-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and manufacturing method thereof |
| CN109390402A (en) * | 2017-08-10 | 2019-02-26 | 长鑫存储技术有限公司 | A kind of semiconductor transistor construction and preparation method thereof |
| CN111192823A (en) * | 2018-11-14 | 2020-05-22 | 东京毅力科创株式会社 | Method for manufacturing device |
| CN112151443A (en) * | 2020-09-25 | 2020-12-29 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
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Application publication date: 20140115 |