CN103514843A - Amorphous silicon integration grid driving circuit - Google Patents
Amorphous silicon integration grid driving circuit Download PDFInfo
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- CN103514843A CN103514843A CN201210214875.2A CN201210214875A CN103514843A CN 103514843 A CN103514843 A CN 103514843A CN 201210214875 A CN201210214875 A CN 201210214875A CN 103514843 A CN103514843 A CN 103514843A
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- level voltage
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Abstract
The invention provides an amorphous silicon integration grid driving circuit. The circuit comprises a plurality of shifting registers. Each shifting register is used to receive a clock signal and a start signal and output a grid driving signal so as to drive a pixel column. The clock signal is switched between a high level voltage and a low level voltage. The clock signal is adjacent to at least one of a level rising edge and a level falling edge and is firstly switched to a second low level voltage which is lower than the low level voltage.
Description
Technical field
The present invention relates to a kind of amorphous silicon and integrate gate driver circuit (Amorphous Silicon Gate, ASG), and be particularly related to a kind of amorphous silicon integration gate driver circuit that can improve driving force.
Background technology
Liquid crystal display needs gate driver circuit to drive each pixel column, and source electrode drive circuit is supplied with each pixel image data.And the drive IC that the many uses of traditional liquid crystal display are attached at panel side is used as the gate driver circuit of this panel.In recent years, because ripe processing procedure and low cost of manufacture, amorphous silicon is integrated gate driver circuit (Amorphous Silicon Gate, ASG) technology and has been widely used in active liquid crystal display.So-called amorphous silicon is integrated gate driver circuit and is referred to and in amorphous silicon processing procedure, be directly integrated in the gate driver circuit on panel, and this technology is also collectively referred to as gate driver circuit technology on panel (Gate On Panel, GOP).
Along with the raising of panel resolution, the load of each gate line also increases thereupon, so the higher driving force that gate driver circuit need to possess drives pixel column.Moreover for the demand in response to narrow edge frame product, on panel, the arrangement space of gate driver circuit is limited, in limited space, make gate driver circuit there is enough driving forces, be also one of difficult problem of this technical development.Therefore, need a kind of amorphous silicon integration gate driver circuit that circuit layout area can improve driving force simultaneously that do not need to increase.
And the driving force of amorphous silicon integration gate driver circuit is decided by rise time and the fall time of the grid impulse of its output whether to reach short.When driving force is not enough, the long rise time can be compressed to the write time of pixel, and the pixel data that may make the mistake long fall time writes.
Summary of the invention
Because above-mentioned demand and problem points, the invention provides a kind of amorphous silicon and integrate gate driver circuit, comprise a plurality of shift registers, each shift register is in order to receive a clock signal and a start signal and to export a gate drive signal to drive a pixel column, and this clock signal switches between a high level voltage and a low level voltage, wherein this clock signal is more in close proximity at least one in electrical level rising edge and level trailing edge edge, first switches to second low level voltage lower than this low level voltage.
At above-mentioned amorphous silicon, integrate in gate driver circuit, the difference of this low level voltage and this second low level voltage be no more than this high level voltage and this low level voltage difference 1/2, or the difference of this low level voltage and this second low level voltage is less than 10V.And the time span of this second low level voltage is less than 10 μ s.
The present invention also provides a kind of amorphous silicon to integrate gate driver circuit, comprise a plurality of shift registers, each shift register is in order to receive a clock signal and a start signal and to export a gate drive signal to drive a pixel column, this clock signal switches between a high level voltage and a low level voltage, wherein this clock signal first switches to one second low level voltage by this low level voltage in next-door neighbour electrical level rising edge and switches to this high level voltage again, and in next-door neighbour level decline edge, first by this high level voltage, switch to one the 3rd low level voltage and switch to again this low level voltage, and this second low level voltage and the 3rd low level voltage are all lower than this low level voltage.
At above-mentioned amorphous silicon, integrate in gate driver circuit, 1/2 of the neither difference over this high level voltage and this low level voltage of difference of the difference of this low level voltage and this second low level voltage and this low level voltage and the 3rd low level voltage, or the difference of the difference of this low level voltage and this second low level voltage and this low level voltage and the 3rd low level voltage is not less than 10V.And the time span of the time span of this second low level voltage and the 3rd level voltage is less than respectively 10 μ s.
According to one embodiment of the invention, this second low level voltage that above-mentioned amorphous silicon is integrated in gate driver circuit equals the 3rd level voltage.
According to amorphous silicon of the present invention, integrate gate driver circuit, do not need to increase circuit layout area or change circuit design, the waveform that only changes clock signal can effectively improve the driving force of circuit.
Accompanying drawing explanation
Fig. 1 is the generalized schematic that typical amorphous silicon is integrated gate driver circuit.
Fig. 2 is the circuit diagram that the amorphous silicon shown in Fig. 1 is integrated a shift register in gate driver circuit.
Fig. 3 is traditional clock signal oscillogram of the shift register shown in input Fig. 2.
Fig. 4 (a) is the oscillogram of clock signal of the embodiment of the present invention of the shift register of input shown in Fig. 2; The oscillogram of the output signal that Fig. 4 (b) is corresponding; The oscillogram of the P1 node that Fig. 4 (c) is corresponding.
Fig. 5 (a) is the oscillogram of clock signal of the embodiment of the present invention 2 of the shift register of input shown in Fig. 2; The oscillogram of the output signal that Fig. 5 (b) is corresponding; The oscillogram of the P1 node that Fig. 5 (c) is corresponding.
Fig. 6 (a) is the oscillogram of clock signal of the embodiment of the present invention 3 of the shift register of input shown in Fig. 2; The oscillogram of the output signal that Fig. 6 (b) is corresponding; The oscillogram of the P1 node that Fig. 6 (c) is corresponding.
Fig. 7 is the comparison diagram of clock signal to the rise time of output signal and fall time that uses the embodiment of the present invention 1～3 and known technology.
[main element symbol description]
1～shift register;
10～control circuit;
20～output circuit;
CK, Clock_In, Clock_InR, Clock_InF, Clock_InRF～clock signal;
STV～start signal;
VGH～high level;
VGL～low level;
VGL2～the second low level;
VGL3～three low level;
T1, T2, T3～transistor;
Cc～electric capacity;
Out1 ~ N, Outout_M-1, Outout_M, Outout_M-1～output signal;
P1, Q1, N1, N2, N3～node.
Embodiment
Fig. 1 is the generalized schematic that typical amorphous silicon is integrated gate driver circuit.As shown in Figure 1, amorphous silicon is integrated shift register Channel 1～N that gate driver circuit comprises plural number level, each shift register receive clock signal CK, start signal, reset signal and common low level voltage VGL.The first order shift register Channel 1 of take is example, and the gate drive signal out 1 that exports a pulse after its reception start signal STV is in order to drive the first pixel column.Then, second level shift register Channel2 can receive the gate drive signal out 1 of first order shift register Channel 1 as its start signal, and the gate drive signal out 2 that exports a pulse is in order to drive the second pixel column and to reset first order shift register Channel 1.The rest may be inferred, and the shift register Channel 1～N of N level sequentially exports gate drive signal out 1～out N and drives the first pixel column～the N pixel column.At this, should be noted in different circuit frameworks, start signal also can be provided by the shift register beyond upper level, and reset signal is also provided by the shift register beyond next stage, and Fig. 1 is the framework of a kind of amorphous silicon integration of illustration gate driver circuit only.
Fig. 2 is the circuit diagram that the amorphous silicon shown in Fig. 1 is integrated a shift register in gate driver circuit.Fig. 3 is traditional clock signal oscillogram of the shift register shown in input Fig. 2.As shown in Figure 3, clock signal C lock_in switches on the square-wave signal of high level VGH and low level VGL.Get back to Fig. 2, a M level shift register 1 comprises that a control circuit 10 and is connected in the output circuit 20 of control circuit 10 rear ends.In Fig. 2, control circuit 10 represents with a square, because its inner circuit structure can be done multiple different design, precisely because common point is to receive a clock signal Clock_in and a start signal Outout_M-1(when this shift register is the first order, start signal is STV), and there are two output terminal node P1 and Q1 outputs signal to output circuit 20.The essential structure of output circuit 20 is comprised of 3 transistor Ts 1, T2, T3 and 1 capacitor C c, wherein transistor T 1 is for pulling up transistor, and between the selecting period in order to the M pixel column that connects at this M level shift register 1, by output signal Output_M(, is grid control signal) be promoted to high level VGH.2 of transistor Ts are pull-down transistor, in order to output signal Output_M is pulled down to low level VGL during the non-selection at this M pixel column.Transistor T 3 receives reset signal Outout_M+1, when the grid control signal of the shift register output high level VGH of next stage, output signal Output_M is pulled low to low level VGL.
Capacitor C c is connected between the grid and source electrode of transistor T 1, between node P1 and node N2.Capacitor C c is used for capacitive coupling node P1 and node N2.Due to when transistor T 1 will be transferred to opening or will be transferred to closed condition by opening by closed condition, the clock signal C lock_in of the drain electrode of transistor T 1 is promoted to high level voltage after can low level voltage being dropped to the second low level voltage lower than this low level voltage again before electrical level rising edge as described later again, or after dropping to the second low level voltage, be promoted to again low level voltage in level trailing edge, so when transistor T 1 is opening, can utilizes this capacitor C c and node P1 level voltage is improved.In addition, when grid and the interchannel electric capacity of transistor T 1 are enough large, capacitor C c also can be replaced by the equivalent capacity of transistor T 1 and directly omit.
In order to make the rise time of output signal or to shorten to improve the driving force of shift register fall time, the present invention is that the waveform that changes the clock signal of input shift register is reached object.Fig. 4 is by the signal waveforms of the explanation embodiment of the present invention 1.
Fig. 4 (a) is the oscillogram of clock signal of the embodiment of the present invention 1 of the shift register of input shown in Fig. 2; The oscillogram of the output signal that Fig. 4 (b) is corresponding; The oscillogram of the P1 node that Fig. 4 (c) is corresponding.In Fig. 4 (a), clock signal C lock_inR can first switch to the second low level VGL2 lower than low level VGL in the time of will switching to high level VGH from low level VGL each time.Because making the voltage change amount on rising edge edge, clock signal C lock_inR is increased to (VGH-VGL2) by (VGH-VGL), the voltage change amount increase of node N1 makes the node voltage of P1 draw high higher value (voltage that is node P1 in Fig. 4 (c) has more increased Δ V) by the stray capacitance between node N1 and P1, therefore transistor T 1 produces larger electric current to node N2 charging, has effectively shortened the rise time of output signal Output.
In addition, the transistor T 3 of shift register that can export prime to because of output signal Output is with the output terminal node N2 of replacement prime shift register, the output signal Output with the shorter rise time is turn-on transistor T3 at faster speed, make the output signal of prime shift register be discharged to sooner low level VGL, so the waveform of clock signal also has the effect that shortens fall time simultaneously.
Fig. 5 is by the signal waveforms of the explanation embodiment of the present invention 2.Fig. 5 a is the oscillogram of clock signal of the embodiment of the present invention 2 of the shift register of input shown in Fig. 2; The oscillogram of the output signal that Fig. 5 b is corresponding; The oscillogram of the P1 node that Fig. 5 c is corresponding.In Fig. 5 a, clock signal C lock_inF can first switch to the second low level VGL2 lower than low level VGL in the time of will switching to low level VGL from high level VGH each time.Because making the voltage change amount on trailing edge edge, clock signal C lock_inR is increased to (VGH-VGL2) by (VGH-VGL), because transistor T 1 can't be closed along moment at the signal level trailing edge of node P1, therefore the voltage change amount of node N1 increases, can help the level of node N2 drop-down, effectively shorten the fall time of output signal Output.
Fig. 6 is by the signal waveforms of the explanation embodiment of the present invention 3.Fig. 6 a is the oscillogram of clock signal of the embodiment of the present invention 3 of the shift register of input shown in Fig. 2; The oscillogram of the output signal that Fig. 6 b is corresponding; The oscillogram of the P1 node that Fig. 6 c is corresponding.In Fig. 6 a, clock signal C lock_inRF can first switch to the second low level VGL2 lower than low level VGL each time when low level VGL switches to high level VGH and switch to low level VGL from high level VGH.
First, the voltage change amount on clock signal C lock_inRF rising edge edge increases, can make as described in Example 1 the voltage of node P1 be pulled up to higher value, make transistor T 1 produce larger electric current to node N2 charging, effectively shorten the rise time of output signal Output.And because output signal Output can feed back to prime shift register, therefore can shorten fall time simultaneously.And the voltage change amount on clock signal C lock_inRF trailing edge edge increases, can help as described in Example 2 the level of node N2 drop-down, effectively shortened the fall time of output signal Output.
In the middle of above-described embodiment 1～3, amorphous silicon is integrated the clock signal of gate driver circuit according to the design of panel, and high level VGH is generally between 15～25V, and low level is between-5～-10V.The second low level VGL2 cans be compared to most the low 10V that is no more than of low level VGL.That is to say, the difference of low level VGL and the second low level VGL2 surpass high level VGH and low level VGL difference 1/2, more preferably below 1/3, because the second too low low level VGL2 can cause the increase of power consumption.In addition, the second low level VGL2 time width is less than 10 μ s, is more preferably less than 5 μ s, because the second low level VGL2 of overlong time not only can increase power consumption, also may cause the output signal that does not conform with demand.
In addition, in embodiment 3, though disclose the rising edge of clock signal C lock_inRF along being all close to the second identical low level with trailing edge edge, but rising edge is along being also close to respectively the second different low level VGL2 and the 3rd low level VGL3 from trailing edge edge, yet both must be lower than low level VGL, and possesses the restriction of size and time span as mentioned above.
Fig. 7 is the comparison diagram of clock signal to the rise time of output signal and fall time that uses the embodiment of the present invention 1～3 and known technology.In Fig. 7, be to use the panel that 5 inches of resolutions are 640 * RGB * 960 to simulate.First use normal clock signal C lock_in, calculate respectively its rise time and fall time.When using embodiment 1 rising edge along next-door neighbour the second low level clock signal C lock_inR, the rise time reduces 20.9%, reduces 3% fall time; When using embodiment 2 trailing edges along next-door neighbour the second low level clock signal C lock_inF, reduce 31.2% fall time; When using embodiment 3 rising edges edges to be all close to the second low level clock signal C lock_inRF with trailing edge edge, the rise time reduces 18.3%, reduces 36.5% fall time.
In addition, owing to increasing the level of clock signal switching, can improve power consumption, but known in Fig. 7, the clock signal C lock_inRF of the embodiment 3 that power consumption is the highest also only increases by 9% with respect to normal clock signal C lock_in, therefore significantly promoting under the advantage of amorphous silicon integration gate driver circuit driving force, the power consumption increase of a little can be accepted.
The various embodiments described above according to the present invention, amorphous silicon of the present invention is integrated gate driver circuit and is not needed to increase circuit layout area or change circuit design, and the waveform that only changes clock signal can effectively improve the driving force of circuit.Therefore the present invention can be applied to gate driver circuit technology on the panel of various frameworks, and is not limited to the gate driver circuit of certain architectures.
Though the present invention illustrates with above-described embodiment, is not limited to this.Furthermore, those skilled in the art, do not depart under concept of the present invention and equal scope, the scope of claims must explain to comprise the embodiment of the present invention and other distortion widely.
Claims (9)
1. an amorphous silicon is integrated gate driver circuit, comprise a plurality of shift registers, each shift register is in order to receive a clock signal and a start signal and to export a gate drive signal to drive a pixel column, and this clock signal switches between a high level voltage and a low level voltage;
Wherein this clock signal is more in close proximity at least one in electrical level rising edge and level trailing edge edge, first switches to second low level voltage lower than this low level voltage.
2. amorphous silicon as claimed in claim 1 is integrated gate driver circuit, wherein the difference of this low level voltage and this second low level voltage be no more than this high level voltage and this low level voltage difference 1/2.
3. amorphous silicon as claimed in claim 1 is integrated gate driver circuit, and wherein the difference of this low level voltage and this second low level voltage is less than 10V.
4. amorphous silicon as claimed in claim 1 is integrated gate driver circuit, and wherein the time span of this second low level voltage is less than 10 μ s.
5. an amorphous silicon is integrated gate driver circuit, comprise a plurality of shift registers, each shift register is in order to receive a clock signal and a start signal and to export a gate drive signal to drive a pixel column, and this clock signal switches between a high level voltage and a low level voltage
Wherein this clock signal first switches to one second low level voltage by this low level voltage in next-door neighbour electrical level rising edge and switches to this high level voltage again, and in next-door neighbour level decline edge, first by this high level voltage, switch to one the 3rd low level voltage and switch to again this low level voltage
Wherein this second low level voltage and the 3rd low level voltage are all lower than this low level voltage.
6. amorphous silicon as claimed in claim 5 is integrated gate driver circuit, and wherein 1/2 of the neither difference over this high level voltage and this low level voltage of the difference of the difference of this low level voltage and this second low level voltage and this low level voltage and the 3rd low level voltage.
7. amorphous silicon as claimed in claim 5 is integrated gate driver circuit, and wherein the difference of the difference of this low level voltage and this second low level voltage and this low level voltage and the 3rd low level voltage is not less than 10V.
8. amorphous silicon as claimed in claim 5 is integrated gate driver circuit, and wherein the time span of the time span of this second low level voltage and the 3rd level voltage is less than respectively 10 μ s.
9. the amorphous silicon as described in as arbitrary in claim 5 to 8 is integrated gate driver circuit, and wherein this second low level voltage equals the 3rd level voltage.
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| CN201210214875.2A CN103514843A (en) | 2012-06-25 | 2012-06-25 | Amorphous silicon integration grid driving circuit |
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| CN201210214875.2A CN103514843A (en) | 2012-06-25 | 2012-06-25 | Amorphous silicon integration grid driving circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105869601A (en) * | 2016-06-22 | 2016-08-17 | 京东方科技集团股份有限公司 | Grid driving method and circuit and display device comprising grid driving circuit |
| WO2017185590A1 (en) * | 2016-04-26 | 2017-11-02 | 京东方科技集团股份有限公司 | Shift register unit, gate driving circuit and driving method therefor, and display device |
| CN111445876A (en) * | 2020-04-22 | 2020-07-24 | Tcl华星光电技术有限公司 | GOA driving unit |
| CN115410506A (en) * | 2021-05-28 | 2022-11-29 | 北京京东方显示技术有限公司 | Display panel and display device |
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2012
- 2012-06-25 CN CN201210214875.2A patent/CN103514843A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2017185590A1 (en) * | 2016-04-26 | 2017-11-02 | 京东方科技集团股份有限公司 | Shift register unit, gate driving circuit and driving method therefor, and display device |
| US10217391B2 (en) | 2016-04-26 | 2019-02-26 | Boe Technology Group Co., Ltd. | Shift register unit, gate driving circuit and driving method thereof, and display apparatus |
| CN105869601A (en) * | 2016-06-22 | 2016-08-17 | 京东方科技集团股份有限公司 | Grid driving method and circuit and display device comprising grid driving circuit |
| CN105869601B (en) * | 2016-06-22 | 2019-05-03 | 京东方科技集团股份有限公司 | Grid drive method and circuit and display device including gate driving circuit |
| CN111445876A (en) * | 2020-04-22 | 2020-07-24 | Tcl华星光电技术有限公司 | GOA driving unit |
| WO2021212562A1 (en) * | 2020-04-22 | 2021-10-28 | Tcl华星光电技术有限公司 | Goa driving unit |
| CN115410506A (en) * | 2021-05-28 | 2022-11-29 | 北京京东方显示技术有限公司 | Display panel and display device |
| WO2022247135A1 (en) * | 2021-05-28 | 2022-12-01 | 京东方科技集团股份有限公司 | Display panel and display device |
| US12087204B2 (en) | 2021-05-28 | 2024-09-10 | Beijing Boe Display Technology Co., Ltd. | Display panel and display device |
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Application publication date: 20140115 |