CN103514617A - Method for improving redundancy graph filling rate in long and narrow area - Google Patents
Method for improving redundancy graph filling rate in long and narrow area Download PDFInfo
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- CN103514617A CN103514617A CN201310491943.4A CN201310491943A CN103514617A CN 103514617 A CN103514617 A CN 103514617A CN 201310491943 A CN201310491943 A CN 201310491943A CN 103514617 A CN103514617 A CN 103514617A
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Abstract
The invention discloses a method for improving redundancy graph filling rate in a long and narrow area. The method comprises the following steps: step S1, carrying out primary conventional redundancy graph offset interleaving filling on a domain; step S2, screening the area, which is not sufficiently filled, of the redundancy graph; step S3, carrying out redundancy graph offset interleaving filling on the area, which is not sufficiently filled, of the redundancy graph; and step S4, repeating the steps S2 and S3 till the redundancy graph is sufficiently filled. The redundancy graph of the domain obtained by using the method for improving redundancy graph filling rate in the long and narrow area is not only sufficiently filled and uniform in pattern density distribution, but also further improves the uniformity in later chemical mechanical grinding or etching, and the reliability of a semiconductor is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of method that improves long and narrow region redundant pattern filling rate.
Background technology
At present, in integrated circuit fabrication process, in order to improve the homogeneity of cmp and etching, conventionally understand in the following technique of 0.25 μ m, and need, in the functional layer of cmp or etching, to add redundant pattern.In order to strengthen the technique performance of described redundant pattern, common redundant pattern filling mode is one of them direction along X or Y by described redundant pattern, or both direction offset staggered is filled.
But traditional redundant pattern filling mode is to carry out disposable filling for the redundant pattern of same type.Significantly, for long and narrow fill area, owing to having exceeded the filling scope that redundant pattern allows after partial redundance map migration, and cannot fill, and then cause the redundant pattern of described redundant pattern fill area to fill insufficient, make described cmp or etching technics homogeneity poor, reduce the reliability of semiconductor devices.
Therefore the problem existing for prior art, this case designer relies on the industry experience for many years of being engaged in, and active research improvement, so there has been a kind of method that improves long and narrow region redundant pattern filling rate of the present invention.
Summary of the invention
The present invention be directed in prior art, described traditional redundant pattern fill method be easy to cause cmp or etching technics homogeneity poor, and the defects such as reliability that reduce semiconductor devices provide a kind of method that improves long and narrow region redundant pattern filling rate.
For realizing the present invention's object, the invention provides a kind of method that improves long and narrow region redundant pattern filling rate, described method comprises:
Execution step S1: the described domain with redundant pattern is carried out to disposable traditional redundant pattern offset staggered and fill;
Execution step S2: the inabundant fill area of screening described redundant pattern;
Execution step S3: the inabundant fill area to described redundant pattern is carried out the filling of redundant pattern offset staggered again;
Execution step S4: repeating step S2, S3, until described redundant pattern is all fully filled.
Alternatively, the minimum spacing that described domain defines in design rule is d, and the functional layer pattern that described domain formed is for chemical mechanical milling tech or etching technics.
Alternatively, form described redundant pattern fill area between described functional layer pattern, the spacing between described redundant pattern fill area and described functional layer pattern is a, and a >=d.
Alternatively, the spacing between described redundant pattern fill area and described functional layer pattern is a, and 5nm≤a≤10 μ m.
Alternatively, the region of the described not redundant pattern of abundant filling is abundant fill area.
Alternatively, described inabundant fill area comprises redundant pattern that at least one is not fully filled.
Alternatively, the spacing of described inabundant fill area and described adjacent redundant pattern is b, and b >=d.
Alternatively, the spacing of described inabundant fill area and described adjacent redundant pattern is b, and 5nm≤b≤10 μ m.
Alternatively, the offset staggered that described redundant pattern is carried out is filled to one of them direction along X or Y by described redundant pattern, or carries out offset staggered filling along X, Y both direction simultaneously.
In sum, the redundant pattern of the domain that the method by the long and narrow region of raising of the present invention redundant pattern filling rate obtains is not only filled fully, pattern density is evenly distributed, and further improve the homogeneity of subsequent chemistry mechanical lapping or etching, strengthen the reliability of semiconductor devices.
Accompanying drawing explanation
Figure 1 shows that the present invention improves the process flow diagram of the method for long and narrow region redundant pattern filling rate;
The concrete interim structural representation of implementing of the method for Fig. 2 (a)～Fig. 2 (c) long and narrow region redundant pattern filling rate for the present invention improves.
Embodiment
By describe in detail the invention technology contents, structural attitude, reached object and effect, below in conjunction with embodiment and coordinate accompanying drawing to be described in detail.
Refer to Fig. 1, Figure 1 shows that the present invention improves the process flow diagram of the method for long and narrow region redundant pattern filling rate.The method of the long and narrow region of described raising redundant pattern filling rate comprises:
Execution step S1: the described domain with redundant pattern is carried out to disposable traditional redundant pattern offset staggered and fill;
Execution step S2: the inabundant fill area of screening described redundant pattern;
Execution step S3: the inabundant fill area to described redundant pattern is carried out the filling of redundant pattern offset staggered again;
Execution step S4: repeating step S2, S3, until described redundant pattern is all fully filled.
In order to set forth more intuitively the present invention's technical scheme, highlight the present invention's technique effect, tiredly take embodiment and set forth as example, but should not be considered as the restriction to the technical scheme of the invention.
Refer to Fig. 2 (a)～Fig. 2 (c), and in conjunction with consulting Fig. 1, the concrete interim structural representation of implementing of the method for Fig. 2 (a)～Fig. 2 (c) long and narrow region redundant pattern filling rate for the present invention improves.The method of the long and narrow region of described raising redundant pattern filling rate comprises:
Execution step S1: the described domain 1 with redundant pattern 11 is carried out to disposable traditional redundant pattern offset staggered and fill;
Nonrestrictive enumerating, the minimum spacing that described domain 1 defines in design rule is d, the functional layer pattern 12 that described domain 1 is formed is for chemical mechanical milling tech or etching technics.Between described functional layer pattern 12, just form described redundant pattern fill area 13, the spacing between described redundant pattern fill area 13 and described functional layer pattern 12 is a, and a >=d.Preferably, 5nm≤a≤10 μ m.In the present embodiment, the described domain 1 with redundant pattern 11 is carried out to the conventional filling mode that process that disposable traditional redundant pattern offset staggered fills can be grasped for those skilled in the art.
Execution step S2: the inabundant fill area 14 of screening described redundant pattern 11;
Particularly, in the described domain 1 with redundant pattern 11 being carried out to the process of disposable traditional redundant pattern offset staggered filling, the redundant pattern 11 that is positioned at described redundant pattern fill area 13 is fully filled; Redundant pattern 11 in non-described redundant pattern fill area 13 is not fully filled, and described in definition not fully the redundant pattern 11 region of fillings be abundant fill area 14.Described abundant fill area 14 comprises at least one not redundant pattern 11 of abundant filling.Described inabundant fill area 14 is b with the spacing of described adjacent redundant pattern 11, and b >=d.Preferably, 5nm≤b≤10 μ m.As those skilled in the art, to hold intelligibly, described redundant pattern 11 can not be positioned at described redundant pattern fill area 13 because of technologic skew.
Execution step S3: the inabundant fill area 14 to described redundant pattern 11 is carried out the filling of redundant pattern offset staggered again;
As concrete embodiment, preferably, it can be one of them direction along X or Y by described redundant pattern 11 that the offset staggered that described redundant pattern 11 is carried out is filled, or carries out offset staggered filling along X, Y both direction simultaneously.
Execution step S4: repeating step S2, S3, until described redundant pattern 11 is all fully filled.
Significantly, the redundant pattern 11 of the domain 1 that the method by the long and narrow region of raising of the present invention redundant pattern filling rate obtains is not only filled fully, pattern density is evenly distributed, and further improve the homogeneity of subsequent chemistry mechanical lapping or etching, strengthen the reliability of semiconductor devices.
In sum, the redundant pattern of the domain that the method by the long and narrow region of raising of the present invention redundant pattern filling rate obtains is not only filled fully, pattern density is evenly distributed, and further improve the homogeneity of subsequent chemistry mechanical lapping or etching, strengthen the reliability of semiconductor devices.
Those skilled in the art all should be appreciated that, in the situation that not departing from the spirit or scope of the present invention, can carry out various modifications and variations to the present invention.Thereby, if when any modification or modification fall in the protection domain of appended claims and equivalent, think that the present invention contains these modifications and modification.
Claims (9)
1. improve a method for long and narrow region redundant pattern filling rate, it is characterized in that, described method comprises:
Execution step S1: described domain is carried out to disposable traditional redundant pattern offset staggered and fill;
Execution step S2: the inabundant fill area of screening described redundant pattern;
Execution step S3: the inabundant fill area to described redundant pattern is carried out the filling of redundant pattern offset staggered again;
Execution step S4: repeating step S2, S3, until described redundant pattern is all fully filled.
2. the method for the long and narrow region of raising as claimed in claim 1 redundant pattern filling rate, is characterized in that, the minimum spacing that described domain defines in design rule is d, and the functional layer pattern that described domain formed is for chemical mechanical milling tech or etching technics.
3. the method for the long and narrow region of raising as claimed in claim 2 redundant pattern filling rate, it is characterized in that, between described functional layer pattern, form described redundant pattern fill area, the spacing between described redundant pattern fill area and described functional layer pattern is a, and a >=d.
4. the method for the long and narrow region of raising as claimed in claim 3 redundant pattern filling rate, is characterized in that, the spacing between described redundant pattern fill area and described functional layer pattern is a, and 5nm≤a≤10 μ m.
5. the method for the long and narrow region of raising as claimed in claim 2 redundant pattern filling rate, is characterized in that, the region of the described not redundant pattern of abundant filling is abundant fill area.
6. the method for the long and narrow region of raising as claimed in claim 5 redundant pattern filling rate, is characterized in that, described inabundant fill area comprises redundant pattern that at least one is not fully filled.
7. the method for the long and narrow region of raising as claimed in claim 6 redundant pattern filling rate, is characterized in that, the spacing of described inabundant fill area and described adjacent redundant pattern is b, and b >=d.
8. the method for the long and narrow region of raising as claimed in claim 7 redundant pattern filling rate, is characterized in that, the spacing of described inabundant fill area and described adjacent redundant pattern is b, and 5nm≤b≤10 μ m.
9. the method for the long and narrow region of raising as claimed in claim 2 redundant pattern filling rate, it is characterized in that, the offset staggered that described redundant pattern is carried out is filled to one of them direction along X or Y by described redundant pattern, or carries out offset staggered filling along X, Y both direction simultaneously.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310491943.4A CN103514617A (en) | 2013-10-18 | 2013-10-18 | Method for improving redundancy graph filling rate in long and narrow area |
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| CN201310491943.4A CN103514617A (en) | 2013-10-18 | 2013-10-18 | Method for improving redundancy graph filling rate in long and narrow area |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106096087A (en) * | 2016-05-31 | 2016-11-09 | 上海华虹宏力半导体制造有限公司 | Capture filling graph method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080176343A1 (en) * | 2007-01-22 | 2008-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method For Smart Dummy Insertion To Reduce Run Time And Dummy Count |
| CN102130096A (en) * | 2010-01-15 | 2011-07-20 | 中国科学院微电子研究所 | Test structure and test method for coupling capacitance of metal redundant fillers in integrated circuit |
| CN102446756A (en) * | 2011-11-02 | 2012-05-09 | 上海华力微电子有限公司 | Method for improving homogeneity of figure density of metal layer of silicon chip |
| CN102468134A (en) * | 2010-11-16 | 2012-05-23 | 上海华虹Nec电子有限公司 | Method for adjusting chip graph density using redundancy graph insertion, |
| CN103049588A (en) * | 2011-10-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Filling method for redundant graphs |
-
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080176343A1 (en) * | 2007-01-22 | 2008-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method For Smart Dummy Insertion To Reduce Run Time And Dummy Count |
| CN102130096A (en) * | 2010-01-15 | 2011-07-20 | 中国科学院微电子研究所 | Test structure and test method for coupling capacitance of metal redundant fillers in integrated circuit |
| CN102468134A (en) * | 2010-11-16 | 2012-05-23 | 上海华虹Nec电子有限公司 | Method for adjusting chip graph density using redundancy graph insertion, |
| CN103049588A (en) * | 2011-10-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Filling method for redundant graphs |
| CN102446756A (en) * | 2011-11-02 | 2012-05-09 | 上海华力微电子有限公司 | Method for improving homogeneity of figure density of metal layer of silicon chip |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106096087A (en) * | 2016-05-31 | 2016-11-09 | 上海华虹宏力半导体制造有限公司 | Capture filling graph method |
| CN106096087B (en) * | 2016-05-31 | 2019-08-13 | 上海华虹宏力半导体制造有限公司 | Capture filling graph method |
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