CN103489789A - Ceramic substrate dual surface photolithography technique and structure - Google Patents
Ceramic substrate dual surface photolithography technique and structure Download PDFInfo
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- CN103489789A CN103489789A CN201210193526.7A CN201210193526A CN103489789A CN 103489789 A CN103489789 A CN 103489789A CN 201210193526 A CN201210193526 A CN 201210193526A CN 103489789 A CN103489789 A CN 103489789A
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- ceramic substrate
- mask plate
- dual surface
- bracing frame
- support frame
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- 239000000758 substrate Substances 0.000 title claims abstract description 123
- 239000000919 ceramic Substances 0.000 title claims abstract description 121
- 230000009977 dual effect Effects 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims description 23
- 238000000206 photolithography Methods 0.000 title abstract 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 238000001459 lithography Methods 0.000 claims description 21
- 238000004140 cleaning Methods 0.000 claims description 9
- 239000010410 layer Substances 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 238000011161 development Methods 0.000 claims description 7
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- 230000007246 mechanism Effects 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000005253 cladding Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 230000018109 developmental process Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 4
- 239000000047 product Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 3
- 239000004568 cement Substances 0.000 description 2
- 238000004100 electronic packaging Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 238000012797 qualification Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- -1 after having changed Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/4807—Ceramic parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The invention discloses a ceramic substrate dual surface photolithography structure. The dual surface photolithography structure comprises a supporting frame, an upper mask plate is arranged at the upper end of the supporting frame, a lower mask plate is arranged at the lower end of the supporting frame, two exposure devices are arranged above the upper mask plate and below the lower mask plate respectively, a ceramic substrate supporting rack is arranged between the upper mask plate and the lower mask plate, a ceramic substrate is arranged on the ceramic substrate supporting rack, and the center positions of the upper mask plate, the ceramic substrate and the lower mask plate correspond vertically. According to the ceramic substrate dual surface photolithography structure, the exposure devices are simultaneously arranged above the upper mask plate and below the lower mask plate respectively, and the upper surface and the lower surface of the ceramic substrate are exposed simultaneously through the upper exposure device and the lower exposure device, so that absolute inosculation of metal graph positions on the upper surface and the lower surface of the ceramic substrate is ensured, offset can not happen, therefore, the quality of the ceramic substrate is ensured, the yield of the product is improved, production efficiency can be effectively improved, and production cost of an enterprise can be reduced by the adoption of the mode.
Description
Technical field
The present invention relates to a kind of photoetching process, particularly a kind ofly at the ceramic substrate upper and lower surface, carry out the method for photoetching and realize the photolithographic structures of the method.
Background technology
Modern microelectric technique undergoes an unusual development rapidly, and particularly various opto-electronic devices are gradually to future developments such as microminiaturization, large scale integration, high efficiency, high reliability.But the raising along with the electronic system integrated level, its power density increases thereupon, electronic component and entire system work produce the heat rising, the rising of system works temperature can cause performance of semiconductor device deterioration, device destruction, layering etc., even can make the chip of encapsulation burn, therefore effective Electronic Packaging must solve the heat dissipation problem of electronic system.
Electronic Packaging substrate used is a kind of base electronic component, and being mainly electronic devices and components and phase interconnection line thereof provides mechanical bearing support, air-tightness to protect and can be used as heat sink transition plate to chip cooling.That ceramic substrate has is high temperature resistant, electrical insulation capability is high, dielectric constant and dielectric loss is low, thermal conductivity is large, chemical stability is good, the advantage such as close with the thermal coefficient of expansion of element; and can play stronger protective effect to opto-electronic device, thereby all obtained application very widely in fields such as Aeronautics and Astronautics and military engineerings.In the encapsulation process of chip, the wiring of usually need to metallizing on the surface of substrate forms metallic pattern, so that the connecting electronic components and parts.
Along with the future development of electronic device to miniaturization, microminiaturization, the upper and lower surface of ceramic substrate all needs the wiring of metallizing usually.Mode at present commonly used is just first in the enterprising row metal wiring of the upper surface of ceramic substrate, and then this ceramic substrate that reverses, carry out metal line at its lower surface, adopt this mode to have a shortcoming, easily occur exactly the position skew will making like this metallic pattern of the upper and lower surface of ceramic substrate deviation occur in the process of ceramic substrate reversion, and then the quality of meeting multi-product impacts, tend to produce a large amount of defective productss, conforming product rate is lower, and the production cost of enterprise is higher.
Summary of the invention
For above-mentioned the deficiencies in the prior art, the technical problem to be solved in the present invention is to provide a kind ofly can carry out the photoetching process of dual surface lithography simultaneously to ceramic substrate.
For solving the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of ceramic substrate dual surface lithography technique, it comprises the steps:
1) require to make corresponding upper mask plate and lower mask plate according to ceramic substrate upper and lower surface metallic pattern;
2) ceramic substrate is carried out to two-sided spattering and cross, and photoresist on all being coated with on the upper and lower surface of ceramic substrate;
3) upper mask plate is arranged on to the ceramic substrate top, lower mask plate is arranged on the ceramic substrate below, by a location device, makes upper mask plate, ceramic substrate, lower mask plate three's center corresponding up and down;
4) above upper mask plate, lower mask plate below an exposure device is set respectively, respectively the upper and lower surface of ceramic substrate is carried out to exposure-processed by upper and lower two exposure devices;
5) ceramic substrate after exposure is carried out to development treatment, and cleaned, the ceramic substrate plating metal on surface layer after cleaning, finally used acetone soln to be cleaned the ceramic substrate of metal cladding.
Preferably, in step 2) at first photoresist is dropped on ceramic substrate, thereby then make the ceramic substrate High Rotation Speed that photoresist is coated on ceramic substrate uniformly.
Preferably, in step 5) in adopt plasma cleaning method cleaning ceramic substrate.
Preferably, in step 5) at the metal level of ceramic substrate plated surface, be gold layer, platinum layer or titanium coating.
Preferably, in step 5) at the metal level of ceramic substrate plated surface, can be one or more layers.
The invention also discloses a kind of ceramic substrate dual surface lithography structure that realizes above-mentioned dual surface lithography technique, this dual surface lithography structure comprises a support frame, the upper end of described support frame is provided with mask plate, the lower end of described support frame is provided with lower mask plate, the top of described upper mask plate and the below of described lower mask plate respectively are provided with an exposure device, described upper mask plate, be provided with a ceramic substrate bracing frame between lower mask plate, described ceramic substrate bracing frame is provided with ceramic substrate, described upper mask plate, ceramic substrate, lower mask plate three's center is corresponding up and down.
Preferably, described ceramic substrate bracing frame both sides respectively are provided with a guide rail, and described guide rail is fixed on described support frame, and described ceramic substrate bracing frame and described guide rail are slidably matched.
Preferably, described support frame is provided with for the ceramic substrate bracing frame is carried out to spacing position-limit mechanism.
Technique scheme has following beneficial effect: this ceramic substrate dual surface lithography technique is above ceramic substrate, below arranges mask plate simultaneously, and make upper and lower mask plate relative with the center of ceramic substrate, then by upper and lower two exposure devices, the upper and lower surface of ceramic substrate is exposed simultaneously, the position that so just can guarantee ceramic substrate upper and lower surface metallic pattern is definitely identical, not there will be skew, thereby can effectively guarantee the quality of ceramic substrate, improve the qualification rate of product, adopt this mode also can effectively enhance productivity, reduce enterprise's production cost.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of specification, below with preferred embodiment of the present invention and coordinate accompanying drawing to be described in detail as follows.The specific embodiment of the present invention is provided in detail by following examples and accompanying drawing thereof.
The accompanying drawing explanation
The structured flowchart that Fig. 1 is dual surface lithography structure embodiment of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are described in detail.
As shown in Figure 1, this dual surface lithography structure comprises a support frame 1, the upper end of support frame 1 is provided with mask plate 2, and the lower end of support frame 1 is provided with lower mask plate 3, and upper mask plate 2, lower mask plate 3 require to make according to ceramic substrate upper and lower surface metallic pattern respectively.The top of upper mask plate 2 is provided with an exposure device 4, and the below of lower mask plate 3 is provided with an exposure device 5.Also be provided with a ceramic substrate bracing frame 7 between upper mask plate 2, lower mask plate 3, ceramic substrate bracing frame 7 generally is positioned at the centre position of support frame 1, ceramic substrate bracing frame 7 is provided with ceramic substrate 6, and upper mask plate 2, ceramic substrate 6, lower mask plate 3 threes' center should be corresponding up and down.
In order to facilitate the replacing of ceramic substrate, the both sides of ceramic substrate bracing frame 7 respectively are provided with a guide rail, guide rail is fixed on support frame 1, ceramic substrate bracing frame 7 is slidably matched with guide rail, only ceramic substrate bracing frame 7 can need be changed along the outside extraction of guide rail during so each replacing ceramic substrate, after having changed, ceramic substrate bracing frame 7 can be reinserted and gets final product along guide rail.For the ease of location, support frame 1 is provided with position-limit mechanism, this position-limit mechanism is spacing for the ceramic substrate bracing frame is carried out, as long as can guarantee that mask plate 2, ceramic substrate 6, lower mask plate 3 threes' center is corresponding up and down, position-limit mechanism can adopt various ways.
While adopting this dual surface lithography structure to carry out dual surface lithography to ceramic substrate, can at first according to ceramic substrate upper and lower surface metallic pattern, require to make corresponding upper mask plate 2 and lower mask plate 3, and be fixed on support frame 1.Then ceramic substrate 6 being carried out to two-sided spattering crosses, and photoresist on all being coated with on the upper and lower surface of ceramic substrate 6, at first coating drops in it on ceramic substrate while carving optical cement, then makes the ceramic substrate High Rotation Speed, so just can make photoresist be coated on ceramic substrate uniformly.Then by coated quarter optical cement ceramic substrate 6 be arranged on ceramic substrate bracing frame 7, and adjust the position of ceramic substrate bracing frame 7, make mask plate, ceramic substrate, lower mask plate three's center corresponding up and down.Then by upper and lower two exposure devices 4, 5 carry out exposure-processed to the upper and lower surface of ceramic substrate respectively, again the ceramic substrate after exposure is carried out to development treatment, employing plasma cleaning method cleaning ceramic substrate after development treatment completes, and then the ceramic substrate plating metal on surface layer after cleaning, the metal level of ceramic substrate plated surface is gold layer, platinum layer or titanium coating, the metal level of ceramic substrate plated surface can be one or more layers, finally use acetone soln to be cleaned the ceramic substrate of metal cladding, wash photoresist, the ceramic substrate upper and lower surface can form metallic pattern.
This ceramic substrate dual surface lithography method above ceramic substrate, below mask plate is set simultaneously, and make upper and lower mask plate relative with the center of ceramic substrate, then by upper and lower two exposure devices, the upper and lower surface of ceramic substrate is exposed simultaneously, the position that so just can guarantee ceramic substrate upper and lower surface metallic pattern is definitely identical, not there will be skew, thereby can effectively guarantee the quality of ceramic substrate, improve the qualification rate of product, adopt this mode also can effectively enhance productivity, reduce enterprise's production cost.
Above ceramic substrate dual surface lithography technique and the structure that the embodiment of the present invention is provided is described in detail; for one of ordinary skill in the art; thought according to the embodiment of the present invention; all will change in specific embodiments and applications; in sum; this description should not be construed as limitation of the present invention, and all any changes of making according to design philosophy of the present invention are all within protection scope of the present invention.
Claims (8)
1. a ceramic substrate dual surface lithography technique, is characterized in that, it comprises the steps:
1) require to make corresponding upper mask plate and lower mask plate according to ceramic substrate upper and lower surface metallic pattern;
2) ceramic substrate is carried out to two-sided spattering and cross, and photoresist on all being coated with on the upper and lower surface of ceramic substrate;
3) upper mask plate is arranged on to the ceramic substrate top, lower mask plate is arranged on the ceramic substrate below, by a location device, makes upper mask plate, ceramic substrate, lower mask plate three's center corresponding up and down;
4) above upper mask plate, lower mask plate below an exposure device is set respectively, respectively the upper and lower surface of ceramic substrate is carried out to exposure-processed by upper and lower two exposure devices;
5) ceramic substrate after exposure is carried out to development treatment, and cleaned, the ceramic substrate plating metal on surface layer after cleaning, finally used acetone soln to be cleaned the ceramic substrate of metal cladding.
2. ceramic substrate dual surface lithography technique according to claim 1, is characterized in that: in step 2) at first photoresist is dropped on ceramic substrate, thus then make the ceramic substrate High Rotation Speed that photoresist is coated on ceramic substrate uniformly.
3. ceramic substrate dual surface lithography technique according to claim 1, is characterized in that: in step 5) in adopt plasma cleaning method cleaning ceramic substrate.
4. ceramic substrate dual surface lithography technique according to claim 1, is characterized in that: in step 5) at the metal level of ceramic substrate plated surface, be gold layer, platinum layer or titanium coating.
5. ceramic substrate dual surface lithography technique according to claim 1, is characterized in that: in step 5) at the metal level of ceramic substrate plated surface, can be one or more layers.
6. a ceramic substrate dual surface lithography structure, it is characterized in that: it comprises a support frame, the upper end of described support frame is provided with mask plate, the lower end of described support frame is provided with lower mask plate, the top of described upper mask plate and the below of described lower mask plate respectively are provided with an exposure device, be provided with a ceramic substrate bracing frame between described upper mask plate, lower mask plate, described ceramic substrate bracing frame is provided with ceramic substrate, and described upper mask plate, ceramic substrate, lower mask plate three's center is corresponding up and down.
7. ceramic substrate dual surface lithography structure according to claim 6, it is characterized in that: described ceramic substrate bracing frame both sides respectively are provided with a guide rail, and described guide rail is fixed on described support frame, and described ceramic substrate bracing frame and described guide rail are slidably matched.
8. ceramic substrate dual surface lithography structure according to claim 6, it is characterized in that: described support frame is provided with for the ceramic substrate bracing frame is carried out to spacing position-limit mechanism.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210193526.7A CN103489789A (en) | 2012-06-13 | 2012-06-13 | Ceramic substrate dual surface photolithography technique and structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210193526.7A CN103489789A (en) | 2012-06-13 | 2012-06-13 | Ceramic substrate dual surface photolithography technique and structure |
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| Publication Number | Publication Date |
|---|---|
| CN103489789A true CN103489789A (en) | 2014-01-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210193526.7A Pending CN103489789A (en) | 2012-06-13 | 2012-06-13 | Ceramic substrate dual surface photolithography technique and structure |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104045055A (en) * | 2014-06-18 | 2014-09-17 | 上海先进半导体制造股份有限公司 | Manufacturing method of cover plate |
| CN105068387A (en) * | 2015-07-28 | 2015-11-18 | 江苏影速光电技术有限公司 | Laser direct writing vertical double-sided exposure system |
| WO2019241945A1 (en) * | 2018-06-21 | 2019-12-26 | 日本光电子化学株式会社 | Method for simultaneously forming patterns on both sides of transparent substrate |
| CN113777886A (en) * | 2021-08-17 | 2021-12-10 | 上海富乐华半导体科技有限公司 | Method for patterning ceramic substrate |
| CN113811091A (en) * | 2021-10-08 | 2021-12-17 | 中紫半导体科技(东莞)有限公司 | Through hole metallization method of fine ceramic circuit board |
-
2012
- 2012-06-13 CN CN201210193526.7A patent/CN103489789A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104045055A (en) * | 2014-06-18 | 2014-09-17 | 上海先进半导体制造股份有限公司 | Manufacturing method of cover plate |
| CN105068387A (en) * | 2015-07-28 | 2015-11-18 | 江苏影速光电技术有限公司 | Laser direct writing vertical double-sided exposure system |
| WO2019241945A1 (en) * | 2018-06-21 | 2019-12-26 | 日本光电子化学株式会社 | Method for simultaneously forming patterns on both sides of transparent substrate |
| CN113777886A (en) * | 2021-08-17 | 2021-12-10 | 上海富乐华半导体科技有限公司 | Method for patterning ceramic substrate |
| CN113811091A (en) * | 2021-10-08 | 2021-12-17 | 中紫半导体科技(东莞)有限公司 | Through hole metallization method of fine ceramic circuit board |
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Application publication date: 20140101 |