CN103487648A - Sigma-delta PLL frequency measuring circuit and method - Google Patents

Abstract

The invention provides a sigma-delta PLL frequency measuring circuit and method. The circuit comprises a rectifying circuit, a phase discriminator, a loop filter, an ADC and a delay link which are sequentially arranged from the input end. The output end of the delay link is fed back and input to the phase discriminator through a counter. The frequency measuring method comprises the steps that after the rectifying circuit filters and amplifies a signal to be detected, the signal to be detected is converted into a square signal with the frequency same as that of the signal to be detected; the phase discriminator measures the zero crossing point time difference of the square signal and an output signal of the counter, and a pulse current signal with the output area and the time in a direct proportion; after the integration and the filtering are carried out on an output current of the phase discriminator through the loop filter, the output current is converted into a voltage signal; the ADC converts analog voltage output by the loop filter into a digital signal; the delay link delays the digital signal output by the ADC, and therefore the frequency of the signal to be detected is determined; a counter output signal with the clock period and the delayed digital signal in a direct proportion is generated by the counter, and is output to the phase discriminator. The anti-noise capacity is strong in the process of measuring the frequency, the resolution ratio is high, and the frequency measurement can be achieved easily.

Description

Sigma-delta PLL frequency measurement circuit and method

Technical field

The present invention relates to electronics and time and frequency measurement field, particularly a kind of sigma-delta (sigma-delta) PLL (Phase Locked Loop, phaselocked loop) frequency measurement circuit and method.

Background technology

In electronic technology, frequency is one of basic parameter always, and with measurement scheme, the measurement result of many electric parameters, very close relationship is arranged, so the measurement of frequency is also particularly important.In recent years, development along with electronic information technology, the frequency of usining is all improving constantly as the crystal oscillator of output signal and the precision of resonant transducer, applies also more and more extensively, and the research and development of the low noise frequency measurement circuit be complementary with it also seem more urgent.

On domestic and international market, the ultimate principle of frequency measurement circuit commonly used has three classes at present: (1) is by carrying out the frequency of Fourier transform signal measuring period to measured signal, (2) within the gate time of standard, the number of cycles of tested frequency signal counted and drawn tested frequency values, (3) frequency measurement circuit based on phaselocked loop, the characteristic of utilizing voltage controlled oscillator (VCO) control signal to be directly proportional to frequency realizes frequency identification; Wherein, (1) class technology possesses certain noiseproof feature, but inevitably to carry out blocking of time domain in the Fourier transform process, this truncated process will produce the leakage of frequency-region signal, frequency domain information after causing converting can not completely reflect former time-domain signal characteristic, so the precision of its measurement result is poor.(2) class technology can complete frequency measurement and Digital output simultaneously, and the sample frequency of this system is only the twice of measured signal frequency, to over-sampling rate without high request too, measurement is convenient, reading is direct, but the quantization error that exists counting to cause in this technology, the raising of restriction frequency-measurement accuracy; Although have improved multi-period synchronizing method and delay chain method to be limited quantization error, but multi-period synchronizing method is to take the sacrificial system bandwidth as cost, and the delay chain method is high to the accuracy requirement of delay cell, realize that difficulty is larger, and have the problems such as delay chain length distribution inequality and delay jitter, make its realistic accuracy far below theoretical value.(3) class technology first locks the measured signal frequency by phaselocked loop, the voltage signal that output is directly proportional to measured signal, transfer voltage signal to numerical frequency by A-D converter (ADC) again, to treat that in two steps measured frequency transfers digital signal to, phaselocked loop Measuring Frequency Method advantage is that circuit is simple, is easy to realize, but the VCO in phaselocked loop self can introduce phase noise, and there is non-linear and temperature sensitivity in VCO, and this will affect the precision of final frequency measurement.

In sum, the frequency measurement method generally used at present all exists noise large, and the problem that resolution is low is difficult to adapt to the requirement that the high precision frequency of new crystal oscillator and resonant transducer reads.

Summary of the invention

The object of the present invention is to provide that a kind of noise resisting ability is strong, resolution is high, be easy to the sigma-delta PLL frequency measurement circuit and the method that realize.

The technical solution that realizes the object of the invention is:

A kind of sigma-delta PLL frequency measurement circuit, comprise the shaping circuit, phase detector, loop filter, ADC and the delay link that start to arrange in turn from input end, and the output terminal of delay link process counter feed back input is to phase detector, wherein: shaping circuit, after measured signal filtering, amplifying, transfer the square-wave signal V of same frequency to _out; Phase detector, measure the measured signal V after shaping _outwith counter output signal C _outthe zero crossing mistiming, and output area and mistiming e _nthe pulsed current signal I be directly proportional _out; Loop filter, to the output current I of phase detector _outcarry out integration and filtering, and transfer it to voltage signal; ADC, transfer the analog voltage of loop filter output to digital signal N; Delay link, the digital signal N that ADC is exported carries out the delay of a clock period; Counter, the counter output signal C that the digital signal N after producing the clock period and postponing is directly proportional _out, and by this counter output signal C _outthe input phase detector.

A kind of sigma-delta PLL frequency measurement method, step is as follows:

Step 1, by after measured signal filtering, amplifying, transfer the square-wave signal V of same frequency by shaping circuit to _out;

Step 2, phase detector is measured the measured signal V after shaping _outoutput signal C with counter _outthe mistiming e of zero crossing _n, and output area and mistiming e _nthe pulsed current signal I be directly proportional _out;

Step 3, the output current I of loop filter to phase detector _outcarry out integration and filtering, and transfer it to voltage signal;

Step 4, ADC transfers the analog voltage of loop filter output to digital signal N;

Step 5, delay link carries out the delay of a clock period to the digital signal N of ADC output, determines the frequency of measured signal according to the digital signal N after this delay;

Step 6, the counter output signal C that the digital signal N after counter produces the clock period and postpones is directly proportional _out, and by this counter output signal C _outmeasured signal V after input phase detector and shaping _outdiffered comparison.

Compared with prior art, remarkable advantage of the present invention is: (1) substitutes VCO, the extra phase noise of having avoided VCO to bring, non-linear and temperature sensitivity with counter; (2) transport function is the version of sigma-delta modulator-demodular unit, and the quantizing noise that counter can be brought is modulated to high-frequency region, shifts out outside the bandwidth range of measured signal, greatly improves the frequency measurement resolution in bandwidth range; Under constant prerequisite, can further improve the resolution performance at quantizing noise by improving the loop exponent number, there is very strong noise resisting ability; (3) simple in structure, flexibility ratio is large, lower to the requirement of device: at first less demanding for the crystal oscillator frequency value as the counter clock benchmark; In addition because ADC carries out digital-to-analog conversion to the DC voltage after integral element and filtering link, thus to the figure place of ADC and sampling rate also all without excessive demand.

The accompanying drawing explanation

Fig. 1 is the structural representation of sigma-delta PLL frequency measurement circuit of the present invention.

Fig. 2 is the waveform schematic diagram of signal in sigma-delta PLL frequency measurement method of the present invention.

Fig. 3 is the loop filter structure schematic diagram that adopts integrator cascade Feedforward version in sigma-delta PLL frequency measurement circuit of the present invention.

Fig. 4 is the first order feedforward path of having removed in sigma-delta PLL frequency measurement circuit of the present invention in integrator cascade Feedforward structure, and adds the structural representation after lead compensation.

Fig. 5 is the structural representation of filtering link in the sigma-delta PLL frequency measurement loop of different rank in the present invention, the structural representation that wherein (a) is filtering link in second order sigma-delta PLL frequency measurement loop, (b) be the structural representation of filtering link in three rank sigma-delta PLL frequency measurement loops, (c) be the structural representation of filtering link in quadravalence sigma-delta PLL frequency measurement loop.

Embodiment

Below in conjunction with drawings and the specific embodiments, the present invention is described in further detail.

In conjunction with Fig. 1, sigma-delta PLL frequency measurement circuit of the present invention, a closed loop negative feedback system on the whole, comprise the shaping circuit 100, phase detector 200, loop filter 300, ADC400 and the delay link 500 that start to arrange in turn from input end, and the output terminal of delay link 500 process counter 600 feed back inputs are to phase detector 200, wherein: shaping circuit 100, after measured signal filtering, amplifying, transfers the square-wave signal V of same frequency to _out; Phase detector 200, measure the measured signal V after shaping _outwith counter output signal C _outthe zero crossing mistiming, and output area and mistiming e _nthe pulsed current signal I be directly proportional _out; Loop filter 300, to the output current I of phase detector 200 _outcarry out integration and filtering, and transfer it to voltage signal; ADC400, transfer the analog voltage of loop filter 300 outputs to digital signal N; Delay link 500, the digital signal N that ADC400 is exported carries out the delay of a clock period; Counter 600, the counter output signal C that the digital signal N after producing the clock period and postponing is directly proportional _out, and by this counter output signal C _out input phase detector 200.

Sigma-delta PLL frequency measurement method of the present invention, mainly, by control counter 600 output signals, make counter 600 output signal C _outwith the measured signal V after shaping _outkeep homophase, thereby realize the solution mediation digitizing conversion of measured signal frequency simultaneously in a step.Consistent in order to maintain phase place, as at first to utilize phase detector 200 to measure after shaping measured signal V _outwith counter output signal C _outzero crossing mistiming e _n=t _n-τ _n, and to produce corresponding area be A _n=K _d* (t _n-τ _n) pulsed current signal I _outas shown in Figure 2, K wherein _dfor phase detector 200 gains, t _nfor the measured signal V after shaping _outthe zero crossing time, τ _nfor counter output signal C _outthe zero crossing time, subscript n means the numbering of time cycle.Then use A _nestimate the measured signal V after shaping _outnext time cycle Δ t _n+1, A _nbecome digital signal N after loop filter 300 and ADC400 _n+1, making the 600 generation time cycles of counter is 2N _n+1* T _refcounter output signal C _out, then with the V in next cycle _outcarry out phase differential relatively, wherein T _refthe cycle of the reference signal produced for crystal oscillator.From the signal waveform schematic diagram of Fig. 2, can find out, from the poor e of Measuring Time _nto utilizing A _nestimate next time cycle Δ t _n+1between, there is the delay of a clock period, therefore delay link 500 is set in feedforward network, the concrete steps of frequency measurement are as follows:

Step 1, by after measured signal filtering, amplifying, transfer the square-wave signal V of same frequency by shaping circuit 100 to _outbe the measured signal V after shaping _out;

Step 2, the measured signal V that phase detector 200 is measured after shaping _outoutput signal C with counter _outthe mistiming e of zero crossing _n, and output area and mistiming e _nthe pulsed current signal I be directly proportional _out;

Step 3, the output current I of 300 pairs of phase detectors 200 of loop filter _outcarry out integration and filtering, and transfer it to voltage signal;

Step 4, ADC400 transfers the analog voltage of loop filter 300 outputs to digital signal N;

Step 5, the digital signal N of 500 pairs of ADC400 outputs of delay link carries out the delay of a clock period, and the digital signal N after delay was directly proportional to the clock period of measured signal, determined the frequency of measured signal according to the digital signal N after this delay;

Step 6, the counter output signal C that the digital signal N after counter 600 produces the clock period and postpones is directly proportional _out, and by this counter output signal C _outmeasured signal V after input phase detector 200 and shaping _outdiffered comparison.

Waveform schematic diagram in conjunction with signal in sigma-delta shown in Fig. 2 (sigma-delta) PLL frequency measurement method, in conjunction with the principle of work of counter 600, can draw τ in the drawings _n+1-τ _n=N _n+1* T _ref, through the z conversion, easily know that the transport function C (z) of counter 600 is:

$C\left(z\right)=\frac{\mathrm{\τ}\left(z\right)}{N\left(z\right)}=\frac{T_{\mathrm{ref}}}{{1-z}^{-1}}$

In conjunction with the structural representation of the PLL of sigma-delta shown in Fig. 1 frequency measurement circuit, the output item N (z) of sigma-delta PLL frequency measurement circuit can be expressed as:

$N\left(z\right)=\left[\frac{K_d{A}_Q{z}^{-1}F\left(z\right)C\left(z\right)}{1+K_d{A}_Q{z}^{-1}F\left(z\right)C\left(z\right)}\right]\frac{t\left(z\right)(1-z^{-1})}{T_{\mathrm{ref}}}+\frac{q\left(z\right)}{1+K_d{A}_Q{z}^{-1}F\left(z\right)C\left(z\right)}$

Wherein, the transport function that F (z) is loop filter 300, A _qfor the linear gain of ADC400, q (z) is the quantizing noise that counter 600 is introduced.

At the measured signal V after shaping in Fig. 2 _outcycle be T=2 Δ t _n=2 (t _n-t _n-1), through the z conversion, can obtain:

T(z)＝2t(z)(1-z ^-1)

By in the expression formula of above formula T (z) substitution output item N (z), can obtain again:

$N\left(z\right)=\left[\frac{K_d{A}_Q{z}^{-1}F\left(z\right)C\left(z\right)}{1+K_d{A}_Q{z}^{-1}F\left(z\right)C\left(z\right)}\right]\frac{T\left(z\right)}{2T_{\mathrm{ref}}}+\frac{q\left(z\right)}{1+K_d{A}_Q{z}^{-1}F\left(z\right)C\left(z\right)}$

Consider integrator cascade Feedforward structure and C (the z)=T of loop filter transfer function F (z) _ref/ (1-z ^-1), can find out that above formula is the transport function of a typical sigma-delta modulator-demodular unit.Counter 600 changes digital signal N the time cycle of simulation into, has played the effect of DAC.

Therefore, frequency measurement method of the present invention has the characteristic of sigma-delta modulator-demodular unit, the quantizing noise q modulation high-frequency region that counter 600 can be introduced, move out of noise outside the bandwidth of measured signal, improves the frequency resolution in the measured signal bandwidth.According to the characteristic of sigma-delta modulator-demodular unit, in the situation that quantizing noise q size is constant, can also improve frequency resolution in the mode that improves sigma-delta frequency measurement loop exponent number simultaneously.

If the frequency measurement loop gain K of sigma-delta PLL _da _qz ^-1f (z) C (z)>>1, output item N (z) can be written as again:

$N\left(z\right)\≈\frac{T\left(z\right)}{2T_{\mathrm{ref}}}+\frac{q\left(z\right)}{K_d{A}_Q{z}^{-1}F\left(z\right)C\left(z\right)}$

Visible in sigma-delta PLL frequency measurement circuit, get final product the signal frequency 1/T of determination of acceleration meter oscillator by digital signal N, and increase loop gain K _da _qz ^-1f (z) C (z) also can effective inhibitory amount noise q impact.

As shown in Figure 3, loop filter 300 in sigma-delta PLL frequency measurement circuit of the present invention adopts integrator cascade Feedforward structure, the version of integrator cascade Feedforward comparatively is applicable to the loop filter 300 in sigma-delta PLL frequency measurement circuit, because this version can be avoided the existence of many feedback networks, the unique feedback network that adopts the sigma-delta PLL of this structure is counter 600.Counter 600 changes digital signal N the time cycle of simulation into, has played the effect of DAC.If adopt integrator cascade multiple feedback structure in sigma-delta PLL frequency measurement circuit, need a plurality of extra DAC that digital signal N is converted into to analog voltage, this will increase implements difficulty and cost.

In conjunction with Fig. 3, the pulsed current signal I of phase detector 200 outputs _outin first order feedforward path FF1, be multiplied by after gain A will with other feedforward path addition, and in other feedforward path, pulsed current signal I _outall will finally want the direct addition of electric current and voltage by after integral element 310, becoming voltage, this realizes more difficult in circuit.First order feedforward path FF1 is removed from loop filter 300 for this reason, and add lead compensation link 700 to guarantee the stability of loop.

Be illustrated in figure 4 the first order feedforward path of having removed in integrator cascade Feedforward structure, and add the sigma-delta PLL frequency measurement circuit structural representation after lead compensation link 700.Loop filter 300 after removal first order feedforward path FF1 can be divided into integral element 310 and filtering link 311 two parts, and wherein the gain of integral element 310 is K _i.Now the structure of sigma-delta PLL frequency measurement circuit is closely similar with typical phase-locked loop pll structure.In typical phaselocked loop, the output signal of phase detector is after integrator and filter process, then feeds back to voltage controlled oscillator.Exponent number as phaselocked loop is decided by wave filter, and the transport function G of filtering link 311 (z) has also determined the loop exponent number of sigma-delta PLL frequency measurement circuit.Between the described feedforward network intermediate ring road wave filter 300 and ADC400 that both can be placed in the frequency measurement loop for the lead compensation link 700 that maintains loop stability, adopt the mimic channel based on integrated operational amplifier to realize; Lead compensation link 700 also can be placed between feedback network delay link 500 sum counters 600 of frequency measurement loop, adopts digital circuit to realize.Implement more simply in digital circuit, can save extra mimic channel.

Fig. 5 is the structural representation of filtering link in the sigma-delta PLL frequency measurement loop of different rank in the present invention, the structural representation that wherein 5 (a) are filtering link in second order sigma-delta PLL frequency measurement loop, the structural representation that 5 (b) are filtering link in three rank sigma-delta PLL frequency measurement loops, the structural representation that 5 (c) are filtering link in quadravalence sigma-delta PLL frequency measurement loop.The higher ability of the inhibition to quantizing noise q of exponent number is stronger, and frequency resolution is higher, but circuit also can be more complicated.As can be seen from Figure 4 loop filter 300 is positioned at the prime of ADC400, should be realized by Analogous Integrated Electronic Circuits, and wherein the integrator of integral element 310 use based on integrated operational amplifier realized; And wave filter link 311 will first utilize state-space method to transfer the discrete transfer function of digital filter to equivalent continuous function, then realized by the analogue filter circuit based on integrated operational amplifier.

In sum, sigma-delta PLL frequency measurement circuit of the present invention and method, substitute VCO, the extra phase noise of having avoided VCO to bring, non-linear and temperature sensitivity with counter; Transport function is the version of sigma-delta modulator-demodular unit, and the quantizing noise that counter can be brought is modulated to high-frequency region, shifts out outside the bandwidth range of measured signal, greatly improves the frequency measurement resolution in bandwidth range; Under constant prerequisite, can further improve the resolution performance at quantizing noise by improving the loop exponent number, there is very strong noise resisting ability; Simple in structure, flexibility ratio is large, lower to the requirement of device: at first less demanding for the crystal oscillator frequency value as the counter clock benchmark; In addition because ADC carries out digital-to-analog conversion to the DC voltage after integral element and filtering link, thus to the figure place of ADC and sampling rate also all without excessive demand.

Claims (7)

1. a sigma-delta PLL frequency measurement circuit, it is characterized in that, comprise the shaping circuit (100), phase detector (200), loop filter (300), the ADC(400 that start to arrange in turn from input end) and delay link (500), and the output terminal of delay link (500) process counter (600) feed back input is to phase detector (200), wherein:

Shaping circuit (100), after measured signal filtering, amplifying, transfer the square-wave signal V of same frequency to _out;

Phase detector (200), measure the measured signal V after shaping _outwith counter output signal C _outthe zero crossing mistiming, and output area and mistiming e _nthe pulsed current signal I be directly proportional _out;

Loop filter (300), to the output current I of phase detector (200) _outcarry out integration and filtering, and transfer it to voltage signal;

ADC(400), transfer the analog voltage of loop filter (300) output to digital signal N;

Delay link (500), to ADC(400) output digital signal N carry out the delay of a clock period;

Counter (600), the counter output signal C that the digital signal N after producing the clock period and postponing is directly proportional _out, and by this counter output signal C _outinput phase detector (200).

2. sigma-delta PLL frequency measurement circuit according to claim 1, is characterized in that, described loop filter (300) adopts integrator cascade Feedforward structure.

3. sigma-delta PLL frequency measurement circuit according to claim 2, it is characterized in that, the integrator cascade Feedforward structure that described loop filter (300) adopts has been removed the front first order feedforward path of first integral element (301), and correspondingly in metering circuit, adds lead compensation link (700).

4. sigma-delta PLL frequency measurement circuit according to claim 3, it is characterized in that, described lead compensation link (700) be arranged at loop filter (300) and ADC(400) between or be arranged between delay link (500) sum counter (600).

5. sigma-delta PLL frequency measurement circuit according to claim 3, it is characterized in that, loop filter (300) after removal first order feedforward path is divided into integral element (310) and filtering link (311), and wherein integral element (310) adopts the integrator based on integrated operational amplifier; Filtering link (311) first transfers the discrete transfer function of digital filter to the continuous transport function of equivalence, then adopts the analogue filter circuit based on integrated operational amplifier.

6. a sigma-delta PLL frequency measurement method, is characterized in that, step is as follows:

Step 1, by after measured signal filtering, amplifying, transfer the square-wave signal V of same frequency by shaping circuit (100) to _out;

Step 2, phase detector (200) is measured the measured signal V after shaping _outoutput signal C with counter _outthe mistiming e of zero crossing _n, and output area and mistiming e _nthe pulsed current signal I be directly proportional _out;

Step 3, the output current I of loop filter (300) to phase detector (200) _outcarry out integration and filtering, and transfer it to voltage signal;

Step 4, ADC(400) transfer the analog voltage of loop filter (300) output to digital signal N;

Step 5, delay link (500) is to ADC(400) the digital signal N of output carries out the delay of a clock period, determines the frequency of measured signal according to the digital signal N after this delay;

Step 6, the counter output signal C that the digital signal N after counter (600) produces the clock period and postpones is directly proportional _out, and by this counter output signal C _outmeasured signal V after input phase detector (200) and shaping _outdiffered comparison.

7. sigma-delta PLL frequency measurement method according to claim 6, is characterized in that, the digital signal N after postponing described in step 5 was directly proportional to the clock period of measured signal.

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