CN103487602B - The anatomic method of integrated circuit (IC) chip - Google Patents
The anatomic method of integrated circuit (IC) chip Download PDFInfo
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The present invention relates to a kind of anatomic method of integrated circuit (IC) chip, comprise: an integrated circuit (IC) chip is provided, this integrated circuit (IC) chip comprises the encapsulated layer and a wire structures that are cascading, this wire structures comprises medium wiring layer between at least one low-k line, has medium wiring layer between a target low-k line between this at least one low-k line in medium wiring layer; Adopt chemical mechanical polishing method, be more than or equal to 3psi, and under being less than or equal to the downforce of 8psi, to be more than or equal to 60 ms/min, and integrated circuit (IC) chip described in the linear velocity polishing being less than or equal to 240 ms/min, remove be positioned at this integrated circuit (IC) chip perimeter encapsulated layer to exposing described wire structures; And continue to adopt chemical mechanical polishing method, be more than or equal to 0.1psi, and under being less than or equal to the downforce of 3psi, described in polishing, be positioned at the wire structures extremely medium wiring layer between exposed described target low-k line of described integrated circuit (IC) chip perimeter.
Description
Technical field
The present invention relates to a kind of anatomic method of integrated circuit (IC) chip.
Background technology
Along with the development of integrated circuit technique, the integrated level of circuit chip improves constantly, and is embodied in circuit components more and more intensive, and the size of the width and whole chip that connect wire is also in continuous reduction.The future development to miniaturization, complicated and three dimensional stress of whole device architecture.At present, the characteristic dimension of integrated circuit develops into 22nm.The reduction of live width, causes the coupling crosstalk between serious RC transmission delay and circuit, becomes the principal element of limiting circuit signaling rate.In this case, the metallic copper that resistivity is less instead of original metallic aluminium becomes new interconnected metal, and in traditional integrated circuit the dielectric material SiO that commonly uses
2also replaced by the new dielectric material that specific inductive capacity k value is less than 3.9.But the physical strength of low-k dielectric material is all lower, and reduce along with specific inductive capacity k is worth, physical strength also has the trend reduced further.Low-k dielectric material differs huge with the elastic modulus of interconnecting material copper, also lower with the bond strength on layers of copper and restraining barrier, thus causes in process and easily occur damage.
In order to solve the problem, research new material of increasing input on the one hand in the world, carries out low downforce or the research without pressure planarization on the one hand.Therefore, decapsulation is carried out to used cpu chip, obtain the mechanical characteristic of its low-k dielectric layer, become a kind of important means of research low-k dielectric layer processing characteristics.For this reason, someone proposes to adopt ion etching method to dissect integrated circuit (IC) chip to obtain low-k dielectric layer.But this ion etching method not only cost is higher, and the low-k dielectric layer sample obtained by the method is owing to mixing through high temperature and ion, and larger change occurs mechanical characteristic, is only suitable for, for observation wire structures, being not suitable for for carrying out mechanical property test.
Summary of the invention
In view of this, the anatomic method of the necessary integrated circuit (IC) chip provided in a kind of integrated circuit, the mechanical characteristic that medium wiring layer sample between this low-k line can be measured with AFM of medium wiring layer sample between the low-k line obtained by this anatomic method.
A kind of anatomic method of integrated circuit (IC) chip, comprise: an integrated circuit (IC) chip is provided, this integrated circuit (IC) chip comprises the encapsulated layer, a upper-layer wirings structure, middle layer cloth line structure and the lower floor's wire structures that are cascading, this lower-layer wiring structure comprises medium wiring layer between at least one low-k line, has medium wiring layer between a target low-k line between this at least one low-k line in medium wiring layer; Adopt chemical mechanical polishing method, under one first downforce, described encapsulated layer is removed to exposed described upper-layer wirings structure with a First Line speed, this first downforce is more than or equal to 3psi, and be less than or equal to 8psi, and this First Line speed is more than or equal to 60 ms/min, and be less than or equal to 240 ms/min; Adopt chemical mechanical polishing method, under one second downforce, described upper-layer wirings structure is removed to exposed described middle wire structures with one second linear velocity, this second downforce is more than or equal to 0.1psi, and be less than or equal to 3psi, and this second linear velocity is more than or equal to 60 ms/min, and be less than or equal to 240 ms/min; Adopt chemical mechanical polishing method, under one the 3rd downforce, described middle wire structures is removed to exposing described lower-layer wiring structure with one the 3rd linear velocity, 3rd downforce is more than or equal to 0.1psi, and be less than or equal to 3psi, and the 3rd linear velocity is more than or equal to 60 ms/min, and be less than or equal to 240 ms/min; And employing chemical mechanical polishing method, under one the 3rd downforce, medium wiring layer between the target low-k line in described lower-layer wiring structure to exposed described lower-layer wiring structure is removed with one the 3rd linear velocity, 3rd downforce is more than or equal to 0.1psi, and be less than or equal to 3psi, and the 3rd linear velocity is less than or equal to 90 ms/min.
A kind of anatomic method of integrated circuit (IC) chip, comprise: an integrated circuit (IC) chip is provided, this integrated circuit (IC) chip comprises the encapsulated layer and a wire structures that are cascading, this wire structures comprises medium wiring layer between at least one low-k line, has medium wiring layer between a target low-k line between this at least one low-k line in medium wiring layer; Adopt chemical mechanical polishing method, be more than or equal to 3psi, and under being less than or equal to the downforce of 8psi, to be more than or equal to 60 ms/min, and integrated circuit (IC) chip described in the linear velocity polishing being less than or equal to 240 ms/min, remove be positioned at this integrated circuit (IC) chip perimeter encapsulated layer to exposing described wire structures; And continue to adopt chemical mechanical polishing method, be more than or equal to 0.1psi, and under being less than or equal to the downforce of 3psi, described in polishing, be positioned at the wire structures extremely medium wiring layer between exposed described target low-k line of described integrated circuit (IC) chip perimeter.
Compared with prior art, the present invention adopts the method for chemically mechanical polishing to dissect described integrated circuit (IC) chip to obtain described low-k dielectric layer AFM sample, the method not only can retain the wire structures of medium wiring Rotating fields between described low-k line preferably, and the mechanical characteristic of described low-k dielectric layer can be kept, relatively be suitable as the sample of AFM, adopt AFM to measure the mechanical characteristic of this low-k dielectric layer.In addition, this method provided by the invention mainly adopts the method for chemical polishing to obtain low-k dielectric layer AFM sample with regard to passable, and cost compare is low, and the time used is shorter.
Accompanying drawing explanation
Fig. 1 is the anatomic method process flow diagram of integrated circuit (IC) chip provided by the invention.
Fig. 2 is the stereoscan photograph figure of the cpu chip that the embodiment of the present invention adopts.
Fig. 3 is the stereoscan photograph figure of medium wiring layer between the low-k line being suitable as AFM sample that obtains after adopting method process provided by the invention of cpu chip in Fig. 2.
Main element symbol description
| Cpu chip | 10 |
| Encapsulated layer | 12 |
| Upper-layer wirings structure | 14 |
| Middle wire structures | 16 |
| Lower-layer wiring structure | 18 |
Following embodiment will further illustrate the present invention in conjunction with above-mentioned accompanying drawing.
Embodiment
Below in conjunction with the accompanying drawings and the specific embodiments, the method that dissection integrated circuit provided by the invention measures medium wiring layer sample between low-k line wherein with acquisition AFM is described in further detail.
Refer to Fig. 1, the invention provides the anatomic method in a kind of integrated circuit, the method comprises the following steps:
S1, one integrated circuit (IC) chip is provided, this integrated circuit (IC) chip comprises the encapsulated layer and lower floor's wire structures that are cascading, this lower-layer wiring structure comprises medium wiring layer between at least one low-k line, has medium wiring layer between a target low-k line between this at least one low-k line in medium wiring layer; And
S2, adopts chemical mechanical polishing method to remove described encapsulated layer until medium wiring layer between target low-k line in described lower-layer wiring structure, obtains medium wiring layer between a low-k line being suitable as AFM sample.
In step S1, between described low-k line, medium wiring layer comprises low-k dielectric layer.Between low-k line, the specific inductive capacity of medium wiring layer is less than or equal to 3 herein.Described integrated circuit (IC) chip is bare chip, and it generally includes described encapsulated layer and a wire structures, and this wire structures comprises described lower-layer wiring structure.This integrated circuit (IC) chip comprises a silicon base further, and the lower-layer wiring structure in described wire structures is stacked is arranged at this silicon base.Described encapsulated layer is for the protection of the circuit in this integrated circuit (IC) chip.This lower-layer wiring structure comprises medium wiring layer between at least one low-k line, and between this at least one low-k line, medium wiring layer comprises at least two thin wires.Preferably, the spacing between these at least two thin wires is less than or equal to 95 nanometers.According to the difference of the purposes of this integrated circuit (IC) chip, the structure of this integrated circuit (IC) chip is also different.Particularly, the wire structures in this integrated circuit (IC) chip can be made up of described lower-layer wiring structure.Wire structures in this integrated circuit (IC) chip can further include a upper-layer wirings structure, and this upper-layer wirings structure is stacked to be arranged between described encapsulated layer and described at least one low-k line between medium wiring layer.This upper-layer wirings structure comprises at least one thick wiring layer, and this at least one thick wiring layer comprises many heavy gauge wires, and the live width of every bar heavy gauge wire is greater than the live width of described thin wires.Wire structures in this integrated circuit (IC) chip can further include a middle wire structures, and this middle wire structures is stacked to be arranged between described upper-layer wirings structure and described at least one low-k line between medium wiring layer.This middle wire structures comprises at least one middle live width wiring layer, and this at least one middle live width wiring layer comprises many central conductors, and the live width of every bar central conductor is less than the live width of described heavy gauge wire, and is greater than the live width of described thin wire.Be appreciated that medium wiring layer between the low-k line that described lower-layer wiring structure can comprise multilayer laminated setting, between described target low-k line, medium wiring layer is one or more layers between this multilayer low-k line in medium wiring layer.Described upper-layer wirings structure can comprise the thick wiring layer of multilayer laminated setting.Described middle wire structures can comprise the middle live width wiring layer of multilayer laminated setting.Therefore, this integrated circuit (IC) chip is generally Miltilayer wiring structure.Preferably, this integrated circuit (IC) chip is VLSI (very large scale integrated circuit) chip.This integrated circuit (IC) chip can be display card chip, cpu chip etc.
This step S1 can comprise step by step following: S11, provides a commercial integrated circuit (IC) chip, and this integrated circuit (IC) chip comprises at least one stitch, a circuit substrate and is placed in the described integrated circuit (IC) chip integrated circuit of this circuit substrate; And S12, at high temperature remove described at least one stitch and described circuit substrate with strong acid, obtain the integrated circuit (IC) chip with described encapsulated layer.Wherein, preferably, described integrated circuit is used commercial integrated circuit.
Step S2 mainly adopts chemical-mechanical polishing mathing to realize.Usually optical microscope is utilized to judge the polishing of described integrated circuit (IC) chip.Wherein, polishing refers to integrated circuit (IC) chip is specifically polished to which layer in encapsulated layer and wire structures.This step S2 is this integrated circuit (IC) chip of topography mainly, and particularly, the encapsulated layer, the wire structures that are positioned at this integrated circuit (IC) chip perimeter are removed in preferential dissection, polishing.Step S2 comprises the following steps:
S21, is fixed on a chemical-mechanical polishing mathing by described integrated circuit (IC) chip;
S22, adopts described chemical-mechanical polishing mathing under one first downforce, removes described encapsulated layer to exposing described lower-layer wiring structure with a First Line speed; And
S23, adopt described chemical-mechanical polishing mathing under one second downforce, with medium wiring layer between lower-layer wiring structure described in one second linear velocity polishing to exposed described target low-k line, wherein, this second downforce is less than the first downforce, and this second linear velocity is less than described First Line speed.
Described chemical-mechanical polishing mathing comprises multiple fixture for fixing described integrated circuit.In the step s 21, first described integrated circuit (IC) chip being fixed on one shares on thing, then be fixed on this chemical-mechanical polishing mathing by fixture, between fixture and integrated circuit (IC) chip, fix multiple thing of sharing to share the load suffered by integrated circuit (IC) chip simultaneously, reduce the downforce that integrated circuit (IC) chip is subject to, and then control polishing progress and effect than being easier to.Wherein, the material sharing thing described in is not limit, as long as this shares thing can play the load shared suffered by integrated circuit (IC) chip.This shares thing can be resin mass.
This step S21 can also be: first on the surface of the encapsulated layer of described integrated circuit (IC) chip, form multiple cut, and the plurality of cut at least penetrates this encapsulated layer, preferably, the plurality of cut penetrates this encapsulated layer to close described silicon base, but this silicon base is out not exposed; Then, then the integrated circuit (IC) chip this being formed with multiple cut be fixed on described chemical-mechanical polishing mathing.The encapsulated layer of this integrated circuit (IC) chip around the plurality of scratching edge place and various wire structures ratio are easier to be removed, thus than being easier to the inner structure exposing this integrated circuit.In addition, the inner structure of this integrated circuit also can be exposed by the edge of described integrated circuit (IC) chip.The inner structure can exposed according to this integrated circuit (IC) chip, successively chemically mechanical polishing remove described encapsulated layer until lower-layer wiring structure target low-k line between medium wiring layer.So, than be easier to each layer controlling this integrated circuit polishing time, determine polishing, make to adopt this chemical mechanical polishing method dissect this integrated circuit (IC) chip be more prone to, convenient.
Step S22 under the effect adopting described chemical-mechanical polishing mathing in described first downforce and described First Line speed, utilizes op-s polishing fluid to remove described encapsulated layer particularly.When described integrated circuit (IC) chip is made up of this encapsulated layer, described lower-layer wiring structure and silicon base, namely, described encapsulated layer is set directly at the surface of this lower-layer wiring structure, this step S22 is specifically as follows and adopts described chemical-mechanical polishing mathing under described first downforce, First Line speed and op-s polishing fluid is adopted to remove described encapsulated layer to exposing described lower-layer wiring structure soon, as this lower-layer wiring structure of maying be seen indistinctly.Wherein, described first downforce between 3psi ~ 8psi, as 4psi, 5psi, 6psi etc.Described First Line speed at 60 ms/min of (m/min) ~ 240m/min, e.g., 100m/min, 120m/min, 180m/min, 200m/min, 240m/min etc.The value of this First Line speed preferably can not be less than 60m/min, otherwise will increase polishing time; The value of this First Line speed can not be excessive, preferably be not more than 240m/min, otherwise can simultaneously because of the serious phenomenon crossing throwing of the thinner appearance of Thickness Ratio of this encapsulated layer, likely can destroy medium wiring layer between the target low-k line in described lower-layer wiring structure, also just can not obtain medium wiring layer AFM sample between low-k line.Wherein, this step S22 can adopt observation by light microscope whether to expose described lower-layer wiring structure.When described lower-layer wiring structure will be exposed time, can every a period of time adopt observation by light microscope once described lower-layer wiring structure whether expose, whether to continue polishing.That is, optical microscope can be adopted to judge whether to expose described lower-layer wiring structure.Alternatively, this step S22 adopts optical microscope to judge the concrete polishing removal position of this integrated circuit (IC) chip.
When described integrated circuit (IC) chip comprises described upper-layer wirings structure further, this step S22 can be:
S221, adopts described chemical-mechanical polishing mathing under described first downforce, removes described encapsulated layer to exposing described upper-layer wirings structure with described First Line speed.Wherein, this step S221 particularly can for first adopting encapsulated layer described in larger First Line velocity process to exposing described upper-layer wirings structure soon; And then adopt smaller First Line speed to continue this encapsulated layer of process to exposing this upper-layer wirings structure.
S222, adopt described chemical-mechanical polishing mathing under the effect of one the 3rd downforce and one the 3rd linear velocity, one first polishing fluid is utilized to remove described upper-layer wirings structure to exposing described lower-layer wiring structure, wherein, described 3rd downforce between 0.1psi ~ 3psi, as 0.6psi, 1.5psi, 2psi, 2.5psi etc.3rd downforce is less than described first downforce.3rd linear velocity is more than or equal to 60m/min, and is less than or equal to 240m/min, and the 3rd linear velocity is less than described First Line speed.Preferably, the 3rd linear velocity is more than or equal to 60m/min, and is less than or equal to 120m/min.This first polishing fluid can be copper polishing fluid.Optical microscope can be adopted to judge whether to expose described upper-layer wirings structure.
When described integrated circuit (IC) chip comprises the encapsulated layer, upper-layer wirings structure, middle wire structures and the lower-layer wiring structure that are cascading, described step S222 can be: under the effect of described 3rd downforce and described 3rd linear velocity, utilize described first polishing fluid to remove described upper-layer wirings structure to exposing described middle wire structures.This step S22 comprises step S223 further: adopt described chemical-mechanical polishing mathing under the effect of described 3rd downforce and one the 4th linear velocity, utilizes one second polishing fluid to remove described middle wire structures until will expose described lower-layer wiring structure.Wherein, the 4th linear velocity is more than or equal to 60m/min, and is less than or equal to 120m/min, and the 4th linear velocity is less than described 3rd linear velocity.This second polishing fluid is barrier polishing solution.
Between the target low-k line that step S23 obtains, medium wiring layer can be used in AFM sample, for measuring the mechanical property of medium wiring layer between ow-k line.This step S23 is for utilizing described second polishing fluid, under described second downforce and described second linear velocity, low-k dielectric structure described in polishing until expose there is smooth surface target low-k line between medium wiring layer, thus obtain described low-k dielectric layer AFM sample, wherein, this second downforce is less than the 3rd downforce, and this second downforce is greater than 0.1psi, and is less than or equal to 3psi.This second linear velocity is less than the 4th linear velocity, and this second linear velocity is less than or equal to 90m/min.Preferably, this second linear velocity is more than or equal to 20m/min, and is less than or equal to 60m/min.
This step S23 comprises further: between the target low-k line utilizing scanning electron microscope to determine to obtain, whether medium wiring layer is applicable to making AFM sample.If medium wiring layer is undesirable between described low-k line, be not suitable for making AFM sample, continue to repeat step S23, again utilize medium wiring layer between scanning electron microscopic observation target low-k line, until obtain satisfactory low-k layer.
The first polishing fluid in this step S22 and S23 and the second polishing fluid can according to the Material selec-tion of described upper-layer wirings structure, middle wire structures and lower-layer wiring structure.Above-mentioned in step S221 to S223 and step S23, after the polishing time of described step S221 to S223 and step S23 at least carries out half, adopt light microscopy once at set intervals, to determine whether to continue polishing, whether remove upper-layer wirings structure and middle wire structures and exposed medium wiring layer between target low-k line.
With specific embodiment, explanation the present invention will be further illustrated below.
Embodiment
The present embodiment provides a kind of method for making sample carrying out the Mechanics Performance Testing of low-k dielectric layer for dissecting commercial cpu chip, and the method specifically comprises the following steps:
1) provide a commercial chemical-mechanical polishing mathing and a cpu chip 10, this cpu chip 10 as shown in Figure 2.
2) cpu chip 10 is bonded on a resin mass, is then fixed on this chemical-mechanical polishing mathing, between this fixture and cpu chip, fix 3 to 6 resin mass to share the load suffered by cpu chip simultaneously; Adopt diamond pen on the surface of cpu chip each stroke of twice anyhow, form four road cuts.
3) the op-s polishing fluid that this chemical-mechanical polishing mathing carries is utilized, adopting linear velocity to be 180m/min and downforce is 3psi, described chemical-mechanical polishing mathing is to the surface encapsulation layer 12 of polishing cpu chip 10, polishing time about 15min, linear velocity is down to 90m/min, polishing time about 3 minutes, the encapsulated layer 12 of cpu chip 10 fringe region occurred throwing and exposed described upper-layer wirings structure 14, thus removed the surface encapsulation layer 12 of cpu chip 10.
4) utilize copper polishing fluid, adopting linear velocity to be 90m/min and downforce is 1psi, and described chemical-mechanical polishing mathing continues to carry out polishing to the above-mentioned cpu chip 10 exposing upper-layer wirings structure 14; Throwing, exposing described lower-layer wiring structure 18 appearred in scratching edge when polishing time is about 15min in described upper-layer wirings structure 14, thus removed described upper-layer wirings structure 14.
5) utilize barrier polishing solution, adopting linear velocity to be 60m/min and downforce is 1psi, and described chemical-mechanical polishing mathing continues to carry out polishing to the cpu chip 10 of the upper-layer wirings structure 14 removing cut place; Upon polishing during about 10min, the scratching edge of middle wire structures 16 mays be seen indistinctly described lower-layer wiring structure 18, thus removes described middle wire structures 16.
6) utilize barrier polishing solution, adopting linear velocity to be 40m/min and downforce is 0.5psi, and described chemical-mechanical polishing mathing continues to carry out polishing to the cpu chip 10 of the middle wire structures 16 removing cut place; About 10min upon polishing, medium wiring layer between the target low-k line that the scratching edge exposing surface of described lower-layer wiring structure 18 compares flat smooth.
7) sample step 6) obtained, observes under scanning electron microscope, searches suitable construction, determine whether to reach requirement, can be used as AFM sample at the edge of this cpu chip and cut place; As backlog demand, can not make AFM sample, continue to repeat step 6), polishing time is 30s, again observes, till can being used as AFM sample until meeting the demands.Between the target low-k line being suitable as AFM sample, medium wiring layer as shown in Figure 3.
In addition, in above-mentioned steps 4), 5), 6) in process, did one-time detection every two minutes of the second half section of described polishing time, determine whether to continue polishing.
Therefore, the embodiment of the present invention medium wiring layer between low-k line that described cpu chip 10 obtains as AFM sample that adopts the method for chemically mechanical polishing to dissect, the method not only can retain the wire structures of medium wiring layer between the low-k line between described low-k line in medium wiring Rotating fields preferably, and the mechanical characteristic of described low-k layer material can be kept, relatively be suitable as the sample of AFM, adopt AFM to measure the mechanical characteristic of this low-k dielectric layer.In addition, this method provided by the invention mainly adopts the method for chemically mechanical polishing just can obtain low-k dielectric layer AFM sample, as long as provide a chemical-mechanical polishing mathing, do not need special equipment and instrument, and the method does not need the encapsulated layer 12 in described cpu chip 10 until expose each layer of medium wiring layer between target low-k line and remove completely, as long as by the encapsulated layer 12 around the edge of cpu chip 10 or around cut place until expose each layer of medium wiring layer between target low-k line and remove, so, cost compare is low, and the time used is shorter.The inner structure of cpu chip 10 is exposed at the edge of described cpu chip 10 or cut place at first.The inner structure can exposed according to this cpu chip, successively chemically mechanical polishing remove the encapsulated layer that is positioned at around described edge or around cut place until expose lower-layer wiring structure target low-k line between medium wiring layer.So, than be easier to each layer controlling this integrated circuit polishing time, determine polishing, make to adopt this chemical mechanical polishing method dissect this integrated circuit (IC) chip be more prone to, convenient.
In addition, those skilled in the art can also do other change in spirit of the present invention, and these changes done according to the present invention's spirit all should be included in the present invention's scope required for protection.
Claims (10)
1. an anatomic method for integrated circuit (IC) chip, comprising:
(1) integrated circuit (IC) chip is provided, this integrated circuit (IC) chip comprises the encapsulated layer, a upper-layer wirings structure, middle layer cloth line structure and the lower floor's wire structures that are cascading, this lower-layer wiring structure comprises medium wiring layer between at least one low-k line, has medium wiring layer between a target low-k line between this at least one low-k line in medium wiring layer;
(2) cmp method is adopted, under one first downforce, described encapsulated layer is removed to exposed described upper-layer wirings structure with a First Line speed, this first downforce is more than or equal to 3psi, and be less than or equal to 8psi, and this First Line speed is more than or equal to 60 ms/min, and be less than or equal to 240 ms/min;
(3) cmp method is adopted, under one second downforce, described upper-layer wirings structure is removed to exposed described middle layer cloth line structure with one second linear velocity, this second downforce is more than or equal to 0.1psi, and be less than or equal to 3psi, and this second linear velocity is more than or equal to 60 ms/min, and be less than or equal to 240 ms/min;
(4) cmp method is adopted, under one the 3rd downforce, described middle layer cloth line structure is removed to exposing described lower-layer wiring structure with one the 3rd linear velocity, 3rd downforce is more than or equal to 0.1psi, and be less than or equal to 3psi, and the 3rd linear velocity is more than or equal to 60 ms/min, and be less than or equal to 240 ms/min; And
(5) cmp method is adopted, under one the 4th downforce, medium wiring layer between the target low-k line in described lower-layer wiring structure to exposed described lower-layer wiring structure is removed with one the 4th linear velocity, 4th downforce is more than or equal to 0.1psi, and be less than or equal to 3psi, and the 4th linear velocity is less than or equal to 90 ms/min.
2. the anatomic method of integrated circuit (IC) chip as claimed in claim 1, it is characterized in that, described step (2) comprises the following steps:
(21) multiple thing of sharing is placed between described integrated circuit (IC) chip and a chemical-mechanical polishing mathing, makes this integrated circuit (IC) chip be fixed in this chemical-mechanical polishing mathing, to share the load suffered by integrated circuit (IC) chip; And
(22) under described first downforce, described chemical-mechanical polishing mathing with described First Line speed, and utilizes op-s polishing fluid to remove described encapsulated layer to exposing described upper-layer wirings structure.
3. the anatomic method of integrated circuit (IC) chip as claimed in claim 1, it is characterized in that, comprise taking a step forward of described step (2): form multiple cut on the surface of described encapsulated layer, and the plurality of cut at least penetrates this encapsulated layer, so that the polishing of the inner structure determination integrated circuit (IC) chip of the integrated circuit (IC) chip exposed according to cut place.
4. the anatomic method of integrated circuit (IC) chip as claimed in claim 1, it is characterized in that, described step (5) comprises step further: between the target low-k line utilizing scanning electron microscope to determine to obtain, whether medium wiring layer is applicable to making atomic force microscope sample.
5. the anatomic method of integrated circuit (IC) chip as claimed in claim 4, it is characterized in that, when when between the target low-k line obtained, medium wiring layer is not suitable for making atomic force microscope sample, to continue between low-k line described in repeating said steps (5) polishing medium wiring layer and utilize medium wiring layer between scanning electron microscopic observation target low-k line, until medium wiring layer between the low-k line obtaining being applicable to doing atomic force microscope sample.
6. the anatomic method of integrated circuit (IC) chip as claimed in claim 1, it is characterized in that, described step (2) utilizes optical microscope to judge the polishing of described integrated circuit (IC) chip to step (4).
7. an anatomic method for integrated circuit (IC) chip, comprising:
(1) integrated circuit (IC) chip is provided, this integrated circuit (IC) chip comprises the encapsulated layer and a wire structures that are cascading, this wire structures comprises medium wiring layer between at least one low-k line, has medium wiring layer between a target low-k line between this at least one low-k line in medium wiring layer;
(2) chemical mechanical polishing method is adopted, be more than or equal to 3psi, and under being less than or equal to the downforce of 8psi, to be more than or equal to 60 ms/min, and integrated circuit (IC) chip described in the linear velocity polishing being less than or equal to 240 ms/min, remove be positioned at this integrated circuit (IC) chip perimeter encapsulated layer to exposing described wire structures; And
(3) continue to adopt chemical mechanical polishing method, be more than or equal to 0.1psi, and under being less than or equal to the downforce of 3psi, polishing is positioned at the wire structures extremely medium wiring layer between exposed described target low-k line of described integrated circuit (IC) chip perimeter.
8. the anatomic method of integrated circuit (IC) chip as claimed in claim 7, it is characterized in that, in step (1), described wire structures is made up of lower floor's wire structures, and this lower-layer wiring structure comprises medium wiring layer between multilayer low dielectric constant line, described step (3) is: adopt a chemical-mechanical polishing mathing being more than or equal to 0.1psi, and under being less than or equal to the downforce of 3psi, and the lower-layer wiring structure extremely medium wiring layer between exposed described target low-k line of described integrated circuit (IC) chip perimeter is positioned at the linear velocity polishing being less than or equal to 90 ms/min.
9. the anatomic method of integrated circuit (IC) chip as claimed in claim 7, it is characterized in that, in step (1), described wire structures comprises a upper-layer wirings structure and lower floor's wire structures, and this upper-layer wirings structure is stacked is arranged between described encapsulated layer and described lower-layer wiring structure; Described step (3) comprises the following steps:
(31) to be more than or equal to 60 ms/min, and the linear velocity removal being less than or equal to 240 ms/min is positioned at the upper-layer wirings structure of described integrated circuit (IC) chip perimeter to exposing described lower-layer wiring structure; And
(32) the lower-layer wiring structure extremely medium wiring layer between exposed described target low-k line of described integrated circuit (IC) chip perimeter is positioned at the linear velocity polishing being less than or equal to 90 ms/min.
10. the anatomic method of integrated circuit (IC) chip as claimed in claim 7, it is characterized in that, taking a step forward of described step (2) comprises step: form multiple cut on the surface of described encapsulated layer, and the plurality of cut at least penetrates this encapsulated layer, so that the polishing of the inner structure determination integrated circuit (IC) chip of the integrated circuit (IC) chip exposed according to cut place.
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