CN103474462B - Lateral double diffusion metal oxide semiconductor element and manufacture method thereof - Google Patents
Lateral double diffusion metal oxide semiconductor element and manufacture method thereof Download PDFInfo
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- CN103474462B CN103474462B CN201210186490.XA CN201210186490A CN103474462B CN 103474462 B CN103474462 B CN 103474462B CN 201210186490 A CN201210186490 A CN 201210186490A CN 103474462 B CN103474462 B CN 103474462B
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Abstract
Does the present invention propose a kind of lateral double diffusion metal oxide semiconductor (lateral? double? diffused? metal? oxide? semiconductor, LDMOS) element and manufacture method thereof. LDMOS element is formed in the first conductivity type substrate, comprise high pressure wellblock, the first field oxide region, at least one the second field oxide region, source electrode, drain electrode, this tagma, with gate pole; Wherein, look it by top view, the second field oxide region is between the first field oxide region and drain electrode, and the distribution of the second conductive-type impurity concentration in this high pressure wellblock, is relevant to the position of this second field oxide region.
Description
Technical field
The present invention relates to a kind of lateral double diffusion metal oxide semiconductor (lateraldoubleDiffusedmetaloxidesemiconductor, LDMOS) element and manufacture method thereof, particularlyRefer to a kind of LDMOS element and manufacture method thereof with higher crash guard voltage.
Background technology
Figure 1A-1C shows respectively the lateral double diffusion metal oxide semiconductor of prior art(lateraldoublediffusedmetaloxidesemiconductor, LDMOS) element 100Cutaway view, stereogram and top view. As shown in Figure 1A-1C, in P type substrate 11, have everyAbsolutely district 12, its around a closed area (in Fig. 1 C, shown in the thick black surround line in isolated district 12Meaning), to define the functional areas of LDMOS element 100, isolated district 12 and field oxide region 12a exampleAs be shallow trench isolation (shallowtrenchisolation, STI) structure or region oxygen as shown in the figureChange (localoxidationofsilicon, LOCOS) structure. LDMOS element 100 comprises N-typeWellblock 14, grid 13, drain electrode 15, source electrode 16, this tagma 17, body utmost point 17a and fieldZoneofoxidation 12a. Wherein, N-type wellblock 14, drain electrode 15 form light with source electrode 16 by micro-shadow technologyResistance and/or taking part or all of grid 13 for shielding, to define each region, and respectively with ionImplanted prosthetics, by N-type impurity, with the form of speeding-up ion, implants in the region of definition. ItsIn, drain electrode 15 lays respectively at grid 13 down either side with source electrode 16; This tagma 17 and bodyUtmost point 17a form photoresistance by micro-shadow technology and/or taking part or all of grid 13 as shielding, with fixedThe each region of justice, and respectively with ion embedding technology, by p type impurity, with the form of speeding-up ion,Implant in the region of definition. And in LDMOS element, some is positioned at an oxygen grid 13Change on district 12a. LDMOS element is high voltage device, that is it is designed for the higher behaviour of supplyMake voltage. The crash guard voltage of LDMOS element is higher, and conducting resistance is lower, and it applies modelEnclose wider. Generally speaking, crash guard voltage and conducting resistance cannot be taken into account, and wish reduces LDMOSElement conductive resistance, must change implanted ions parameter, so can sacrifice crash guard voltage;Or increase the implanted ions step of specific region, like this need extra micro-shadow and implanting stepSuddenly, manufacturing cost be will increase, desired conducting resistance and crash guard voltage just can be reached.
In view of this, the present invention, for above-mentioned the deficiencies in the prior art, proposes a kind of LDMOSElement and manufacture method thereof, do not increasing fabrication steps and do not sacrificing the conducting resistance of element operationSituation under, improve crash guard voltage, increase the range of application of element. In addition the present invention,LDMOS element implanted ions parameter can with low voltage component share, also can be integrated in lowPress the processing procedure of element, to manufacture high voltage device and low voltage component on same wafer simultaneously.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art and defect, proposes a kind of laterally two expansionDispersed metallic oxide semiconductor (lateraldoublediffusedmetaloxidesemiconductor,LDMOS) element and manufacture method thereof.
For reaching above-mentioned purpose, the invention provides a kind of LDMOS element, be formed at one firstIn conductivity type substrate, this substrate has a upper surface, and this LDMOS element comprises: one secondConductivity type high pressure wellblock, is formed in this substrate under this upper surface; One first field oxide region,Be formed on this upper surface, look it by top view, this first field oxide region is positioned at this high pressure wellblockIn; One grid, is formed on this upper surface, and this grid comprises a Part I, is positioned at thisOn the first field oxide region; One second conductivity type source electrode and the drain electrode of one second conductivity type, form respectivelyIn this upper surface below of these grid both sides; One first conductive type body region, is formed at table on thisUnder face, in this substrate, be positioned at this grid homonymy with this source electrode, and this source electrode is arranged in this this tagma;And at least one the second field oxide region, be formed on this upper surface, look it by top view, this is years oldTwo field oxide regions are between this first field oxide region and this drain electrode.
With regard to another viewpoint, the present invention also provides a kind of lateral double diffusion metal oxide semiconductor(lateraldoublediffusedmetaloxidesemiconductor, LDMOS) element manufacturerMethod, comprises: one first conductivity type substrate is provided, and this substrate has a upper surface; Form oneOne field oxide region and at least one the second field oxide region are on this upper surface; Form one second conductivity typeIn this substrate under this upper surface of high pressure wellblock, look it by top view, this second conductivity type is highThe scope in kill-job district comprises this first field oxide region and this at least one the second field oxide region; Form oneGrid is on this upper surface, and this grid comprises a Part I, is positioned at this first field oxide regionOn; And form that one second conductivity type source electrode and one second conductivity type drain in these grid both sidesThis upper surface below, and form one first conductive type body region under this upper surface in this substrate,Be positioned at this grid homonymy with this source electrode, and this source electrode is arranged in this this tagma, wherein this drain bitIn the outside away from this second field oxide region of this grid; Wherein, this high pressure wellblock is formed atAfter this first field oxide region and this second field oxide region form, to make in this high pressure wellblockThe distribution of the second conductive-type impurity concentration, is relevant to the position of this second field oxide region.
Therein in a kind of preferred embodiment, this first field oxide region and this at least one secondBetween zoneofoxidation, define at least one open region, lead in second of this upper surface below this open regionElectricity type impurity concentration, leads higher than second of this first field oxide region and this second field oxide region belowElectricity type impurity concentration.
In above-mentioned preferred embodiment, this grid can more comprise a Part II, is positioned at this openingOn this upper surface of district top, and this Part II has a dielectric layer, is connected with this upper surface.
In previous embodiment, this grid can more comprise a Part III, is positioned at this second oxidationTop, district.
In a kind of preferred embodiment, this LDMOS element should comprise multiple the second field oxide regions,And between this first field oxide region and adjacent the second field oxide region and adjacent secondBetween zoneofoxidation, define multiple open regions, this open region is in the second conduction of this upper surface belowType impurity concentration, higher than the second conduction of this first field oxide region and this second field oxide region belowType impurity concentration.
In above-mentioned preferred embodiment, look it by top view, this of relatively close this drain electrode openedMouth region area is greater than relatively this open region area near this first field oxide region.
In another embodiment, between this this tagma and this substrate, can be separated out by this high-pressure well again,So that this this tagma is not directly connected with this electrical property of substrate; Or at least partly this this tagma can with thisSubstrate connects, or can connect this substrate via one first conductivity type connection wellblock, so that this bodyDistrict is connected with this electrical property of substrate.
Illustrate in detail below by specific embodiment, when being easier to understand object of the present invention, skillArt content, feature and effect of reaching thereof.
Brief description of the drawings
Figure 1A-1C shows respectively cutaway view, the solid of the LDMOS element 100 of prior artFigure and top view;
Fig. 2 A-2D shows first embodiment of the present invention;
Fig. 3 shows second embodiment of the present invention;
Fig. 4 shows the 3rd embodiment of the present invention;
Fig. 5 shows the 4th embodiment of the present invention;
Fig. 6 shows the 5th embodiment of the present invention;
Fig. 7 shows the 6th embodiment of the present invention;
Fig. 8 shows the 7th embodiment of the present invention;
Fig. 9 shows the 8th embodiment of the present invention;
Figure 10 shows the 9th embodiment of the present invention;
Figure 11 shows the of the present invention ten embodiment;
Figure 12 A-12C shows a kind of characteristic curve of prior art LDMOS element;
Figure 13 A-13C shows a kind of characteristic curve that utilizes LDMOS element of the present invention.
Symbol description in figure
11,21,31,41,51,61,91 substrates
12,22,32,42,52,62,72,82,92,102,112 isolated districts
12a,22a,22b,32a,32b,42a,42b,42c,52a,52b,52c,62a,62b,62c,62d, 72a, 72b, 82a, 82b, 82c, 82d, 92a, 92b, 102a, 102b, 112a, 112b field oxygenChange district
13,23,33,43,53,63,73,83,93,103,113 grids
14,24,34,44,54,64,74,84,94,104,114 high pressure wellblocks
15,25,35,45,55,65,75,85,95,105,115 drain electrodes
16,26,36,46,56,66,76,86,96,106,116 source electrodes
17,27,37,47,57,67,77,87,97,107,117 these tagmas
17a, 27a, 37a, 47a, 57a, 67a, 77a, 87a, 97a, 107a, the 117a body utmost point
21a, 31a, 41a, 51a, 61a, 91a, 101a upper surface
108 connect wellblock
100,200,300,400,600,700,800,900,1000,1100LDMOS element
221,321,421,422 open regions
Detailed description of the invention
Graphic in the present invention all belongs to signal, is mainly intended to represent between fabrication steps and each layerOrbution up and down, as for shape, thickness and width not according to scale.
Refer to Fig. 2 A-2D, show first embodiment of the present invention, the present embodiment shows shouldWith the manufacture method schematic diagram of LDMOS element 200 of the present invention. Wherein, Fig. 2 A-2B isSchematic perspective view, Fig. 2 C is cross-sectional schematic, Fig. 2 D is schematic top plan view. First, as figureShown in 2A, provide substrate 21, it has upper surface 21a, and the conductivity type of substrate 21 is for exampleP type but be not limited to P type (implementing in kenel at other can also be N-type); And, substrate21 can be for example p-nJie Erjiguan non-epitaxial p-n junction diode silicon substrate, can also be epitaxial substrate. Next, please continue ginsengRead Fig. 2 A, can utilize identical but be not limited to identical fabrication steps, form isolated district 22 and fieldZoneofoxidation 22a and 22b are upper in upper surface 21a, by top view depending on it (consulting Fig. 2 D), an oxygenChange district 22a and 22b and be arranged in the high pressure wellblock 24 that successive process steps forms; Wherein, everyDistrict 22 is for example sti structure or the oxidation of region as shown in the figure with field oxide region 22a and 22b absolutelyLOCOS structure. Then, with ion embedding technology, will be such as but not limited to N-type impurity, withThe form of speeding-up ion, implants in the region of definition, forms N-type high pressure under upper surface 21aWellblock 24 is in substrate 21. Should be noted, because field oxide region 22a and 22b are to above-mentionedSpeeding-up ion has shield effectiveness; Therefore, high pressure wellblock 24 is formed at field oxide region 22a and 22bAfter formation, and the distribution of N-type impurity concentration in high pressure wellblock 24, be relevant to field oxide regionThe position of 22b; With the present embodiment speech, between field oxide region 22a and 22b, defined openingThe upper surface 21a below of mouth region 221 (referring to Fig. 2 C and Fig. 2 D), N-type impurity concentration is highIn the N-type impurity concentration of field oxide region 22a and 22b below. Then refer to Fig. 2 B, 2CWith 2D, form grid 23, drain electrode 25, source electrode 26, this tagma 27, with body utmost point 27a.Wherein, as shown in the figure, it is upper that grid 23 is formed at upper surface 21a, and part of grid pole 23 is positioned at fieldOn zoneofoxidation 22a. Drain electrode 25 is for example N-type with source electrode 26 but is not limited to N-type, differenceBe positioned at grid 23 both sides upper surface 21a belows, and look it by top view Fig. 2 D, drain electrode 25 withSource electrode 26 is separated with field oxide region 22a and 22b by grid 23; Wherein, this tagma 27 formsUnder upper surface 21a, in high pressure wellblock 24, be all positioned at grid 23 homonymies with source electrode 26, and sourceThe utmost point 26 is arranged in this tagma 27, wherein drains 25 to be positioned at the field oxide region away from grid 23The outside of 22b; Drain electrode 25 is formed in the high pressure wellblock 24 of grid 23 opposite sides. Wherein,N-type source electrode 26 is formed at upper surface 21a below with N-type drain electrode 25, by micro-shadow technology and/orTaking part or all of grid 23, field oxide region 22a and 22b as shielding, to define each region,And respectively with ion embedding technology, by N-type impurity, with the form of speeding-up ion, implant definitionRegion in institute form. This tagma 27 of P type and P type body utmost point 27a are formed at upper surface 21aBelow, by micro-shadow technology and/or taking part or all of grid 23, isolated district 22 as shielding,Define this region, and with ion embedding technology, by p type impurity, with the form of speeding-up ion,Implanting institute in the region defining forms. Wherein, source electrode 26 can be by identical or not with drain electrode 25Same micro-photographing process step and implanted ions step complete, and source electrode 26, drain electrode 25 and this tagma27 and body utmost point 27a form fabrication steps order can convert.
In the LDMOS element 100 of aforementioned prior art, between this tagma 17 and drain electrode 15Drift region (driftregion) covered completely with field oxide region 12a by grid 13. With prior artDifferent, in the present embodiment, the drift region in LDMOS element 200, by grid23 cover completely with field oxide region 22a and 22b, and opening between field oxide region 22a and 22bMouth region 221, comes out the upper surface 21a of the high pressure wellblock 24 of part, makes to form highThe ion implantation manufacture process step in kill-job district 24, at 221 places, open region, implants more impurityIn substrate, make the upper surface 21a below of open region 221, N-type impurity concentration is higher. This kindThe advantage of arrangement comprises: in component specification, and compared to prior art, application the present inventionCan improve the crash guard voltage of LDMOS element, especially to relaxing Cork effect (KirkEffect), more obvious, conducting crash guard voltage can significantly be improved; On processing procedure,Field oxide region 22b can utilize the fabrication steps shape identical with field oxide region 22a and isolated district 22Become, and do not need to increase newly in addition fabrication steps, therefore can reduce manufacturing cost.
Fig. 3 shows second embodiment of the present invention, is application LDMOS element 300 of the present inventionCross-sectional schematic. As shown in the figure, the LDMOS element 300 of the present embodiment, its functional areas byIsolated district 32 defines; LDMOS element 300 comprises field oxide region 32a and 32b, grid33, high pressure wellblock 34, drain electrode 35, source electrode 36, this tagma 37, with body utmost point 37a. WithAn embodiment difference is, in the present embodiment, grid 33 has comprised and lays respectively at an oxygenChange the Part I 33a of district 32a top, be positioned on the upper surface 31a of 321 tops, open regionPart II 33b, with the Part III 33c that is positioned at field oxide region 32b top. Should be noted,Part II 33b should have dielectric layer (that is grid 33 comprises gate electrode and gate dielectric),This dielectric layer is connected with upper surface 31a, to avoid grid 33 to be directly electrically connected with high pressure wellblock 34.In addition, Part III 33c can not exist, and this also within the scope of the present invention.
Fig. 4 shows the 3rd embodiment of the present invention, is application LDMOS element 400 of the present inventionCross-sectional schematic. As shown in the figure, the LDMOS element 400 of the present embodiment, its functional areas byIsolated district 42 defines; LDMOS element 400 comprise field oxide region 42a, 42b and 42c,Grid 43, high pressure wellblock 44, drain electrode 45, source electrode 46, this tagma 47, with body utmost point 47a.Be with first embodiment difference, in the present embodiment, be positioned at field oxide region 42a and drain electrodeThe field oxide region 42b of 45 and 42c are multiple, and at field oxide region 42a and adjacent field oxygenChange between district 42b and between adjacent field oxide region 42b and 42c, define multiple open regions,Open region 421 and 422 as shown in the figure, and open region 421 and 422 is in upper surface 41a belowN-type impurity concentration, higher than the N of field oxide region 42a and field oxide region 42b and 42c belowType impurity concentration.
Fig. 5 shows the 4th embodiment of the present invention, is application LDMOS element 500 of the present inventionCross-sectional schematic. As shown in the figure, the LDMOS element 500 of the present embodiment, its functional areas byIsolated district 52 defines; LDMOS element 500 comprise field oxide region 52a, 52b and 52c,Grid 53, high pressure wellblock 54, drain electrode 55, source electrode 56, this tagma 57, with body utmost point 57a.Be with the 3rd embodiment difference, in the present embodiment, similar with second embodiment,Grid 53 has covered field oxide region 52a, 52b and 52c and multiple open regions therebetween, certainly,Still must note being positioned at part of grid pole 53 on open region should have dielectric layer (that is grid 53 wrapsContaining gate electrode and gate dielectric), this dielectric layer is connected with upper surface 51a, makes grid 53Directly be not electrically connected with high pressure wellblock 54.
Fig. 6 shows the 5th embodiment of the present invention, is application LDMOS element 600 of the present inventionCross-sectional schematic. As shown in the figure, the LDMOS element 600 of the present embodiment, its functional areas byIsolated district 62 defines; LDMOS element 600 comprise field oxide region 62a, 62b, 62c and62d, grid 63, high pressure wellblock 64, drain electrode 65, source electrode 66, this tagma 67, with the body utmost point67a. The present embodiment is intended to illustrate in LDMOS element 600 of the present invention, multiple field oxide regionsDefined open region between 62a, 62b, 62c and 62d, can utilize field oxide region 62a, 62b,The size of 62c and 62d, controls N-type impurity and implants the quantity of high pressure wellblock 64, so that applicationUsefulness the best of the present invention, for example, can be larger by relatively approaching the design of drain electrode 65 open region,Relatively less near the open region design of field oxide region 62a, with optimization LDMOS element600 conducting crash guard voltage.
Fig. 7 shows the 6th embodiment of the present invention, is application LDMOS high pressure of the present invention unitThe schematic top plan view of part 700. As shown in the figure, the LDMOS element 700 of the present embodiment, its meritCan be defined by completely cutting off district 72 in district; LDMOS element 700 comprise field oxide region 72a and 72b,Grid 73, high pressure wellblock 74, drain electrode 75, source electrode 76, this tagma 77 and body utmost point 77a.The present embodiment is intended in application LDMOS element 700 of the present invention, can be in field oxide regionIn 72b, according to demand, form the open region of varying number in diverse location, to increase LDMOSThe crash guard voltage of element, the arrangement of this kind of field oxide region 72b, also in scope of the present inventionWithin.
Fig. 8 shows the 7th embodiment of the present invention, is application LDMOS element 800 of the present inventionSchematic top plan view. As shown in the figure, the LDMOS of the present embodiment presses element 800, its functional areasDefined by isolated district 82; LDMOS element 800 comprises field oxide region 82a, 82b, 82cWith 82d, grid 83, high pressure wellblock 84, drain electrode 85, source electrode 86, this tagma 87, with thisBody utmost point 87a. The present embodiment is intended in application LDMOS element 800 of the present invention, can profitWith the position of multiple field oxide region 82a, 82b, 82c and 82d, look it by top view, according to electricitySexual needs, the width of adjustment open region.
Fig. 9 shows the 8th embodiment of the present invention, is application LDMOS element 900 of the present inventionCross-sectional schematic. As shown in the figure, the LDMOS element 900 of the present embodiment, its functional areas byIsolated district 92 defines; LDMOS element 900 comprises field oxide region 92a and 92b, grid93, high pressure wellblock 94, drain electrode 95, source electrode 96, this tagma 97, with body utmost point 97a. WithAn embodiment difference, in first embodiment, between this tagma 27 and substrate 21, by heightKill-job district 24 separates, so that this tagma 27 is not electrically connected with substrate 21, makes LDMOS unitPart 200 can be used as upper bridge (highside) element in power supply circuit. Differently, as figureShown in, in the present embodiment LDMOS element 900, this tagma 97 of part connects with substrate 91Connect, so that this tagma 97 is electrically connected with substrate 91, this makes LDMOS element 900 passableAs lower bridge (lowside) element in power supply circuit.
Figure 10 shows the 9th embodiment of the present invention, is application LDMOS element of the present invention1000 cross-sectional schematic. As shown in the figure, the LDMOS element 1000 of the present embodiment, its meritCan be defined by completely cutting off district 102 in district; LDMOS element 1000 comprise field oxide region 102a with102b, grid 103, high pressure wellblock 104, drain electrode 105, source electrode 106, this tagma 107, withBody utmost point 107a. Be with the 8th embodiment difference, in the present embodiment, part bodyBetween district 107 and substrate 101, connect wellblock 108 via P type and connect, so that this tagma 107Be electrically connected with substrate 101, this makes LDMOS element 1000 can be used as power supply circuitIn lower bridge (lowside) element.
Figure 11 shows the of the present invention ten embodiment, is application LDMOS high pressure of the present invention unitThe schematic top plan view of part 1100. As shown in the figure, the LDMOS element 1100 of the present embodiment, itsFunctional areas are defined by completely cutting off district 112; LDMOS element 1100 comprise field oxide region 112a with112b, grid 113, high pressure wellblock 114, drain electrode 115, source electrode 116, this tagma 117, withAnd body utmost point 117a. The present embodiment is intended in application LDMOS element 1100 of the present invention,Can be in field oxide region 112b, according to demand, the shape of open region, by top view, Figure 11 looksIt, be not limited to the rectangle in aforementioned each embodiment, also can be arbitrary shape, this kind of field oxidationThe arrangement of district 112b, also within the scope of the present invention.
Figure 12 A-12C shows a kind of characteristic curve of prior art LDMOS element. Refer toFigure 12 A, shows that this prior art LDMOS element operation is in the time of conduction status not, drain currentTo the characteristic curve of drain voltage, according to this characteristic curve, can learn this prior artThe not conducting crash guard voltage of LDMOS element is about 76V. Then refer to Figure 12 B, aobviousShow that this prior art LDMOS element drain current (the left side longitudinal axis) and electricity lead (the right side longitudinal axis) to gridThe characteristic curve of pole tension, according to this characteristic curve, can learn this prior art LDMOSThe critical voltage of element is about 1V. Next refer to Figure 12 C, show this prior artLDMOS element operation in the time of conduction status, the characteristic curve of drain current to drain voltage, rootCharacteristic curve accordingly, can learn the conducting crash guard electricity of this prior art LDMOS elementPressure is about 54V.
On the other hand, Figure 13 A-13C shows a kind of characteristic of utilizing LDMOS element of the present inventionCurve, prior art LDMOS unit shown in the operating voltage that it is basic and earlier figures 12A-12CPart is identical. Refer to Figure 13 A, show that this utilizes LDMOS element operation of the present invention in not conductingWhen situation, the characteristic curve of drain current to drain voltage, according to this characteristic curve, can obtainKnow that this utilizes the not conducting crash guard voltage of LDMOS element of the present invention to be about 100V. ThenRefer to Figure 13 B, show this utilize LDMOS element drain current of the present invention (the left side longitudinal axis) withElectricity is led (the right side longitudinal axis) characteristic curve to grid voltage, according to this characteristic curve, can learn thisUtilize the critical voltage of LDMOS element of the present invention to be also about 1V, and its conducting resistance and aforementionedThe element of prior art LDMOS shown in Figure 12 A-12C is suitable. Next refer to Figure 13 C,Show that this utilizes LDMOS element operation of the present invention in the time of conduction status, drain current is to drain electrodeThe characteristic curve of voltage, according to this characteristic curve, can learn that this utilizes LDMOS of the present inventionThe conducting crash guard voltage of element is about 75V.
The element characteristic curve of prior art LDMOS shown in comparison diagram 12A-12C and figureShown in 13A-13C, utilize LDMOS element characteristic curve of the present invention, can learn, apply thisThe bright crash guard voltage that can significantly improve LDMOS element, and do not sacrifice conducting resistance.
Below for preferred embodiment, the present invention being described, is the above, only for making thisThose skilled in the art are easy to understand content of the present invention, are not used for limiting right model of the present inventionEnclose. Under same spirit of the present invention, those skilled in the art can think and various equivalence changes.For example, not affecting under the main characteristic of element, can add other fabrication steps or structure, asCritical voltage is adjusted district etc.; And for example, micro-shadow technology is not limited to light shield technology, also can comprise electricitySub-Shu Weiying technology; For another example, look it by top view, apply LDMOS element of the present invention notBeing limited to for rectangle, can also be circular or snakelike etc. Scope of the present invention should contain above-mentioned andIts all equivalence changes.
Claims (12)
1. a lateral double diffusion metal oxide semiconductor element, is formed at one first conductivity typeIn substrate, this substrate has a upper surface, comprises:
One second conductivity type high pressure wellblock, is formed in this substrate under this upper surface;
One first field oxide region, is formed on this upper surface, looks it by top view, this firstZoneofoxidation is arranged in this high pressure wellblock;
One grid, is formed on this upper surface, and this grid comprises a Part I, is positioned at thisOn the first field oxide region;
One second conductivity type source electrode and the drain electrode of one second conductivity type, be formed at respectively this grid both sidesThis upper surface below;
One first conductive type body region, is formed under this upper surface in this substrate, with this source bitIn this grid homonymy, and this source electrode is arranged in this this tagma; And
At least one the second field oxide region, is formed on this upper surface, looks it by top view, and this is years oldTwo field oxide regions between this first field oxide region and this drain electrode,
It is characterized in that, between this first field oxide region and this at least one the second field oxide region, fixedAt least one open region of justice, the second conductive-type impurity concentration of this open region below this upper surface,Higher than the second conductive-type impurity concentration of this first field oxide region and this second field oxide region below.
2. lateral double diffusion metal oxide semiconductor element as claimed in claim 1, wherein,This grid more comprises a Part II, be positioned on this upper surface of top, this open region, and thisTwo parts have a dielectric layer, are connected with this upper surface.
3. lateral double diffusion metal oxide semiconductor element as claimed in claim 2, wherein,This grid more comprises a Part III, is positioned at this second field oxide region top.
4. a lateral double diffusion metal oxide semiconductor element, is formed at one first conductivity typeIn substrate, this substrate has a upper surface, comprises:
One second conductivity type high pressure wellblock, is formed in this substrate under this upper surface;
One first field oxide region, is formed on this upper surface, looks it by top view, this firstZoneofoxidation is arranged in this high pressure wellblock;
One grid, is formed on this upper surface, and this grid comprises a Part I, is positioned at thisOn the first field oxide region;
One second conductivity type source electrode and the drain electrode of one second conductivity type, be formed at respectively this grid both sidesThis upper surface below;
One first conductive type body region, is formed under this upper surface in this substrate, with this source bitIn this grid homonymy, and this source electrode is arranged in this this tagma; And
At least one the second field oxide region, is formed on this upper surface, looks it by top view, and this is years oldTwo field oxide regions are between this first field oxide region and this drain electrode
It is characterized in that, lateral double diffusion metal oxide semiconductor element comprises multiple secondZoneofoxidation, and between this first field oxide region and adjacent the second field oxide region and adjacentThe second field oxide region between, define multiple open regions, this open region is in this upper surface belowThe second conductive-type impurity concentration, higher than this first field oxide region and this second field oxide region belowThe second conductive-type impurity concentration.
5. lateral double diffusion metal oxide semiconductor element as claimed in claim 4, wherein,Look it by top view, be relatively greater than relatively near being somebody's turn to do near this open region area of this drain electrodeThis open region area of the first field oxide region.
6. a lateral double diffusion metal oxide semiconductor manufacturing method, is characterized in that,Comprise:
One first conductivity type substrate is provided, and this substrate has a upper surface;
Form one first field oxide region and at least one the second field oxide region on this upper surface;
Form in one second conductivity type high pressure wellblock this substrate under this upper surface, by top viewDepending on it, the scope of this second conductivity type high pressure wellblock comprises this first field oxide region and this is at least oneThe second field oxide region;
Form a grid on this upper surface, and this grid comprises a Part I, be positioned at thisOn one field oxide region; And
Forming one second conductivity type source electrode and one second conductivity type drains on this of this grid both sidesLower face, and form one first conductive type body region under this upper surface in this substrate, with thisSource electrode is positioned at this grid homonymy, and this source electrode is arranged in this this tagma, and wherein this drain electrode is positioned atAway from the outside of this second field oxide region of this grid;
Wherein, this high pressure wellblock is formed at this first field oxide region and the formation of this second field oxide regionAfterwards, to make the distribution of the second conductive-type impurity concentration in this high pressure wellblock, be relevant to thisThe position of the second field oxide region.
7. lateral double diffusion metal oxide semiconductor element manufacturer as claimed in claim 6Method, wherein, between this first field oxide region and this at least one the second field oxide region, definition at leastOne open region, this open region is in the second conductive-type impurity concentration of this upper surface below, higher than thisThe second conductive-type impurity concentration of the first field oxide region and this second field oxide region below.
8. lateral double diffusion metal oxide semiconductor element manufacturer as claimed in claim 7Method, wherein, this grid more comprises a Part II, is positioned at this upper surface of this top, open regionUpper, and this Part II has a dielectric layer, is connected with this upper surface.
9. lateral double diffusion metal oxide semiconductor element manufacturer as claimed in claim 8Method, wherein, this grid more comprises a Part III, is positioned at this second field oxide region top.
10. lateral double diffusion metal oxide semiconductor element as claimed in claim 6 is manufacturedMethod, wherein, lateral double diffusion metal oxide semiconductor element comprises multiple second oxidationDistrict, and between this first field oxide region and adjacent the second field oxide region and adjacentBetween two field oxide regions, define multiple open regions, this open region is in second of this upper surface belowConductive-type impurity concentration, higher than second of this first field oxide region and this second field oxide region belowConductive-type impurity concentration.
11. lateral double diffusion metal oxide semiconductor elements as claimed in claim 10 are manufacturedMethod, wherein, looks it by top view, is relatively greater than near this open region area of this drain electrodeThis open region area of relatively close this first field oxide region.
12. lateral double diffusion metal oxide semiconductor elements as claimed in claim 6 are manufacturedMethod, wherein, is separated out by this high-pressure well between this this tagma and this substrate, so that this this tagmaDirectly be not connected with this electrical property of substrate; Or this this tagma is connected with this substrate at least partly, or warpConnect wellblock by one first conductivity type and connect this substrate, so that this this tagma and this electrical property of substrate connectConnect.
Priority Applications (1)
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| US6528850B1 (en) * | 2000-05-03 | 2003-03-04 | Linear Technology Corporation | High voltage MOS transistor with up-retro well |
| US7122876B2 (en) * | 2004-08-11 | 2006-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation-region configuration for integrated-circuit transistor |
| US9142671B2 (en) * | 2009-10-30 | 2015-09-22 | Vanguard International Semiconductor Corporation | Lateral double-diffused metal oxide semiconductor |
| CN102148247B (en) * | 2010-02-04 | 2013-07-31 | 立锜科技股份有限公司 | LDMOS (lateral diffused metal-oxide-semiconductor device) capable of increasing punch-through protective voltage and manufacturing method thereof |
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