CN103456710A - Mos device and manufacturing method thereof - Google Patents
Mos device and manufacturing method thereof Download PDFInfo
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- CN103456710A CN103456710A CN2012101811300A CN201210181130A CN103456710A CN 103456710 A CN103456710 A CN 103456710A CN 2012101811300 A CN2012101811300 A CN 2012101811300A CN 201210181130 A CN201210181130 A CN 201210181130A CN 103456710 A CN103456710 A CN 103456710A
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Abstract
The invention discloses an MOS device and a manufacturing method thereof. The MOS device comprises a substrate, a grid electrode structure, a drain electrode area and a source electrode area. The grid electrode structure is arranged on the substrate, and the drain electrode area and the source electrode area are arranged in substrate located on the two sides of the grid electrode structure respectively. The substrate is provided with a first well region and a second well region, and the first well region and the second well region are connected at the substrate which is located at the bottom of the grid electrode structure. The drain electrode area is located in the first well region, and the source electrode area is located in the second well region. An anti-fuse element is arranged on the drain electrode area. The MOS device can be adaptive to high work voltages, and further can be adaptive to electronic products working under high power.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly a kind of MOS(Metal Oxide Semiconductor, metal-oxide semiconductor (MOS)) device and manufacture method thereof.
Background technology
As the most basic electronic component, the MOS device is widely used in semi-conductor industry.No matter what kind of occurs and changes in the shape of MOS device, and its basic structure includes 3 electrodes, i.e. grid, source electrode, drain electrode makes source electrode, drain electrode conducting by apply voltage at grid.In general, the MOS device comprises substrate and the grid structure (as polysilicon gate construction or metal gates) formed thereon, successively by light dope and heavy doping, form source area and drain region in the substrate of the both sides of grid structure, when access MOS device is opened on grid control voltage and when drain region and source area access respectively input power and out-put supply, just form conducting channel in the substrate of the gate bottom between drain region and source area, the work of MOS break-over of device.
Progress along with semiconductor technology, the size of MOS device is constantly being dwindled, a lot of problems have thereupon been derived, one of them is hot carrier's effect (hot carrier effect), be exactly when the operating voltage of MOS device surpasses some strength, because powerful electric field acceleration electronic impact electron hole pair has produced a large amount of charge carriers, the electric current that makes the MOS device increases and produces and puncture, and then make the MOS device damage too early, reduced the useful life of MOS device.
Therefore, common MOS device is difficult under high pressure to work adapt to the application of the electronic product of high power operation.
Summary of the invention
In view of this, the invention provides a kind of MOS device and manufacture method thereof, can work under high voltage, with the electronic product that is applicable to work under high power.
Technical scheme of the present invention is achieved in that
A kind of MOS device, comprise substrate, be formed at the grid structure on described substrate and lay respectively at drain region and the source area in the substrate of described grid structure both sides; Wherein,
Described substrate is provided with the first well region and the second well region, and described the first well region and the second well region join in the substrate of described grid structure bottom;
Described drain region is positioned at described the first well region;
Described source area is positioned at described the second well region;
On described drain region, be provided with antifuse element.
Further, described antifuse element comprises: be formed at the self-aligned silicide barrier layer on described drain region; And be formed at the contact hole on described self-aligned silicide barrier layer.
Further, described self-aligned silicide barrier material is silica, and thickness is 3 ~ 10 nanometers.
Further, described contact hole material is tungsten, and thickness is 200 ~ 400 nanometers.
Further, described the first well region is the N-type well region, and described the second well region is P type well region, and described drain region is N-type ion heavily doped drain region, and described source area is N-type ion heavy-doped source polar region.
Further, described the first well region is P type well region, and described the second well region is the N-type well region, and described drain region is P type ion heavily doped drain region, and described source area is P type ion heavy-doped source polar region.
A kind of manufacture method of MOS device comprises:
Substrate is provided, and the zones of different of described substrate is carried out respectively to Implantation to form the first well region and the second well region, and described the first well region and the second well region join in described substrate;
Form grid structure on described substrate, the joining part of described the first well region and the second well region is positioned at described grid structure bottom;
Carry out Implantation to form respectively drain region and source area in described the first well region and the second well region;
Form antifuse element on the substrate of described drain region.
Further, on the substrate of described drain region, form antifuse element, specifically comprise:
Form the self-aligned silicide barrier layer on described drain region;
Form contact hole on described self-aligned silicide barrier layer.
Further, described self-aligned silicide barrier layer is silica, adopts chemical vapour deposition (CVD) CVD method to make.
Further, described contact hole material is tungsten, adopts physical vapour deposition (PVD) PVD method to make.
Further, adopt the N-type Implantation to carry out light dope and form described the first well region, adopt P type Implantation to carry out light dope and form described the second well region, adopt the N-type Implantation to carry out heavy doping and form described drain region, adopt the N-type Implantation to carry out heavy doping and form described source area.
Further, adopt P type Implantation to carry out light dope and form described the first well region, adopt the N-type Implantation to carry out light dope and form described the second well region, adopt P type Implantation to carry out heavy doping and form described drain region, adopt P type Implantation to carry out heavy doping and form described source area.
From such scheme, can find out, MOS device of the present invention and manufacture method thereof, on the one hand, adopted anti-fuse structures in drain region, in this anti-fuse structures, used the self-aligned silicide barrier layer as insulating barrier, when the metal level in anti-fuse structures applies enough voltage, just can run through the self-aligned silicide barrier layer, and make the MOS break-over of device, on the other hand, the first well region in substrate and the second well region are that (the first well region is the N-type well region to two kinds of veriform well regions, the second well region is P type well region, perhaps the first well region is P type well region, the second well region is the N-type well region), this structure can increase the puncture voltage of MOS device.Therefore the present invention has promoted the operating voltage of MOS device, and then the electronic product that makes the MOS device to be adapted to work under high power.
The accompanying drawing explanation
The structural representation that Fig. 1 is MOS device of the present invention;
The flow chart that Fig. 2 is MOS device making method of the present invention;
Fig. 3 is the structure chart formed on substrate in MOS device making method of the present invention after the first well region and the second well region;
Fig. 4 is the structure chart after structure shown in Fig. 3 forms grid structure;
Fig. 5 is the structure chart formed in structure shown in Fig. 4 after drain region and source area;
Fig. 6 is the structure chart formed in structure shown in Fig. 5 after antifuse element.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
As shown in Figure 1, MOS device of the present invention, its structure mainly comprises the grid structure 2 on substrate 1, formation and substrate 1 and lays respectively at drain region 3 and the source area 4 in grid structure 2 both sides substrates 1, on drain region 3, is provided with antifuse element 5; Wherein, substrate 1 is provided with the first well region 6 second well regions 7, and the first well region 6 and the second well region 7 join in the substrate 1 of grid structure 2 bottoms; Drain region 3 is positioned at the first well region 6; Source area 4 is positioned at the second well region 7; Antifuse element 5 is stopped (SAB, Salicide Block) layer 51 and is deposited on contact hole 52 formations on this self-aligned silicide barrier layer 51 by the self-aligned silicide be deposited on drain region 3.Wherein, self-aligned silicide barrier layer 51 materials are silica, and thickness is 3 ~ 10 nanometers, and the material of contact hole 52 can be tungsten (W), and thickness is 200 ~ 400 nanometers.
In MOS device shown in Fig. 1, substrate 1 can comprise any can be as the basic material that builds semiconductor device thereon, such as silicon substrate, or make the silicon substrate of an isolated area or the silicon substrate on insulating material.
As the specific embodiment of polysilicon gate, the grid structure 2 formed on substrate 1 mainly comprises gate dielectric layer 21, polygate electrodes 22 and side wall (spacer) 23.Wherein, gate dielectric layer 21 materials are as silica; its Main Function is the electric leakage prevented between polygate electrodes 22 and substrate 1; side wall 23 materials are as silica; for the protection of polygate electrodes 22; when carrying out Implantation with formation drain region 3 and source area 4, thereby can prevent that heavy dose of Implantation from too approaching polygate electrodes 22 and causing Punchthrough with polygate electrodes 22 formation short circuits.
Above-mentioned MOS device provided by the invention can be NMOS(N-Metal-Oxide-Semiconductor, the N-type metal-oxide semiconductor (MOS)) device or PMOS(P-Metal-Oxide-Semiconductor, P-type mos) device.During as nmos device, the first well region 6 is the N-type well region, and the second well region 7 is P type well region, and drain region 3 is N-type ion heavily doped drain region, and source area 4 is N-type ion heavy-doped source polar region; During as the PMOS device, the first well region 6 is P type well region, and the second well region 7 is the N-type well region, and drain region 3 is P type ion heavily doped drain region, and source area 4 is P type ion heavy-doped source polar region.The N-type ion that formation N-type well region and the heavily doped drain region of N-type and source area adopt can adopt the phosphonium ion of 5 valencys, and the P type ion that formation P type well region and the heavily doped drain region of P type and source area adopt can adopt the boron ion of 3 valencys.
Above-mentioned MOS device provided by the invention, owing to having adopted the antifuse element 5 formed by self-aligned silicide barrier layer 51 and contact hole 52 on drain region 3, with do not adopt this antifuse element 5 and compare, only have the MOS device conduction that just can make self-aligned silicide barrier layer 51 puncture and make after the access voltage of contact hole 52 improves, thus can so that MOS device of the present invention can under higher operating voltage, just can start working.
Simultaneously, above-mentioned MOS device provided by the invention, the first well region 6 and the second well region 7 are that (the first well region 6 is P type well region for N-type well region while second well region 7 to two kinds of veriform well regions, perhaps the first well region 6 is that P type well region while second well region 7 is the N-type well region), and the first well region 6 and the second well region 7 join in the substrate 1 of grid structure 2 bottoms, and this structure can increase the puncture voltage of MOS device of the present invention.Drain region 3 and source area 4 are formed at respectively in the first well region 6 and the second well region 7, so drain region 3 and source area 4 to the first well regions 6 and the second well region 7 are smaller.
Due to the existence of antifuse element 5 and the structure of above-mentioned the first well region 6 and the second well region 7, make the operating voltage of MOS device of the present invention be improved, and then the electronic product that makes the MOS device to be adapted to work under high power.
The basic structure that said structure is MOS device provided by the invention, certainly on the basis of said structure, according to the design and processes requirement, also can form other each functional layer structure in MOS device and subsequent production technique, silicon nitride layer as the formation of MOS device surface, interlayer dielectric layer (ILD, Inter Layerdielectric), for isolating the shallow trench isolation of each MOS device from (STI, Shallow Trench Isolation) structure, in interlayer dielectric layer, form for contact hole (contact) of connecting each conductive layer etc., these structures are requisite structure in prior art or semiconductor circuit manufacture process, repeat no more herein.In MOS device of the present invention, contact hole 52 described in antifuse element 5 is contact hole of the prior art (contact), the formation of contact hole 52 is generally: first on MOS device (comprising self-aligned silicide barrier layer 51) surface, form interlayer dielectric layer, then form the hole ditch of a plurality of contact holes by photoetching and etching technics on interlayer dielectric layer, the equal break-through interlayer dielectric layer of a plurality of holes ditch, until the grid structure 2 of MOS device, drain region 3 and source area 4, afterwards at hole ditch plated metal (as tungsten) thus form contact hole (in the MOS device architecture as shown in Fig. 1, not shown with the contact hole that source area 4 is connected with grid structure 2).Above-mentioned MOS device architecture of the present invention, contact hole 52 contacts with self-aligned silicide barrier layer 51, and not direct through described self-aligned silicide barrier layer 51 and drain region 3 Surface Contacts.
As shown in Figure 2, above-mentioned MOS device provided by the invention is made by following steps:
Step 1: substrate is provided, and the zones of different of described substrate is carried out respectively to Implantation to form the first well region and the second well region, and described the first well region and the second well region join in described substrate;
Step 2: form grid structure on described substrate, the joining part of described the first well region and the second well region is positioned at described grid structure bottom;
Step 3: carry out Implantation to form respectively drain region and source area in described the first well region and the second well region;
Step 4: on the substrate of described drain region, form antifuse element.
Below in conjunction with Fig. 3 to Fig. 6, this process is elaborated.
Step 1: as shown in Figure 3, provide substrate 1, and the zones of different of described substrate 1 is carried out respectively to Implantation to form the first well region 6 and the second well region 7, and described the first well region 6 and the second well region 7 join in described substrate 1.
In this step 1, substrate 1 can comprise any can be as the basic material that builds semiconductor device thereon, such as silicon substrate, or make the silicon substrate of an isolated area or the silicon substrate on insulating material.
More specifically, the formation of the first well region 6 and the second well region 7, can form in conjunction with means such as mask, photoetching.As defined the first well region 6 and the second well region 7 on substrate 1 surface; At substrate 1 surface deposition mask, and utilize photoetching process to carry out etching to described mask, expose the substrate 1 that will form the first well region 6, then using mask as stopping that substrate 1 is carried out to Implantation forms the first well region 6; At substrate 1 surface deposition mask, and utilize photoetching process to carry out etching to described mask, expose the substrate 1 that will form the second well region 7, then using mask as stopping that substrate 1 is carried out to Implantation forms the second well region 7.
The first well region 6 and the second well region 7 are veriform well region: if will manufacture nmos device, the first well region 6 is the N-type well region, and the second well region 7 is P type well region; If manufacture the PMOS device, the first well region 6 is P type well region, and the second well region 7 is the N-type well region.Corresponding to N-type well region and P type well region, the ion that need to be injected is respectively N-type ion (as 5 valency phosphonium ions) and P type ion (as 3 valency boron ions).The formation of the first well region 6 and the second well region 7 adopts light dope to carry out.
Step 2: as shown in Figure 4, the joining part that forms grid structure 2, the first well regions 6 and the second well region 7 on substrate 1 is positioned at the bottom of grid structure 2.
In this step 2, grid structure 2 is to form on the substrate 1 of the joining part of the first well region 6 and the second well region 7.The forming process of grid structure 2 mainly comprises:
Deposit successively gate dielectric layer and polysilicon layer on whole substrate 1, utilize photoetching and etching technics to carry out etching formation stack to polysilicon layer and gate dielectric layer, this stack, as the gate dielectric layer 21 in Fig. 4 and polygate electrodes 22, exposes the substrate 1 of described stack both sides; Form side wall 23 in described stack both sides, the material of side wall 23 is as silica, can be by the device surface cvd silicon oxide and carry out directed etching formation.
Step 3: as shown in Figure 5, carry out Implantation to form respectively drain region 3 and source area 4 in the first well region 6 and the second well region 7.
In this step 3, adopt the heavy doping mode.If manufacture nmos device, in this step 3, adopt N-type ion (as 5 valency phosphonium ions) to carry out heavy doping to form drain region 3 and source area 4, the drain region 3 of the N-type that forms is positioned at the first well region 6 of N-type, and the source area 4 of the N-type that forms is positioned at the second well region 7 of P type; If manufacture the PMOS device, in this step 3, adopt P type ion (as the boron ion of 3 valencys) to carry out heavy doping to form drain region 3 and source area 4, the drain region 3 of the P type that forms is positioned at the first well region 6 of P type, and the source area 4 of the P type that forms is positioned at the second well region 7 of N-type.
Step 4: as shown in Figure 6, form antifuse element 5 on drain region 3.
Can comprise following sub-step in this step 4:
Step 41: form self-aligned silicide barrier layer 51 on drain region 3.
In this step 41, self-aligned silicide barrier layer 51 materials can be silica, adopt the common process preparation, as adopted silester (TEOS) and oxygen (O
2), adopt the chemical vapor deposition (CVD) method to make, because be in drain region 3 formation described self-aligned silicide barrier layers 51, in therefore existing technique, on whole device surface deposition self-aligned silicide barrier layer 51, remove on the self-aligned silicide barrier layer 51 that will be deposited on grid structure 2 and source area 4 by photoetching and lithographic method again, only retains the self-aligned silicide barrier layer 51 on drain region 3.
Step 42: form contact hole 52 on self-aligned silicide barrier layer 51.
The formation of contact hole 52 can be carried out in conjunction with prior art, as at the whole device surface deposition interlayer dielectric layer of (comprising self-aligned silicide barrier layer 51) (not shown in accompanying drawing), utilizing photoetching and etching technics to form the hole ditch of contact hole in described interlayer dielectric layer, the described interlayer dielectric layer of described hole ditch break-through is until expose self-aligned silicide barrier layer 51, in the ditch of hole, adopt as physical vapour deposition (PVD) (PVD afterwards, Physical Vapor Deposition) the method plated metal such as, as tungsten (W), to form contact hole 52, contact hole 52 contacts with self-aligned silicide barrier layer 51, directly with drain region 3, do not contact.
Through after above steps, can form MOS device provided by the present invention.
Each step institute's adopting process and method that MOS device of the present invention is manufactured, all can be realized by existing technique and method, and the details of wherein not introducing in detail all can be by obtaining in the existing known arrangement such as existing technological parameter and technical manual.
Above-mentioned MOS device of the present invention and manufacture method thereof, on the one hand, adopted anti-fuse structures in drain region, in this anti-fuse structures, used the self-aligned silicide barrier layer as insulating barrier, when the metal level in anti-fuse structures applies enough voltage, just can run through the self-aligned silicide barrier layer, and make the MOS break-over of device, on the other hand, the first well region in substrate and the second well region are that (the first well region is the N-type well region to two kinds of veriform well regions, the second well region is P type well region, perhaps the first well region is P type well region, the second well region is the N-type well region), this structure can increase the puncture voltage of MOS device.Therefore the present invention has promoted the operating voltage of MOS device, and then the electronic product that makes the MOS device to be adapted to work under high power.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (12)
1. a MOS device, comprise substrate, be formed at the grid structure on described substrate and lay respectively at drain region and the source area in the substrate of described grid structure both sides, it is characterized in that:
Described substrate is provided with the first well region and the second well region, and described the first well region and the second well region join in the substrate of described grid structure bottom;
Described drain region is positioned at described the first well region;
Described source area is positioned at described the second well region;
On described drain region, be provided with antifuse element.
2. MOS device according to claim 1, is characterized in that, described antifuse element comprises: be formed at the self-aligned silicide barrier layer on described drain region; And be formed at the contact hole on described self-aligned silicide barrier layer.
3. MOS device according to claim 2, is characterized in that, described self-aligned silicide barrier material is silica, and thickness is 3 ~ 10 nanometers.
4. MOS device according to claim 2, is characterized in that, described contact hole material is tungsten, and thickness is 200 ~ 400 nanometers.
5. according to the described MOS device of claim 1 to 4 any one, it is characterized in that: described the first well region is the N-type well region, and described the second well region is P type well region, and described drain region is N-type ion heavily doped drain region, and described source area is N-type ion heavy-doped source polar region.
6. according to the described MOS device of claim 1 to 4 any one, it is characterized in that: described the first well region is P type well region, and described the second well region is the N-type well region, and described drain region is P type ion heavily doped drain region, and described source area is P type ion heavy-doped source polar region.
7. the manufacture method of a MOS device comprises:
Substrate is provided, and the zones of different of described substrate is carried out respectively to Implantation to form the first well region and the second well region, and described the first well region and the second well region join in described substrate;
Form grid structure on described substrate, the joining part of described the first well region and the second well region is positioned at described grid structure bottom;
Carry out Implantation to form respectively drain region and source area in described the first well region and the second well region;
Form antifuse element on described drain region.
8. the manufacture method of MOS device according to claim 7, is characterized in that, on the substrate of described drain region, forms antifuse element, specifically comprises:
Form the self-aligned silicide barrier layer on described drain region;
Form contact hole on described self-aligned silicide barrier layer.
9. the manufacture method of MOS device according to claim 8, is characterized in that, described self-aligned silicide barrier layer is silica, adopts chemical vapour deposition (CVD) CVD method to make.
10. the manufacture method of MOS device according to claim 8, is characterized in that, described contact hole material is tungsten, adopts physical vapour deposition (PVD) PVD method to make.
11. the manufacture method according to the described MOS device of claim 7 to 10 any one, it is characterized in that: adopt the N-type Implantation to carry out light dope and form described the first well region, adopt P type Implantation to carry out light dope and form described the second well region, adopt the N-type Implantation to carry out heavy doping and form described drain region, adopt the N-type Implantation to carry out heavy doping and form described source area.
12. the manufacture method according to the described MOS device of claim 7 to 10 any one, it is characterized in that: adopt P type Implantation to carry out light dope and form described the first well region, adopt the N-type Implantation to carry out light dope and form described the second well region, adopt P type Implantation to carry out heavy doping and form described drain region, adopt P type Implantation to carry out heavy doping and form described source area.
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