CN103454854A - Yield rate improving method of photolithographic mask - Google Patents
Yield rate improving method of photolithographic mask Download PDFInfo
- Publication number
- CN103454854A CN103454854A CN2012101702341A CN201210170234A CN103454854A CN 103454854 A CN103454854 A CN 103454854A CN 2012101702341 A CN2012101702341 A CN 2012101702341A CN 201210170234 A CN201210170234 A CN 201210170234A CN 103454854 A CN103454854 A CN 103454854A
- Authority
- CN
- China
- Prior art keywords
- sub
- photoetching
- assist features
- resolution assist
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
The invention discloses a yield improving method of photolithographic mask. The method adds supporting graphics on a photolithography sub-resolution assistance feature. Through adding small supporting graphics on a photolithography sub-resolution assistance feature, the method makes the photoresist to form some larger photoresist shapes in some areas, thus increases the adhesive force between the photoresist and the substrate, avoids the collapse of the photoresist, and achieves the goal of improving yield rate of photolithographic mask.
Description
Technical field
The present invention relates to SIC (semiconductor integrated circuit) and manufacture field, particularly relate to a kind of Yield lmproved method of lithography mask version.
Background technology
At present, in semiconductor technology, photoetching process is in order to promote the technological ability of self, generally the technology node at 65nm just starts to have increased photoetching Sub-resolution assist features (SRAF, Sub-resolution Assist Features), these auxiliary patterns are because physical size is less than normal lithography design figure, they are by changing light intensity by the light distribution after reticle, make the light intensity of normal lithography design figure be strengthened, and the light intensity of self does not reach requirement due to the resolution of photoresist, can on silicon chip, not develop and form pattern.But the manufacture craft of such reticle requires very high, because the size of auxiliary pattern is more much smaller than normal lithography design figure, is generally 1/5～1/4 of exposure wavelength, so price several times of cutting blocks for printing of normal optical often.Because the dimension of picture of auxiliary pattern is more much smaller than normal figure, so, in the process of making in reticle, photoresist is easy to the phenomenon that collapses while forming these auxiliary patterns, especially in the situation that poor focusing.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of Yield lmproved method of lithography mask version, and it can improve the yield with the mask plate of photoetching Sub-resolution assist features.
For solving the problems of the technologies described above, the Yield lmproved method of lithography mask version of the present invention, be on the photoetching Sub-resolution assist features, to increase to support figure.
Described support figure can be placed around the photoetching Sub-resolution assist features, also can be placed on one side of photoetching Sub-resolution assist features.
The present invention by increasing some little support figures on the photoetching Sub-resolution assist features, make photoresist form larger photoresist pattern in part, thereby increased the adhesion of photoresist and substrate, avoided photoresist to collapse, reached the purpose that promotes the reticle yield.
The accompanying drawing explanation
Fig. 1 be the embodiment of the present invention increase the photoetching Sub-resolution assist features schematic diagram of triangular support figure.
Fig. 2 be the embodiment of the present invention increase the photoetching Sub-resolution assist features schematic diagram of trapezoidal support figure.
Embodiment
For technology contents of the present invention, characteristics and effect being had more specifically, understand, existing in conjunction with illustrated embodiment, details are as follows:
The Yield lmproved method of the lithography mask version of the present embodiment is the placed around support figure at the photoetching Sub-resolution assist features, as illustrated in fig. 1 and 2.
In order not affect the pattern of normal figure, supporting on figure, the size on that limit of close photoetching Sub-resolution assist features (hereinafter referred to as long limit) is greater than the size away from that limit (hereinafter referred to as minor face) of photoetching Sub-resolution assist features, in general, the size on long limit can be 0.3～1.5 times of photoetching Sub-resolution assist features width, the size of minor face can be 0～1 times of photoetching Sub-resolution assist features width, and long limit generally is no more than 1.5 times of photoetching Sub-resolution assist features width to the distance of minor face.Therefore, the shape that supports figure is preferably triangle or trapezoidal, but also can meet the geometric figure of above-mentioned dimensional requirement or the complex figure be comprised of geometric figure with other.
Support figure and can evenly place around the photoetching Sub-resolution assist features, also can inhomogeneously place.Supporting figure and supporting the distance in the line orientations along the photoetching Sub-resolution assist features (being vertical direction in Fig. 1,2) between figure is 10～50 nanometers.At the end of photoetching Sub-resolution assist features, support figure and can place closelyer, support the spacing between the support figure at place, centre position that spacing between figure can be less than the photoetching Sub-resolution assist features.
Claims (7)
1. the Yield lmproved method of lithography mask version, is characterized in that, increases on the photoetching Sub-resolution assist features and support figure.
2. method according to claim 1, is characterized in that, described support figure is placed around the photoetching Sub-resolution assist features, or be placed on one side of photoetching Sub-resolution assist features.
3. method according to claim 1, is characterized in that, supporting figure and supporting the distance in the line orientations along the photoetching Sub-resolution assist features between figure is 10～50 nanometers.
4. according to any one described method in claims 1 to 3, it is characterized in that, on described support figure, the size on the limit of close photoetching Sub-resolution assist features is greater than the size away from the limit of photoetching Sub-resolution assist features.
5. method according to claim 4, it is characterized in that, on described support figure, the limit of close photoetching Sub-resolution assist features is of a size of 0.3～1.5 times of photoetching Sub-resolution assist features width, is of a size of 0～1 times of photoetching Sub-resolution assist features width away from the limit of photoetching Sub-resolution assist features.
6. method according to claim 5, is characterized in that, on described support figure, is no more than 1.5 times of photoetching Sub-resolution assist features width to the distance on the limit away from the photoetching Sub-resolution assist features near the limit of photoetching Sub-resolution assist features.
7. method according to claim 1, is characterized in that, described support figure be shaped as triangle or trapezoidal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101702341A CN103454854A (en) | 2012-05-28 | 2012-05-28 | Yield rate improving method of photolithographic mask |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101702341A CN103454854A (en) | 2012-05-28 | 2012-05-28 | Yield rate improving method of photolithographic mask |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103454854A true CN103454854A (en) | 2013-12-18 |
Family
ID=49737386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012101702341A Pending CN103454854A (en) | 2012-05-28 | 2012-05-28 | Yield rate improving method of photolithographic mask |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103454854A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101408723A (en) * | 2007-10-09 | 2009-04-15 | 中芯国际集成电路制造(上海)有限公司 | Light shield capable of improving yield |
| US20090159965A1 (en) * | 2007-12-21 | 2009-06-25 | Hynix Semiconductor Inc. | Semiconductor device and method for fabricating the same |
| CN101488450A (en) * | 2008-01-14 | 2009-07-22 | 国际商业机器公司 | Methods for forming a composite pattern including printed resolution assist features |
| CN102097362A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Method for forming mask layer and etching method |
-
2012
- 2012-05-28 CN CN2012101702341A patent/CN103454854A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101408723A (en) * | 2007-10-09 | 2009-04-15 | 中芯国际集成电路制造(上海)有限公司 | Light shield capable of improving yield |
| US20090159965A1 (en) * | 2007-12-21 | 2009-06-25 | Hynix Semiconductor Inc. | Semiconductor device and method for fabricating the same |
| CN101488450A (en) * | 2008-01-14 | 2009-07-22 | 国际商业机器公司 | Methods for forming a composite pattern including printed resolution assist features |
| CN102097362A (en) * | 2009-12-15 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Method for forming mask layer and etching method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4792096B2 (en) | A template pattern design method, a template manufacturing method, and a semiconductor device manufacturing method. | |
| CN101458446B (en) | Optical approaching correction, photo mask production and graphic method | |
| US8524423B2 (en) | Method of forming assist feature patterns | |
| JP2006303498A5 (en) | ||
| CN101957556B (en) | Mask picture modification method, mask manufacturing method and optical proximity correction method | |
| CN102122113A (en) | Photoetching method | |
| CN101458442B (en) | Production of layout and photo mask and graphic method | |
| CN100561340C (en) | The method of optical close correction | |
| WO2017041438A1 (en) | Optical mask plate and exposure system | |
| US20110024879A1 (en) | Method to reduce pre-alignment error using multi-notch pattern or in combination with flat side | |
| JP2012089636A (en) | Nano-imprint method | |
| CN103454854A (en) | Yield rate improving method of photolithographic mask | |
| CN103576469B (en) | Photoresist exposure device | |
| CN103019042B (en) | Method for improving stability of alignment precision of high-transparency mask plate | |
| JP2018163335A (en) | Photomask and method for manufacturing display device | |
| CN107643651B (en) | Design method of photoetching auxiliary pattern | |
| US8822104B2 (en) | Photomask | |
| JP2013021153A (en) | Method for manufacturing imprint mold | |
| JP2010076134A (en) | Nanoimprint mold | |
| US7781126B2 (en) | Mask and pattern forming method by using the same | |
| JP6316036B2 (en) | Photomask manufacturing method | |
| JP6415186B2 (en) | Evaluation mask, evaluation method, exposure apparatus, and article manufacturing method | |
| CN103424993A (en) | Photoetching key dimension measurement mark | |
| CN103913954B (en) | A kind of large chip exposure method and chip | |
| KR20100093773A (en) | Photo mask |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140116 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20140116 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
|
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20131218 |