CN103441142A - Sige heterojunction bipolar transistor - Google Patents
Sige heterojunction bipolar transistor Download PDFInfo
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- CN103441142A CN103441142A CN2013103707912A CN201310370791A CN103441142A CN 103441142 A CN103441142 A CN 103441142A CN 2013103707912 A CN2013103707912 A CN 2013103707912A CN 201310370791 A CN201310370791 A CN 201310370791A CN 103441142 A CN103441142 A CN 103441142A
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- sige
- heterojunction bipolar
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Abstract
The invention provides a method for designing a SiGe heterojunction bipolar transistor, and belongs to the fields of micro-electronics and solid electronics. The method relates to a distribution method of germanium contents in a base region specifically comprising a first stage area, a gradient area and a second stage area. The content value of the germanium in the first stage area and the content value of the germanium in the second stage area are constant, and the content values of the germanium in the gradient area are increased in a linear mode. Under the condition that the total contents of the germanium in the base region are not increased, the temperature stability of current gain of the SiGe heterojunction bipolar transistor based on the distribution method of the germanium contents in the base region is better, early voltage is high, the collected early voltage is higher, and the application range of the transistor is enlarged. Meanwhile, under the condition that characteristic frequency of the device is not lost much, breakdown voltage is increased, and accordingly the quality factor of the transistor is improved.
Description
Technical field
The present invention relates to a kind of SiGe heterojunction bipolar transistor (HBT), particularly a kind of base Germanium content profiles method that improves SiGe heterojunction bipolar transistor device performance.
Background technology
SiGe HBT be take " energy band engineering " as basis, is one of emphasis device of studying both at home and abroad at present.After in the SiGe heterojunction transistor, base mixes the germanium component, can regulate device base germanium component and obtain higher current gain.In addition, after germanium mixes base, the ell of device profit voltage increases; Simultaneously energy gap reduce make in base to induce electric field, reduced Base Transit Time, thereby improved the cut-off frequency of device.Therefore, the SiGe heterojunction transistor has high-frequency, low-power consumption, the characteristics such as low noise, and can with traditional Si technique and CMOS technique compatible advantage mutually.
The SiGe heterojunction transistor base Germanium content profiles of prior art often adopts distributed rectangular, the method for triangle and trapezoidal profile.These distribution modes, in the situation that base germanium component total content is identical, although can obtain higher currentgainβ, can be lost a lot of ell profit voltage V
athereby, greatly reduce the long-pending β V of ell profit voltage
a.Simultaneously, be accompanied by the variation of temperature, the temperature stability fluctuation of its current gain is larger.In addition, in prior art be raising device electric breakdown strength BV
cEO, often to lose larger characteristic frequency f
t.
In order not increase base germanium total content, cause the SiGe layer to arrive critical thickness, thereby the phenomenon of relaxation occurs.Therefore, the present invention wishes to propose the method for a kind of base Germanium content profiles, at base germanium component total content, under identical condition, improves current gain temperature stabilization coefficient and the ell profit voltage V of SiGe HBT device
athereby, improve the long-pending β V of ell profit voltage
a.Simultaneously, wish do not losing too many characteristic frequency f
tsituation under, improve puncture voltage BV
cEO, to improve the quality factor of device.
Fig. 1 shows three examples of the SiGe heterojunction transistor base Germanium content profiles of prior art, and these three examples are divided into distributed rectangular 2, Triangle-Profile 4, and trapezoidal profile 6.Identical for guaranteeing that base mixes the total content of germanium, therefore the Ge content in three examples can be set as follows:
In prior art in rectangle Germanium content profiles mode 2 examples the germanium component be 12%; Germanium component in prior art intermediate cam shape Germanium content profiles mode 4 examples is the Ge content X near emitter one side group district
0be 6%, near the Ge content X of collector electrode base
wbbe 18%; In prior art in trapezoidal Germanium content profiles mode 6 examples the germanium component be set as the Ge content X near emitter one side group district
0be 6%, the trapezoidal flex point Y of place
0in the position, base, be 2W
b/ 3, near the Ge content X of collector electrode base
wbbe 15%.
Although in prior art, rectangle Germanium content profiles 2 can obtain very high current gain, because there is not the Germanium content profiles of gradual change in base, lacked built-in drift field.This built-in drift field can accelerate transporting of charge carrier at base region, thereby reduces the characteristic frequency that Base Transit Time improves device.Therefore, the characteristic frequency of distributed rectangular 2 devices and ell profit voltage minimum in example.
For the drift field that keeps prior art SiGe HBT gradual change Ge content to produce, the present invention proposes the modification to existing SiGeHBT base Germanium content profiles method, the method can be improved the performance of existing SiGe HBT device.
Summary of the invention
The present invention is intended to improve by changing SiGe HBT base Germanium content profiles the temperature stability of device current gain, and improves the long-pending β V of ell profit voltage of device
aand quality factor f
t* BV
cEO.
In order to achieve the above object, a kind of SiGe heterojunction bipolar transistor of the present invention comprises collector region, base region, emitter region, it is characterized in that: the Germanium content profiles that described base region comprises the SiGe layer is that staged increases progressively distribution mode, and the average Germanium content of SiGe layer is no more than 20%.；
Described base region comprises the SiGe floor and is divided into the first rank district 8, gradient zones 10, and second-order district 12;
The Ge content in described the first rank district 8 is greater than 0, and the Ge content value is constant, and the Ge content value is no more than 12%;
The width in described the first rank district 8 is greater than 0, and is less than 50% of base width;
The Germanium content profiles of described gradient zones 10 is that linear increment distributes, and the Ge content initial value equals the Ge content value in the first rank district 8;
The width of described gradient zones is greater than 0, and is less than 50% of base width;
The Ge content value in described second-order district 12 is greater than the first rank district 8 Ge content values, and the Ge content value is constant;
The Ge content value in second-order district 12 is no more than 30%;
Described second-order district 12 width are greater than 0, and are less than 50% of base width.
Beneficial effect
Fig. 3 shows the TCAD characteristic curve that SiGe HBT device of the present invention base Ge content staged is distributed in current gain under different temperatures, with prior art base Germanium content profiles, compares, and the currentgainβ of device of the present invention has reduced temperature sensitivity.
Fig. 4 shows the β V of Ge content staged distribution of the present invention and prior art Germanium content profiles SiGe HBT device
acurve, can find out, the ell profit voltage that Ge content staged distribution of the present invention has greatly improved device amasss.
The present invention proposes the method for a kind of SiGe heterojunction transistor base Germanium content profiles, has improved the temperature stability of SiGe HBT device current gain, has enlarged the range of application of device; Improved the ell profit voltage V of device simultaneously
aand the long-pending β V of ell profit voltage
a.And in the situation that do not lose too many device feature frequency, increased the puncture voltage BV of device
cEOthereby, improved the quality factor f of device
t* BV
cEO.According to the present invention, obtain the raising of device performance by changing heterojunction transistor narrow base Germanium content profiles, do not increasing in the total content situation of germanium, can not cause the SiGe layer to approach critical thickness, avoided occurring the phenomenon of relaxation.
The accompanying drawing explanation
Fig. 1 shows the exemplary plot of SiGe heterojunction transistor base Germanium content profiles in prior art.
Fig. 2 shows the enforcement illustration of the SiGe heterojunction transistor base Germanium content profiles according to the present invention.
Fig. 3 illustrates according to the current gain of base of the present invention Germanium content profiles device and varies with temperature curve chart, with making comparisons of the SiGe heterojunction transistor base germanium component of prior art.
Fig. 4 shows base of the present invention Germanium content profiles and prior art Germanium content profiles device ell profit voltage amasss the curve chart in the different temperatures scope.
Embodiment
The manufacture method of the embodiment of the present invention is different from the method for prior art except the epitaxial step of base SiGe layer region, and other steps all are same as prior art, take the enforcement of LOCOS isolation technology this SiGe heterojunction transistor as example illustrates of commonly using.
1, on 10～20 Ω .cm P types<100 > silicon materials, adopt the industry passing method to form photoetching contraposition sign;
2, on the described silicon materials of the 1st step, adopt the method for industry universal to carry out the dry oxidation of 850 ℃, thickness is 40nm, then the method for carrying out industry universal carries out n type buried layer NBL alignment, is with glue NBL buried regions arsenic to inject, and implantation dosage is 3 * 10
15/ cm
3, Implantation Energy is 100KeV, and after completing the NBL injection, after the injection of employing industry universal, the method for removing photoresist is removed photoresist, carries out the method for industry universal and carries out the NBL propelling, and temperature is 1150 ℃, and 180 minutes time, atmosphere is inert atmosphere of nitrogen;
3, on the 2nd step process basis, adopt the method for industry universal to carry out p type buried layer PBL alignment, be with glue PBL buried regions boron to inject, implantation dosage is 5 * 10
13/ cm
3, Implantation Energy is 150KeV, after completing the NBL injection, after the injection of employing industry universal, the method for removing photoresist is removed photoresist;
4, on the 3rd step process basis, adopt the method for industry universal to float the photooxidation layer, then adopt the RPCVD method of industry universal to carry out the N-type silicon epitaxy, resistivity is 0.4 Ω .cm, epitaxy layer thickness is 0.6 μ m;
5, on the basis completed at the 4th step epitaxy technique, adopt the method for industry universal to carry out 850 ℃ of dry oxidations, oxidated layer thickness is 30nm, adopt again the method for industry universal to carry out the silicon nitride growth of LPCVD, thickness is 100nm, then adopt the method photoetching locos region of industry universal, adopt the dry method silicon nitride etch method of industry universal to etch away the outer silicon nitride of transistor active area, adopt again the cover carving method of industry universal, carry out transistor active area isolating trenches stopband glue boron in addition and inject, implantation dosage is 3 * 10
14/ cm
3, Implantation Energy is 60KeV, after completing injection, after the injection of employing industry universal, the method for removing photoresist is removed photoresist;
6, on the 5th step process basis, adopt the steam oxidation method of industry universal to carry out the place oxidation, temperature is 1000 ℃, and oxidated layer thickness is 600nm-700nm, after completing the place oxidation, adopt the wet method removal silicon nitride method of industry universal to carry out Nitride Strip;
7, on the 6th step process basis, adopt the cover carving method of industry universal, carry out collector electrode band glue phosphorus and inject, implantation dosage is 4 * 10
15/ cm
3, Implantation Energy is 150KeV, and after completing injection, after the injection of employing industry universal, the method for removing photoresist is removed photoresist, and the method for annealing of the rear employing industry universal that removes photoresist carries out the inert atmosphere of nitrogen annealing activation technology of 30 minutes of 900 ℃;
8, on the 7th step process basis, adopt the wet etching method of industry universal, removing the transistor active area (is base, collector region) oxide layer, expose transistor active area silicon face, adopt again the dry oxidation method of industry universal to carry out thin oxidation, temperature is 850 ℃, oxidated layer thickness is 30nm, then carry out polycrystalline deposition in the LPCVD polycrystalline deposition method that adopts again industry universal, temperature is 550 ℃, polycrystalline thickness is 50nm-70nm, adopt the photoetching method of industry universal to make base by lithography, adopt general method dry etching to fall the 50nm-70nm polycrystalline, and take polysilicon as mask, erode the 30nm oxide layer by general wet process,
9, on the 8th step process basis, adopt the SiGe epitaxy method of the RPCVD of industry universal to carry out SiGe base extension, the Ge of SiGe base extension distributes and adopts characterization method of the present invention, for the total content with germanium in Germanium content profiles example in base in prior art consistent, an embodiment of Germanium content profiles mode of the present invention is: near emitter place the first equally distributed Ge content in rank district 8, be 6%, and gradient flex point Y
1in position, SiGe base, be W
bthe thickness on the/3, first rank district 8 is taken as 13nm; Near collector electrode place second-order district 12 equally distributed Ge contents, be 18%, the thickness in second-order district 12 is taken as 13nm; The gradient zones Ge content at middle part, SiGe base 10 is that gradient distributes, near Y
1the end Ge content is 6%, near Y
2the end Ge content is 18%, and gradient flex point Y2 is 2W in the position, base
b/ 3, the thickness of gradient zones is taken as 14nm, and SiGe base middle part 10 carries out equally distributed boron doping, and concentration is 4e19, and base SiGe distributes as shown in Figure 2;
10, on the 9th step process basis, adopt the photoetching method of industry universal, photoetching dry etching fall except the SiGe layer beyond interior outer base area and the polycrystal layer of following 50nm-70nm, adopt again the method for industry universal to carry out PECVD deposit silicon dioxide, thickness is 90nm-110nm, adopt the method for industry universal to carry out LPCVD polycrystalline resilient coating, temperature is 550 ℃, thickness is 50nm-70nm, make emitter-window by lithography with general photoetching method, fall the 50nm-70nm polycrystalline with general dry etching, and dry etching falls the PECVD silicon dioxide of 70nm-90nm, fall 20nm-30nm silicon dioxide with general wet etching again, expose the base silicon face,
11, on the 10th step process basis, adopt the method for industry universal to carry out the growth of original position phosphorus doping emitter-polysilicon, 630 ℃ of temperature, thickness is 150nm, the polycrystalline square resistance is less than 20 ohm of every squares, adopt universal method to make emitter by lithography, then original position phosphorus doping and 50nm-70nm liner polysilicon beyond dry etching hair loss emitter-base bandgap grading;
12, on the 11st step process basis, adopt the method for industry universal to make again base stage and collector contact hole by lithography, dry etching falls PECVD and the part thermal oxide layer of 100-120nm, then wet method erodes the 30nm oxide layer;
13, on the 12nd step process basis, adopt the thick platinum of method sputter 50nm of industry universal, carrying out 550 ℃ of platinum annealing and platinum peels off, and then the AlCuSi metal level of sputter 100nm titanium and 50nm titanium nitride layer and 500nm, adopt universal method photoetching dry etching to go out emitter, base stage, collector electrode metal electrode, carry out 400 ℃ of nitrogen hydrogen alloys 15 minutes by general method again, finally complete the making of device.
Omitted the cleaning of well-known, obvious industry universal, the simple procedure such as remove photoresist in above-mentioned steps, this is conventional for one of ordinary skill in the art, specifically is not described in detail here.
Claims (10)
1. a SiGe heterojunction bipolar transistor, comprise collector region, base region, emitter region; Wherein said base region comprises the SiGe layer, and the Germanium content profiles of described SiGe layer is that staged increases progressively distribution mode, and the average Germanium content of SiGe layer is no more than 20%.
2. SiGe heterojunction bipolar transistor as claimed in claim 1, it is characterized in that: the Ge content of described base SiGe layer is that staged increases progressively distribution, specifically can be divided into the first rank district (8), gradient zones (10), and second-order district (12).
3. a kind of SiGe heterojunction bipolar transistor as claimed in claim 2, is characterized in that the Ge content in described the first rank district (8) is greater than 0, and content value is constant.
4. SiGe heterojunction bipolar transistor as claimed in claim 3, is characterized in that the Ge content value in described the first rank district (8) is no more than 12%.
5. SiGe heterojunction bipolar transistor as claimed in claim 3, is characterized in that the width in described the first rank district (8) is greater than 0, and be less than 50% of base width.
6. SiGe heterojunction bipolar transistor as claimed in claim 2, the Germanium content profiles that it is characterized in that described gradient zones (10) is that linear increment distributes, the Ge content initial value equals the Ge content value in the first rank district (8).
7. SiGe heterojunction bipolar transistor as claimed in claim 6, is characterized in that the width of described gradient zones (10) is greater than 0, and be less than 50% of base width.
8. SiGe heterojunction bipolar transistor as claimed in claim 2, is characterized in that the Ge content value in described second-order district (12) is greater than the first rank district (8) Ge content value, and content value is constant.
9. SiGe heterojunction bipolar transistor as claimed in claim 8, is characterized in that the Ge content value in described second-order district (12) is no more than 30%.
10. SiGe heterojunction bipolar transistor as claimed in claim 8, is characterized in that described second-order district (12) width is greater than 0, and be less than 50% of base width.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104900752A (en) * | 2015-04-14 | 2015-09-09 | 中国电子科技集团公司第四十四研究所 | Black silicon layer preparation method and black silicon PIN photoelectric detector preparation method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040256635A1 (en) * | 2001-12-11 | 2004-12-23 | Matsushita Electric Industrial Co., Ltd. | Hetero bipolar transistor |
| TW200729487A (en) * | 2005-11-04 | 2007-08-01 | Atmel Corp | Method and system for providing a heterojunction bipolar transistor having Si-Ge extensions |
| US20130009280A1 (en) * | 2011-07-06 | 2013-01-10 | International Business Machines Corporation | Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases |
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2013
- 2013-08-22 CN CN2013103707912A patent/CN103441142A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040256635A1 (en) * | 2001-12-11 | 2004-12-23 | Matsushita Electric Industrial Co., Ltd. | Hetero bipolar transistor |
| TW200729487A (en) * | 2005-11-04 | 2007-08-01 | Atmel Corp | Method and system for providing a heterojunction bipolar transistor having Si-Ge extensions |
| US20130009280A1 (en) * | 2011-07-06 | 2013-01-10 | International Business Machines Corporation | Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104900752A (en) * | 2015-04-14 | 2015-09-09 | 中国电子科技集团公司第四十四研究所 | Black silicon layer preparation method and black silicon PIN photoelectric detector preparation method |
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Application publication date: 20131211 |