CN103427927B - Clock synchronization realizing method and system for MPLS-TP network - Google Patents
Clock synchronization realizing method and system for MPLS-TP network Download PDFInfo
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Abstract
The invention provides a clock synchronization realizing method and system for an MPLS-TP network. The method comprises the steps of recording the time stamp of packaged PTP1588V2 messages of the MPLS-TP, and upgrading the value of the fixed reserved domain of the PTP1588V2 messages according to the time stamp; generating corresponding processing orders according to the packaging format of the PTP1588V2 messages; compiling the PTP1588V2 messages according to the processing orders; conducting synchronous treatment on the compiled PTP1588V2 messages. The device comprises a wire card and an ASIC integrated chip. The method and device simplify designs, reduce cost, and solve the problem of time stamp treatment.
Description
Technical field
The present invention relates to the communications field, more particularly to a kind of MPLS（Multi-Protocol Label Switching are more
Protocol label is exchanged）The synchronous method and device of-TP real-time performances clock.
Background technology
MPLS-TP networkings are MPLS Transport Profile, are to have merged T-MPLS and tradition MPLS networkings skill
Art, for solving the problems, such as the intercommunication of T-MPLS and tradition MPLS.
PTN (Packet Transport Network, grouping conveying network) is mainly used in returning for mobile or data service
Pass, belong to transmission network category, be relatively adapted to transmitting data service, but PTN needs whole network clock synchronization, PTN is to the same of clock
Step is mainly reflected in two aspects：1. carrying TDM（Time division multiplexing）Business or with PSTN (Public Switched
Telephone Network, PSTN) intercommunication when, need TDM seam provide synchronizing function.②
When PTN carries NodeB business, as the 3G business base stations of TD-CDMA, CDMA2000, WiMAX type need to provide high accuracy
Time synchronization information.PTN is relatively adapted to using MPLS-TP network transmitting data information, so MPLS-TP network is also required to tool
There is the ability of transmission high precision clock.
Existing Clock Synchronization Technology includes：Synchronous ether technology, TOP（Timing Over Packet-swithing, bag
Passing time）Technology, NTP（Network Time Protocol, NTP）、GPS（Global Positioning
System, global positioning system）Time service, PTP1588V2 technologies.Clock is transmitted on networking using PTP1588V2 wherein relative
Other several simultaneous techniquess have low cost, high precision and can be while the advantage such as passing time and frequency, is widely used
On PTN network equipment.
Two layers or three-layer network are carried on as existing PTP1588 standards provide only PTP1588V2, and MPLS-TP nets
Road does not have related standard definition, if but PTN adopts MPLS-TP network transmitting data information, and entered using PTP1588V2
Row clock synchronization, then must make MPLS-TP networkings support PTP1588V2, to meet when PTN operates in MPLS-TP networkings to height
The demand of accuracy clock.
The content of the invention
It is an object of the present invention to provide a kind of MPLS-TP network realizes the synchronous method and device of clock, to solve
The synchronous problem of MPLS-TP network clock.
The invention provides a kind of MPLS-TP network realizes the synchronous method of clock, comprise the following steps：
The timestamp of the PTP1588V2 messages of the MPLS-TP encapsulation that record is received, and it is above-mentioned according to above-mentioned update of time stamp
The value of the fixed reserved field of PTP1588V2 messages；
According to the encapsulation format of above-mentioned PTP1588V2 messages, corresponding process instruction is generated；
According to above-mentioned process instruction, edlin is entered to above-mentioned PTP1588V2 messages；
Timestamp synchronization process is carried out to the PTP1588V2 messages after editor.
Preferably, above-mentioned fixed reserved field is the correction domain of above-mentioned PTP1588V2 messages.
Preferably, the encapsulation format of above-mentioned PTP1588V2 messages includes the PTP1588V2 messages of section layer encapsulation, LSP（Mark
Sign switching path）The PTP1588V2 messages of layer encapsulation, the PTP1588V2 messages of PW layers encapsulation, the ether of PW layers encapsulation
PTP1588V2 messages and the IP PTP1588V2 messages of PW layers encapsulation.
Preferably, the timestamp of the PTP1588V2 messages of above-mentioned record is received MPLS-TP encapsulation, and according to it is above-mentioned when
Between the value step of the stamp fixed reserved field that updates above-mentioned PTP1588V2 messages be specially：
The timestamp of the PTP1588V2 messages that record is received；
Judge that whether above-mentioned PTP1588V2 messages are the PTP1588V2 messages of MPLS-TP encapsulation；If so, then take out above-mentioned
PTP1588V2 messages correct the currency in domain, deduct the timestamp of above-mentioned record, and update above-mentioned with the difference for obtaining
PTP1588V2 messages correct the value in domain；Otherwise, the above-mentioned PTP1588V2 messages of transparent transmission.
Preferably, the above-mentioned encapsulation format according to PTP1588V2 messages, generates corresponding process instruction step and specifically includes
Following steps：
Determine the encapsulation format of above-mentioned PTP1588V2 messages；
If the encapsulation format of above-mentioned PTP1588V2 messages is the PTP1588V2 messages of section layer encapsulation, above-mentioned
The link number of PTP1588V2 messages is logical port number and VLAN（Virtual Local Area Network, virtual local area
Net）Sum；If the PTP1588V2 messages of LSP layers encapsulation, then the link number of above-mentioned PTP1588V2 messages is logical port number
With LSP label sum；If the PTP1588V2 messages of PW layers encapsulation, the ether PTP1588V2 messages of PW layers encapsulation and PW layers
The IP of encapsulation（Internet Protocol, Internet protocol）PTP1588V2 messages, the then chain of above-mentioned PTP1588V2 messages
The number of connecing is logical port number, LSP label and PW label sums；
According to the link number of above-mentioned PTP1588V2 messages, search the configuration information of above-mentioned link, obtain its port attribute and
Type of message；
According to above-mentioned port attribute and type of message, the process instruction of above-mentioned PTP1588V2 messages is generated.
Preferably, it is above-mentioned according to process instruction, edit step is carried out to above-mentioned PTP1588V2 messages and is specially：
Parse above-mentioned PTP1588V2 messages；
According to analysis result and above-mentioned process instruction, asymmetry compensation and timestamp are carried out to above-mentioned PTP1588V2 messages
Process.
Preferably, the above-mentioned PTP1588V2 messages to after editor carry out timestamp synchronization process step and are specially：
Obtain the timestamp of above-mentioned PTP1588V2 messages；
Determine the type of message of above-mentioned PTP1588V2 messages；
If sync types and for two_step patterns simultaneously sourceportID the match is successful, or be Resp types and
For two_step patterns simultaneously sourceportID the match is successful, then the Time And Frequency for keeping in above-mentioned PTP1588V2 messages is extensive
Multiple timestamp and correction domain；If Req types, then RESP messages are generated；If Req types and be two_step patterns, then give birth to
Into follow_up messages, and the PTP1588V2 messages of above-mentioned Req types are sent into into queue queue, wait to be sent；If other
Type, then be directly forwarded to upper strata process；
Message sends the time to sending above-mentioned PTP1588V2 messages logging timestamp.
Invention further provides a kind of MPLS-TP network realizes the synchronous device of clock, including line card and ASIC collection
Into chip, very first time stamp processor in each input port of above-mentioned line card, is integrated with, above-mentioned ASIC integrated chips include
Row processor, downstream processor and network protocol processing engine, wherein,
The above-mentioned very first time stabs processor, for recording the time of the PTP1588V2 messages of the MPLS-TP for receiving encapsulation
Stamp, and the value of the fixed reserved field according to the above-mentioned PTP1588V2 messages of above-mentioned update of time stamp, by above-mentioned PTP1588V2 messages
It is sent to above-mentioned ASIC integrated chips；
Above-mentioned upstream processor, for the encapsulation format according to above-mentioned PTP1588V2 messages, generates corresponding process and refers to
Order；
Above-mentioned downstream processor, for the process instruction generated according to above-mentioned upstream processor, reports to above-mentioned PTP1588V2
Text enters edlin；
Above-mentioned network protocol processing engine, for carrying out the time to the PTP1588V2 messages Jing after above-mentioned downstream processor editor
Stamp synchronization process.
Preferably, the second timestamp processor is integrated with the port of the not connected line card of above-mentioned ASIC integrated chips, be used for
The timestamp of the PTP1588V2 messages of the MPLS-TP encapsulation that record ASIC integrated chips are received.
Preferably, said apparatus also include the 3rd timestamp processor, for the outside gps signal for accessing is converted into
The internal interface signal of network protocol processing engine is stated, and synchronous transfer gives above-mentioned network protocol processing engine.
Preferably, above-mentioned timestamp processor, for judging whether above-mentioned PTP1588V2 messages are MPLS-TP encapsulation
PTP1588V2 messages；And when above-mentioned PTP1588V2 messages are the PTP1588V2 messages of MPLS-TP encapsulation, take out above-mentioned
PTP1588V2 messages correct the currency in domain, deduct the timestamp of above-mentioned record, and update above-mentioned with the difference for obtaining
PTP1588V2 messages correct the value in domain.
Preferably, above-mentioned upstream processor, for determining the encapsulation format of above-mentioned PTP1588V2 messages；And above-mentioned
When the encapsulation format of PTP1588V2 messages is the PTP1588V2 messages of section layer encapsulation, calculating logic port numbers and VLAN sums,
Obtain the link number of above-mentioned PTP1588V2 messages；It is the encapsulation of LSP layers in the encapsulation format of above-mentioned PTP1588V2 messages
During PTP1588V2 messages, calculating logic port numbers and LSP label sum obtain the link number of above-mentioned PTP1588V2 messages；
The encapsulation format of above-mentioned PTP1588V2 messages is the PTP1588V2 messages of PW layers encapsulation, the ether PTP1588V2 of PW layers encapsulation
During the IP PTP1588V2 messages of message and the encapsulation of PW layers, calculating logic port numbers, LSP label and PW label sums are obtained
To the link number of above-mentioned PTP1588V2 messages；And according to the link number of above-mentioned PTP1588V2 messages, search above-mentioned link
Configuration information, obtains its port attribute and type of message, and according to above-mentioned port attribute and type of message, generates above-mentioned
The process instruction of PTP1588V2 messages；
Above-mentioned downstream processor, for parsing above-mentioned PTP1588V2 messages；And according to analysis result and above-mentioned up process
The process instruction that device is generated, carries out asymmetry compensation to above-mentioned PTP1588V2 messages and timestamp is processed.
Preferably, above-mentioned network protocol processing engine, for obtaining the timestamp of above-mentioned PTP1588V2 messages；Determine above-mentioned
The type of message of PTP1588V2 messages；And the type of message in above-mentioned PTP1588V2 messages is sync types and is two_step
Pattern simultaneously sourceportID the match is successful, or be Resp types and for two_step patterns sourceportID simultaneously
With it is successful when, the Time And Frequency recovery time for keeping in above-mentioned PTP1588V2 messages and corrects domain at stamp；In above-mentioned PTP1588V2
When the type of message of message is Req types, RESP messages are generated；It is Req types in the type of message of above-mentioned PTP1588V2 messages
And when being two_step patterns, generate follow_up messages, and the PTP1588V2 messages of above-mentioned Req types are sent into into queuing team
Row, wait to be sent；When the type of message of above-mentioned PTP1588V2 messages is other types, will be above-mentioned PTP1588V2 messages direct
It is transmitted to upper strata process；And the time is sent to after in message, send above-mentioned PTP1588V2 messages logging timestamp；And
Local time stamp is periodically updated, and when the timing of above-mentioned timestamp information is sent to above-mentioned very first time stamp processor, second
Between stab processor and above-mentioned 3rd timestamp processor.
Preferably, above-mentioned very first time stamp processor, for receiving the timestamp that above-mentioned network protocol processing engine sends
During information, local time stamp is updated；
Above-mentioned second timestamp processor, for when the timestamp information that above-mentioned network protocol processing engine sends is received,
Update local time stamp；
Above-mentioned 3rd timestamp processor, for when the timestamp information that above-mentioned network protocol processing engine sends is received,
Update local time stamp.
The present invention only processes the PTP1588V2 messages that multiple line cards or non-thread clamping are received using a network protocol processing engine,
Design is simplified, cost is reduced；And the process of PTP1588V2 clocks on MPLS-TP is supported, the entrances such as line card are solved
Timestamp process problem, and network protocol processing engine timestamp coordinate and stationary problem.
Description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the present invention, this
Bright schematic description and description does not constitute inappropriate limitation of the present invention for explaining the present invention.In the accompanying drawings：
Fig. 1 is the theory diagram that MPLS-TP network of the present invention realizes the synchronous device preferred embodiment of clock；
Fig. 2 is that MPLS-TP network of the present invention realizes the synchronous method preferred embodiment flow chart of clock；
Fig. 3 is the PTP1588V2 message format schematic diagrams of MPLS-TP encapsulation；
Fig. 4 is a typical application example schematic diagram of the present invention.
Specific embodiment
In order that the technical problem to be solved, technical scheme and beneficial effect are clearer, clear, below tie
Drawings and Examples are closed, the present invention will be described in further detail.It should be appreciated that specific embodiment described herein is only used
To explain the present invention, it is not intended to limit the present invention.
As shown in figure 1, be the theory diagram that MPLS-TP network of the present invention realizes the synchronous device preferred embodiment of clock,
The present embodiment includes the ASIC integrated chips 20 of the line card 10, N+1 port with N group I/O ports and the 3rd time
Stamp processor 30, is integrated with very first time stamp processor 101, N number of delivery outlet of line card 10 in each input port of line card 10
It is connected with the 1-N port of ASIC integrated chips 20；ASIC integrated chips 20 include the second timestamp processor 201, up
With 203 and network protocol processing engine 204, the second timestamp processor 201 is integrated in not band line card to processor 202, downstream processor
Port in, as the N+1 port of ASIC integrated chips 20 is without line card, therefore in the present embodiment, the second timestamp process
Device 201 is integrated in the port, wherein,
The very first time stabs processor 101, for recording the PTP1588V2 messages of the MPLS-TP encapsulation that line card 10 is received
Timestamp, and the value of the fixed reserved field according to the above-mentioned PTP1588V2 messages of above-mentioned update of time stamp, specially：Judge above-mentioned
Whether PTP1588V2 messages are the PTP1588V2 messages of MPLS-TP encapsulation；And be MPLS-TP in above-mentioned PTP1588V2 messages
During the PTP1588V2 messages of encapsulation, the currency that above-mentioned PTP1588V2 messages correct domain is taken out, the time of above-mentioned record is deducted
Stamp, and the value that above-mentioned PTP1588V2 messages correct domain is updated with the difference for obtaining, above-mentioned PTP1588V2 messages are sent to
ASIC integrated chips 02；And when the timestamp information that network protocol processing engine 204 sends is received, update local time stamp；
Second timestamp processor 201, for recording what the MPLS-TP that ASIC integrated chips 20 are received was encapsulated
The timestamp of PTP1588V2 messages；And when the timestamp information that network protocol processing engine 204 sends is received, update local
Timestamp；
Upstream processor 202, for the encapsulation format according to above-mentioned PTP1588V2 messages, generates corresponding process instruction；
Specially：Determine the encapsulation format of PTP1588V2 messages；And the encapsulation format in above-mentioned PTP1588V2 messages is encapsulated for section layer
PTP1588V2 messages when, calculating logic port numbers and VLAN sums obtain the link number of above-mentioned PTP1588V2 messages；Upper
When the encapsulation format for stating PTP1588V2 messages is the PTP1588V2 messages of LSP layers encapsulation, calculating logic port numbers and LSP label
Sum, obtains the link number of above-mentioned PTP1588V2 messages；It is the encapsulation of PW layers in the encapsulation format of above-mentioned PTP1588V2 messages
During the IP PTP1588V2 messages of PTP1588V2 messages, the ether PTP1588V2 messages of PW layers encapsulation and the encapsulation of PW layers, meter
Logical port number, LSP label and PW label sums are calculated, the link number of above-mentioned PTP1588V2 messages is obtained；And according to above-mentioned
The link number of PTP1588V2 messages, searches the configuration information of above-mentioned link, obtains its port attribute and type of message, and according to
Above-mentioned port attribute and type of message, generate the process instruction of PTP1588V2 messages；
Downstream processor 203, for the process instruction generated according to upstream processor 202, to above-mentioned PTP1588V2 messages
Enter edlin；Specially：Parsing PTP1588V2 messages, and referred to according to the process of analysis result and the generation of upstream processor 202
Order, carries out asymmetry compensation to PTP1588V2 messages and timestamp is processed；
Network protocol processing engine 204, for carrying out timestamp to the PTP1588V2 messages Jing after downstream processor 203 is edited
Synchronization process；Specially：Obtain the timestamp of PTP1588V2 messages；Determine the type of message of PTP1588V2 messages；And
The type of message of PTP1588V2 messages be sync types and for two_step patterns simultaneously sourceportID the match is successful, or
Person be Resp types and for two_step patterns simultaneously sourceportID the match is successful when, keep in PTP1588V2 messages when
Between with frequency retrieval timestamp and correction domain；When the type of message of PTP1588V2 messages is Req types, RESP messages are generated；
PTP1588V2 messages type of message be Req types and for two_step patterns when, generate follow_up messages, and will
The PTP1588V2 messages of Req types send into queue queue, wait to be sent；It is other classes in the type of message of PTP1588V2 messages
During type, upper strata process is directly forwarded to；And PTP1588V2 of the time to after, in dispatcher queue queue is sent in message
Message logging timestamp, periodically update local time stamp, and the timing of above-mentioned timestamp information are sent to very first time stamp
Processor 101, the second time processor 201 and the 3rd timestamp processor 30；
3rd timestamp processor 30, for the outside gps signal for accessing is converted in above-mentioned network protocol processing engine
Portion's interface signal, and synchronous transfer is to network protocol processing engine 204；And receiving the time that network protocol processing engine 204 sends
During stamp information, local time stamp is updated.
As shown in Fig. 2 being that MPLS-TP network of the present invention realizes the synchronous method preferred embodiment flow chart of clock, this reality
Apply example and specifically include following steps：
Step S001：The timestamp of the PTP1588V2 messages that record is received；
Step S002：Judge that whether above-mentioned PTP1588V2 messages are the PTP1588V2 messages of MPLS-TP encapsulation, if so,
Then execution step S003；Otherwise, execution step S023；
As shown in figure 3, be MPLS-TP encapsulation PTP1588V2 message format schematic diagrams, the encapsulation of PTP1588V2 messages
Form includes the PTP1588V2 messages of section layer encapsulation, as shown in a in figure；The PTP1588V2 messages of LSP layers encapsulation, such as in figure
B shown in；The PTP1588V2 messages of PW layers encapsulation, as shown in the c in figure；The ether PTP1588V2 messages of PW layers encapsulation, such as
Shown in d in figure；And the IP PTP1588V2 messages of PW layers encapsulation, as shown in the e in figure；According to agreement, in figure, DA tables
Show destination address；SA represents source address；VLAN0 represents ground floor VLAN；VLAN1 represents second layer VLAN；VLAN2 represents the 3rd
Layer VLAN；Etype represents ethernet type value；Label_ptp represents MPLS Label For PTP；Label_1 is represented
The ground floor label of MPLS；Label_2 represents the second layer label of MPLS；Gach represents Generic associated
channel；PTP1588_payload represents PTP1588 message payloads；Ethernet_PTP1588_payload represents ether
Net encapsulation PTP1588 message payloads；IP_PTP1588_payload represents the PTP1588 message payloads of IP encapsulation；IP head
Represent IP heads；UDP head represent UDP heads；CRC table shows CRC check value；
Step S003：The currency that above-mentioned PTP1588V2 messages correct domain is taken out, the timestamp of above-mentioned record is deducted, and
The value that above-mentioned PTP1588V2 messages correct domain is updated with the difference for obtaining；
In the present embodiment, fixed reserved field is the correction domain of above-mentioned PTP1588V2 messages；
If the input port that above-mentioned PTP1588V2 messages are line cards 01 receives, when step S001- step S003 is by first
Between stab processor 101；It is not connected with the port of line card and receives if above-mentioned PTP1588V2 messages are ASIC integrated chips 20, walks
Rapid S001- steps S003 are performed by the second timestamp processor 201；The PTP1588V2 messages of Jing timestamps processor process, quilt
It is sent to upstream processor 202 to process；
Step S004：Upstream processor 202 determines the encapsulation format of above-mentioned PTP1588V2 messages, if the encapsulation of section layer
PTP1588V2 messages, then execution step S005；If the PTP1588V2 messages of LSP layers encapsulation, then execution step S006；If
The IP PTP1588V2 of the PTP1588V2 messages, the ether PTP1588V2 messages of PW layers encapsulation and the encapsulation of PW layers of the encapsulation of PW layers
Message, then steps performed S007;
Step S005：Calculating logic port numbers and VLAN sums, obtain the link number of above-mentioned PTP1588V2 messages, proceed to
Step S008 is performed；
Step S006：Calculating logic port numbers and LSP label sum, obtain the link number of above-mentioned PTP1588V2 messages, turn
Enter the execution of step S008；
Step S007：Calculating logic port numbers, LSP label and PW label sums, obtain above-mentioned PTP1588V2 messages
Link number；
Step S008：According to the link number of above-mentioned PTP1588V2 messages, the configuration information of above-mentioned link is searched, which is obtained
Port attribute and type of message；
Step S009：According to above-mentioned port attribute and type of message, the process instruction of above-mentioned PTP1588V2 messages is generated,
And above-mentioned instruction is transferred to into downstream processor 203；
Step S010：Downstream processor 203 parses above-mentioned PTP1588V2 messages；
Step S011：According to analysis result and the process instruction for receiving, asymmetric benefit is carried out to above-mentioned PTP1588V2 messages
Repay and timestamp is processed, PTP1588V2 messages are sent to into protocol engine 204 afterwards；
Step S012：Protocol engine 204 obtains the timestamp of above-mentioned PTP1588V2 messages；
Step S013：Determine the type of message of above-mentioned PTP1588V2 messages, if sync types or Req types, then perform
Step S014；If Resp types, then execution step S018；If other types, then execution step S024；
Step S014：Judge whether above-mentioned PTP1588V2 messages are two_step patterns, if so, then execution step S015；
Otherwise, execution step S017；
Step S015：Follow_up messages are waited to be matched；
Step S016：Whether the match is successful to judge the sourceportID of above-mentioned PTP1588V2 messages, if so, above-mentioned
PTP1588V2 Message processings terminate；Otherwise, execution step S017；
Step S017：Keep in Time And Frequency stamp recovery time of above-mentioned PTP1588V2 messages and correct domain, terminate；
Step S018：Generate RESP messages；
Step S019：Judge whether above-mentioned PTP1588V2 messages are two_step patterns, if so, then execution step S020；
Otherwise, execution step S021；
Step S020：Generate follow_up messages；
Step S021：Above-mentioned PTP1588V2 messages are sent into into queue queue, waits to be sent；
Step S022：Message sends the time to sending above-mentioned PTP1588V2 messages logging timestamp, terminate；
Step S023：The above-mentioned PTP1588V2 messages of transparent transmission, terminate；
Step S024：Above-mentioned PTP1588V2 messages are directly forwarded to into upper strata process, are terminated.
As shown in figure 4, being a typical application example schematic diagram of the present invention；In figure, MPLS-TP-1588 parts are
MPLS-TP networkings, including edge PE node, intermediate P-node；CE nodes pass through PTP1588V2 messages that ether or IP encapsulate with
PE nodes are communicated；It is OC that typical application is CE nodes（Ordinary Clock, ordinary clock） /BC（Boundary
Clock, boundary clock）Node, PE nodes are OC/BC nodes, and P node can be TC（Transparent Clock, when transparent
Clock）Or BC nodes；1588 agreements of MPLS-TP are run between PE-P-PE, ether can be utilized so between PE and CE nodes
Or the PTP1588V2 messages of IP encapsulation are capable of achieving the clock synchronization between CE and PE nodes, and PE nodes are run between PE nodes
The PTP1588V2 messages of MPLS-TP encapsulation, enter row clock synchronization, so as to realize the clock synchronization of whole network.In PE and PE nodes
Between can also run PW encapsulation PTP1588V2 messages, between adjacent node target phase layer encapsulation PTP1588V2 messages,
The PTP1588V2 messages of LSP encapsulation are run on end-to-end node.The wherein distribution of label can adopt LDP（label
Distribution protocol, tag distribution protocol）Agreement.Pdelay measurement mechanism is run between two points for example, it is main
1588 messages of node delivery section layer encapsulation automatically reply reciprocal section of layer envelope to from node after receiving detection process from node
The PTP1588V2 messages of dress, realize that the time between principal and subordinate shakes hands, and reach the effect of measurement main and subordinate node link delay.
Described above illustrates and describes the preferred embodiments of the present invention, but as previously mentioned, it should be understood that the present invention is not
Form disclosed herein is confined to, the exclusion to other embodiment is not to be taken as, and be can be used for various other combinations, modification
And environment, and can be carried out by the technology or knowledge of above-mentioned teaching or association area in invention contemplated scope described herein
Change.And change that those skilled in the art are carried out and change be without departing from the spirit and scope of the present invention, then all should be in institute of the present invention
In attached scope of the claims.
Claims (14)
1. a kind of MPLS-TP network realizes the synchronous method of clock, it is characterised in that comprise the following steps：
The timestamp of the PTP1588V2 messages of the MPLS-TP encapsulation that record is received, and according to the update of time stamp
The value of the fixed reserved field of PTP1588V2 messages；
According to the encapsulation format of the PTP1588V2 messages, corresponding process instruction is generated；
According to the process instruction, edlin is entered to the PTP1588V2 messages；
Timestamp synchronization process is carried out to the PTP1588V2 messages after editor.
2. method according to claim 1, it is characterised in that the fixed reserved field is the PTP1588V2 messages
Correction domain.
3. method according to claim 1, it is characterised in that the encapsulation format of the PTP1588V2 messages includes section layer
The PTP1588V2 messages of encapsulation, the PTP1588V2 messages of LSP layers encapsulation, the PTP1588V2 messages of PW layers encapsulation, the encapsulation of PW layers
Ether PTP1588V2 messages and PW layers encapsulation IP PTP1588V2 messages.
4. method according to claim 2, it is characterised in that the PTP1588V2 of the MPLS-TP encapsulation that the record is received
The timestamp of message, and the value step of the fixed reserved field of PTP1588V2 messages is specially according to the update of time stamp：
The timestamp of the PTP1588V2 messages that record is received；
Judge that whether the PTP1588V2 messages are the PTP1588V2 messages of MPLS-TP encapsulation；If so, then take out described
PTP1588V2 messages correct the currency in domain, deduct the timestamp of the record, and update described with the difference for obtaining
PTP1588V2 messages correct the value in domain；Otherwise, PTP1588V2 messages described in transparent transmission.
5. method according to claim 4, it is characterised in that the encapsulation format according to PTP1588V2 messages, generates
Corresponding process instruction step specifically includes following steps：
Determine the encapsulation format of the PTP1588V2 messages；
If the encapsulation format of the PTP1588V2 messages is the PTP1588V2 messages of section layer encapsulation, the PTP1588V2 reports
The link number of text is logical port number and VLAN sums；If the PTP1588V2 messages of LSP layers encapsulation, the then PTP1588V2
The link number of message is logical port number and LSP label sum；If the PTP1588V2 messages of PW layers encapsulation, PW layers are encapsulated
Ether PTP1588V2 messages and the IP PTP1588V2 messages of PW layers encapsulation, then the link number of the PTP1588V2 messages is
Logical port number, LSP label and PW label sums；
According to the link number of the PTP1588V2 messages, the configuration information of the link is searched, its port attribute and message is obtained
Type；
According to the port attribute and type of message, the process instruction of the PTP1588V2 messages is generated.
6. method according to claim 1, it is characterised in that described according to process instruction, to the PTP1588V2 messages
Carry out edit step to be specially：
Parse the PTP1588V2 messages；
According to analysis result and the process instruction, asymmetry compensation is carried out to the PTP1588V2 messages and timestamp is processed.
7. method according to claim 1, it is characterised in that the PTP1588V2 messages after described couple of editor carry out the time
Stamp synchronization process step is specially：
Obtain the timestamp of the PTP1588V2 messages；
Determine the type of message of the PTP1588V2 messages；
If sync types and for two_step patterns simultaneously sourceportID the match is successful, or be Resp types and be
Two_step patterns simultaneously sourceportID the match is successful, then the Time And Frequency for keeping in the PTP1588V2 messages recovers
Timestamp and correction domain；If Req types, then RESP messages are generated；If Req types and be two_step patterns, then generate
Follow_up messages, and the PTP1588V2 messages of the Req types are sent into into queue queue, wait to be sent；If other classes
Type, then be directly forwarded to upper strata process；
Message sends the time to sending the PTP1588V2 messages logging timestamp.
8. a kind of MPLS-TP network realizes the synchronous device of clock, including line card and ASIC integrated chips, it is characterised in that institute
State be integrated with each input port of line card the very first time stamp processor, the ASIC integrated chips include upstream processor,
Downstream processor and network protocol processing engine, wherein,
The very first time stabs processor, for recording the timestamp of the PTP1588V2 messages of the MPLS-TP for receiving encapsulation, and
The value of the fixed reserved field of PTP1588V2 messages according to the update of time stamp, the PTP1588V2 messages are sent to
The ASIC integrated chips；
The upstream processor, for the encapsulation format according to the PTP1588V2 messages, generates corresponding process instruction；
The downstream processor, for the process instruction generated according to the upstream processor, enters to the PTP1588V2 messages
Edlin；
The network protocol processing engine, it is same for carrying out timestamp to the PTP1588V2 messages after the downstream processor editor described in
Step process.
9. device according to claim 8, it is characterised in that the port Nei Ji of the not connected line card of the ASIC integrated chips
Into there is the second timestamp processor, for record the PTP1588V2 messages of the MPLS-TP encapsulation that ASIC integrated chips are received when
Between stab.
10. device according to claim 8 or claim 9, it is characterised in that described device also includes the 3rd timestamp processor,
For the outside gps signal for accessing to be converted into the internal interface signal of the network protocol processing engine, and synchronous transfer to described
Network protocol processing engine.
11. devices according to claim 10, it is characterised in that the very first time stamp processor and second time
Stamp processor, for judging that whether the PTP1588V2 messages are the PTP1588V2 messages of MPLS-TP encapsulation；And described
When PTP1588V2 messages are the PTP1588V2 messages of MPLS-TP encapsulation, the current of the PTP1588V2 messages correction domain is taken out
Value, deducts the timestamp of the record, and updates the value that the PTP1588V2 messages correct domain with the difference for obtaining.
12. devices according to claim 10, it is characterised in that the upstream processor, it is described for determining
The encapsulation format of PTP1588V2 messages；And the PTP1588V2 messages encapsulation format be section layer encapsulation PTP1588V2
During message, calculating logic port numbers and VLAN sums obtain the link number of the PTP1588V2 messages；In the PTP1588V2
When the encapsulation format of message is the PTP1588V2 messages of LSP layers encapsulation, calculating logic port numbers and LSP label sum obtain institute
State the link number of PTP1588V2 messages；In the PTP1588V2 reports that the encapsulation format of the PTP1588V2 messages is the encapsulation of PW layers
During the IP PTP1588V2 messages of text, the ether PTP1588V2 messages of PW layers encapsulation and the encapsulation of PW layers, calculating logic port
Number, LSP label and PW label sums, obtain the link number of the PTP1588V2 messages；And according to the PTP1588V2
The link number of message, searches the configuration information of the link, obtains its port attribute and type of message, and is belonged to according to the port
Property and type of message, generate the process instruction of the PTP1588V2 messages；
The downstream processor, for parsing the PTP1588V2 messages；And given birth to according to analysis result and the upstream processor
Into process instruction, asymmetry compensation and timestamp are carried out to the PTP1588V2 messages and are processed.
13. devices according to claim 10, it is characterised in that the network protocol processing engine, it is described for obtaining
The timestamp of PTP1588V2 messages；Determine the type of message of the PTP1588V2 messages；And in the PTP1588V2 messages
Type of message be sync types and for two_step patterns simultaneously sourceportID the match is successful, or be Resp types and be
Two_step patterns simultaneously sourceportID when the match is successful, the Time And Frequency for keeping in the PTP1588V2 messages recovers
Timestamp and correction domain；When the type of message of the PTP1588V2 messages is Req types, RESP messages are generated；Described
The type of message of PTP1588V2 messages be Req types and for two_step patterns when, generate follow_up messages, and will be described
The PTP1588V2 messages of Req types send into queue queue, wait to be sent；It is which in the type of message of the PTP1588V2 messages
During his type, the PTP1588V2 messages are directly forwarded to into upper strata process；And the time is sent to after in message, send institute
State PTP1588V2 messages logging timestamp；And local time stamp is periodically updated, and timestamp information timing is sent out
Give the very first time stamp processor, the second timestamp processor and the 3rd timestamp processor.
14. devices according to claim 13, it is characterised in that the very first time stabs processor, for receiving
When stating the timestamp information that network protocol processing engine sends, local time stamp is updated；
The second timestamp processor, for when the timestamp information that the network protocol processing engine sends is received, updating
Local time stamp；
The 3rd timestamp processor, for when the timestamp information that the network protocol processing engine sends is received, updating
Local time stamp.
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