CN103426879B - Transient Voltage Suppressor and manufacture method thereof - Google Patents
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- CN103426879B CN103426879B CN201210161049.6A CN201210161049A CN103426879B CN 103426879 B CN103426879 B CN 103426879B CN 201210161049 A CN201210161049 A CN 201210161049A CN 103426879 B CN103426879 B CN 103426879B
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Abstract
The invention discloses a kind of Transient Voltage Suppressor, comprising: N type semiconductor substrate and the P type epitaxial loayer be formed on N type semiconductor substrate.Zener diode is made up of with the N type semiconductor substrate bottom this P+ buried regions the P+ buried regions on the surface being formed at N type semiconductor substrate.P type epi-layer surface directly over P+ buried regions is formed with a N+ district, N+ district and the upper diode of the composition of the P type epitaxial loayer bottom it.A P+ district is being formed with, P+ district and the P type epitaxial loayer bottom it and the lower diode of N type semiconductor substrate composition with the be separated by P type epi-layer surface of a lateral separation of upper diode.The invention also discloses a kind of manufacture method of Transient Voltage Suppressor.The N-type impurity of substrate of the present invention not easily spreads in the heat treatment process of technique, the Impurity Diffusion due to substrate can not be caused in epitaxial loayer to make the used up defect of the thickness of epitaxial loayer, the thickness of the epitaxial loayer formed needed for device can be reduced, reduce process costs.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of Transient Voltage Suppressor (TransientVoltageSuppressor, TVS); The invention still further relates to a kind of manufacture method of Transient Voltage Suppressor.
Background technology
TVS is a kind of high-effect protection device of diode form.When the two poles of the earth of TVS diode are subject to reverse transient state high energy impact events, it can with 10
-12the speed of second-time, becomes Low ESR by the high impedance of its two interpolar, absorbs the surge power up to thousands of watts, makes the voltage clamp of two interpolars in a predetermined value, effectively protects the precision components in electronic circuit, from the damage of various surge pulse.TVS diode has a very wide range of applications scope, in various circuit, transmission line and electric equipment, all can provide surge voltage protection.As household electrical appliance; Sound, video input; Electronic instrument; Instrument; Precision equipment; Computer system; Communication apparatus; IC circuit protection; AC and DC power supply; The every field such as the suppression of motor, relay noise.
The structure of existing TVS is made up of three diodes, is upper diode (TopDiode) respectively, lower diode (DownDiode) and be positioned at and imbed Zener diode (BuriedZenerDiode) immediately below diode.In order to realize response speed fast, the junction capacitance of upper diode and lower diode will very little.In order to realize very little junction capacitance, PN junction just must realize very light doping, to form a kind of structure of single side abrupt junction.The manufacture craft of existing TVS adopts the substrate of low-resistance P-type, then in the N-type epitaxy layer that Grown doping is very light.Upper diode and lower diode make to be formed in N-type epitaxy layer; Wherein, N-type epitaxy layer is all lower for the formation of the doping content of single side abrupt junction.But existing above-mentioned technique can produce following problem: because the thermal process in process engineering can cause the impurity of P type substrate to run into expansion, consume portion of epi layer, so epitaxial loayer must increase extra thickness.And the diffusion of boron impurities is quickly, therefore the additional thickness of epitaxial loayer is thicker, and this thickness additionally increased can be greater than the thickness needed for junction capacitance of the low upper diode of formation one and lower diode.Because epitaxy technique is the technique that a kind of cost compare is high, so and the thickness increased outward result in the increase of process costs.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of Transient Voltage Suppressor, can reduce the thickness of the epitaxial loayer formed needed for device, reduces process costs.The present invention also provides a kind of manufacture method of Transient Voltage Suppressor.
For solving the problems of the technologies described above, Transient Voltage Suppressor of the present invention comprises: N type semiconductor substrate; Be formed at the P type epitaxial loayer on described N type semiconductor substrate; P+ buried regions, be positioned at the surface of described N type semiconductor substrate and be diffused into the bottom of described P type epitaxial loayer, described P+ buried regions has certain transverse width, the described N type semiconductor substrate composition Zener diode of described P+ buried regions and its bottom section; Described P type epi-layer surface directly over described P+ buried regions is formed with a N+ district, this N+ district and the upper diode of described P type epitaxial loayer composition bottom it, the doping content of described P type epitaxial loayer is less than the doping content in described N+ district and makes described upper diode be a kind of structure of single side abrupt junction; With described on the be separated by described P type epi-layer surface of a lateral separation of diode be formed with a P+ district, this P+ district and the described P type epitaxial loayer bottom it and the lower diode of the composition of the described N type semiconductor substrate bottom described P+ district, described P+ district is used for described P type epitaxial loayer to draw, and the doping content of described P type epitaxial loayer is less than the doping content of described N type semiconductor substrate and makes described lower diode be a kind of structure of single side abrupt junction; On described all sides of diode described P type epitaxial loayer in be formed by diode ring on described around P type isolation well; In the vertical, the bottom extending to described P type epitaxial loayer from the top of described P type epitaxial loayer of described P type isolation well, the bottom of described P type isolation well and described P+ buried regions intersect and for being drawn by described P+ buried regions; Be formed in the described P type epitaxial loayer of all sides of described lower diode by described lower diode ring around N-type isolation well; In the vertical, the bottom extending to described P type epitaxial loayer from the top of described P type epitaxial loayer of described N-type isolation well.
Further improvement is, resistivity 0.0064 ohmcm ~ 0.014 ohmcm of described N type semiconductor substrate.
Further improvement is, the impurity of described P type epitaxial loayer is boron, and doping content is 1e13cm
-3~ 1e14cm
-3.
For solving the problems of the technologies described above, the manufacture method of Transient Voltage Suppressor of the present invention comprises the steps:
Step one, carry out P type ion implantation and form a P+ buried regions on the surface of N type semiconductor substrate, described P+ buried regions has certain transverse width, the described N type semiconductor substrate composition Zener diode of described P+ buried regions and its bottom section.
Step 2, described N type semiconductor substrate carries out epitaxial growth form P type epitaxial loayer.
Step 3, carry out P type ion implantation form P type isolation well in described P type epitaxial loayer, described P type isolation well is a circulating type structure, and the circle zone of described P type isolation well is upper diode area; In the vertical, the bottom extending to described P type epitaxial loayer from the top of described P type epitaxial loayer of described P type isolation well, the bottom of described P type isolation well and described P+ buried regions intersect and for being drawn by described P+ buried regions.
Step 4, carry out N-type ion implantation form N-type isolation well in described P type epitaxial loayer, described N-type isolation well is a circulating type structure, the circle zone of described N-type isolation well is lower diode area, and described lower diode area and described upper diode area are separated by a lateral separation.
Step 5, carry out N-type ion implantation described P type epi-layer surface of diode area on described and form a N+ district, this N+ district and the upper diode of described P type epitaxial loayer composition bottom it, the doping content of described P type epitaxial loayer is less than the doping content in described N+ district and makes described upper diode be a kind of structure of single side abrupt junction.
Step 6, carry out P type ion implantation and form a P+ district in the described P type epi-layer surface of described lower diode area, this P+ district and the described P type epitaxial loayer bottom it and the lower diode of the composition of the described N type semiconductor substrate bottom described P+ district, described P+ district is used for described P type epitaxial loayer to draw, and the doping content of described P type epitaxial loayer is less than the doping content of described N type semiconductor substrate and makes described lower diode be a kind of structure of single side abrupt junction.
Further improvement is, the process conditions of the P type ion implantation of the buried regions of P+ described in step one are: implanted dopant is boron or boron fluoride, and the dosage of injection is 1e14cm
-2~ 1e16cm
-2, Implantation Energy 10KeV ~ 50KeV.
Further improvement is, the process conditions of the P type ion implantation of the type of P described in step 3 isolation well are: implanted dopant is boron, and the dosage of injection is 2e14cm
-2~ 2e16cm
-2, Implantation Energy 35KeV ~ 150KeV.
Further improvement is, the process conditions of the N-type ion implantation of the isolation well of N-type described in step 4 are: implanted dopant is phosphorus, and the dosage of injection is 2e14cm
-2~ 1e15cm
-2, Implantation Energy 200KeV ~ 1000KeV.
Further improvement is, the process conditions of the N-type ion implantation in the district of N+ described in step 5 are: implanted dopant is arsenic, and the dosage of injection is 1e15cm
-2~ 1e16cm
-2, Implantation Energy 10KeV ~ 100KeV.
Further improvement is, the process conditions of the P type ion implantation in the district of P+ described in step 6 are: implanted dopant is boron, and the dosage of injection is 2e15cm
-2~ 2e16cm
-2, Implantation Energy 5KeV ~ 20KeV.
Further improvement is, resistivity 0.0064 ohmcm ~ 0.014 ohmcm of the substrate of N type semiconductor described in step one; The impurity of the type of P described in step 2 epitaxial loayer is boron, and doping content is 1e13cm
-3~ 1e14cm
-3.
The present invention, by adopting N type semiconductor substrate and the P type epitaxial loayer that is formed on N type semiconductor substrate, forms the doping content of the upper diode of TVS and the single side abrupt junction of lower diode with P type epitaxial loayer lower.Be the impurity that boron etc. is lighter relative to the impurity of P type semiconductor substrate in prior art, the N-type impurity of N type semiconductor substrate of the present invention is the impurity of the heavy types such as arsenic, so not easily the spreading in the heat treatment process of technique of N-type impurity, thus the Impurity Diffusion due to substrate can not be caused in epitaxial loayer to make the used up defect of the thickness of epitaxial loayer, as long as the thickness of such P type epitaxial loayer is arranged to meet and is formed the upper diode of TVS and the single side abrupt junction of lower diode and make the condition that the junction capacitance of diode and lower diode is less, thickness consumption to epitaxial loayer after the Impurity Diffusion not needing the extra thickness of increase by compensate due to the opposite types of substrate, so the present invention can reduce the thickness of the epitaxial loayer formed needed for device, reduce process costs.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of embodiment of the present invention Transient Voltage Suppressor;
Fig. 2 A-Fig. 2 E is the device architecture schematic diagram in each step of the manufacture method of embodiment of the present invention Transient Voltage Suppressor;
Fig. 3 is three diode structure schematic diagrames of embodiment of the present invention Transient Voltage Suppressor.
Embodiment
As shown in Figure 1, be the structural representation of embodiment of the present invention Transient Voltage Suppressor; Embodiment of the present invention Transient Voltage Suppressor comprises:
N type semiconductor substrate 1, this N type semiconductor substrate 1 has low resistance, has higher doping content, and the doping content of described N type semiconductor substrate 1 can meet follow-up formation Zener diode, and forms the needs of lower diode; As the N-type region of lower diode, the PN junction of lower diode can be made to be the structure of the single side abrupt junction mainly exhausted in p type island region.In the preferred embodiment, resistivity 0.0064 ohmcm ~ 0.014 ohmcm of described N type semiconductor substrate.
Be formed at the P type epitaxial loayer 2 on described N type semiconductor substrate 1; The doping content of this P type epitaxial loayer 2 is low doping concentration, and this doping content to meet in upper diode and lower diode as low-doped p type island region, the depletion region of diode and lower diode is mainly formed in p type island region and structure in single side abrupt junction.In the preferred embodiment, the impurity of described P type epitaxial loayer is boron, and doping content is 1e13cm
-3~ 1e14cm
-3, the thickness of described P type epitaxial loayer 8 microns ~ 10 microns.
P+ buried regions 3, be positioned at the surface of described N type semiconductor substrate 1 and be diffused into the bottom of described P type epitaxial loayer 2, described P+ buried regions 3 has certain transverse width, and the described N type semiconductor substrate 1 of described P+ buried regions 3 and its bottom section forms Zener diode.Described P+ buried regions 3 adopts P type ion implantation to be formed, and process conditions are: implanted dopant is boron or boron fluoride, and the dosage of injection is 1e14cm
-2~ 1e16cm
-2, Implantation Energy 10KeV ~ 50KeV.
Described P type epitaxial loayer 2 surface directly over described P+ buried regions 3 is formed with a N+ district 4, this N+ district 4 and the upper diode of described P type epitaxial loayer 2 composition bottom it; The doping content of described P type epitaxial loayer 2 is less than the doping content in described N+ district 4 and makes described upper diode be a kind of structure of single side abrupt junction.Described N+ district 4 adopts N-type ion implantation technology to be formed, and process conditions are: implanted dopant is arsenic, and the dosage of injection is 1e15cm
-2~ 1e16cm
-2, Implantation Energy 10KeV ~ 100KeV.
With described on be separated by described P type epitaxial loayer 2 surface of a lateral separation of diode be formed with a P+ district 5, the described N type semiconductor substrate 1 bottom this P+ district 5 and the described P type epitaxial loayer 2 bottom it and described P+ district 5 forms lower diode.Described P+ district 5 is for drawing described P type epitaxial loayer 2, and the doping content of described P type epitaxial loayer 2 is less than the doping content of described N type semiconductor substrate 1 and makes described lower diode be a kind of structure of single side abrupt junction.Described P+ district 5 adopts P type ion implantation technology to be formed, and process conditions are: implanted dopant is boron, and the dosage of injection is 2e15cm
-2~ 2e16cm
-2, Implantation Energy 5KeV ~ 20KeV.
On described all sides of diode described P type epitaxial loayer 2 in be formed by diode ring on described around P type isolation well 6; In the vertical, the bottom extending to described P type epitaxial loayer 2 from the top of described P type epitaxial loayer 2 of described P type isolation well 6, the bottom of described P type isolation well 6 and described P+ buried regions 3 intersect and for being drawn by described P+ buried regions 3.Described P type isolation well 6 adopts P type ion implantation technology to be formed, and process conditions are: implanted dopant is boron, and the dosage of injection is 2e14cm
-2~ 2e16cm
-2, Implantation Energy 35KeV ~ 150KeV.
Be formed in the described P type epitaxial loayer 2 of all sides of described lower diode by described lower diode ring around N-type isolation well 7; In the vertical, the bottom extending to described P type epitaxial loayer 2 from the top of described P type epitaxial loayer 2 of described N-type isolation well 7.Described N-type isolation well 7 adopts N-type ion implantation technology to be formed, and process conditions are: implanted dopant is phosphorus, and the dosage of injection is 2e14cm
-2~ 1e15cm
-2, Implantation Energy 200KeV ~ 1000KeV.
The N+ district 4 of described upper diode and the P+ district 5 of described lower diode are linked together by metal connecting line and form an electrode tip of device, and described N type semiconductor substrate 1 is drawn by a metal connecting line and formed another electrode tip of device; The annexation of described upper diode, described lower diode and described Zener diode can reference diagram 3.
As shown in Fig. 2 A to Fig. 2 E, it is the device architecture schematic diagram in each step of the manufacture method of embodiment of the present invention Transient Voltage Suppressor.The manufacture method of embodiment of the present invention Transient Voltage Suppressor comprises the steps:
Step one, as shown in Figure 2 A, carry out P type ion implantation and form a P+ buried regions 3 on the surface of N type semiconductor substrate 1, described P+ buried regions 3 has certain transverse width, and the described N type semiconductor substrate 1 of described P+ buried regions 3 and its bottom section forms Zener diode.
Wherein said N type semiconductor substrate 1 has low resistance, has higher doping content, and the doping content of described N type semiconductor substrate 1 can meet follow-up formation Zener diode, and forms the needs of lower diode; As the N-type region of lower diode, the PN junction of lower diode can be made to be the structure of the single side abrupt junction mainly exhausted in p type island region.In the preferred embodiment, resistivity 0.0064 ohmcm ~ 0.014 ohmcm of described N type semiconductor substrate.
The process conditions of the P type ion implantation of described P+ buried regions 3 are: implanted dopant is boron or boron fluoride, and the dosage of injection is 1e14cm
-2~ 1e16cm
-2, Implantation Energy 10KeV ~ 50KeV.
Step 2, as shown in Figure 2 B, described N type semiconductor substrate 1 carries out epitaxial growth and forms P type epitaxial loayer 2.The doping content of this P type epitaxial loayer 2 is low doping concentration, this doping content meets in upper diode and lower diode as low-doped p type island region, the depletion region of diode and lower diode is mainly formed in p type island region and structure in single side abrupt junction, make diode and lower diode junction capacitance low.In the preferred embodiment, the impurity of described P type epitaxial loayer is boron, and doping content is 1e13cm
-3~ 1e14cm
-3, the thickness of described P type epitaxial loayer 8 microns ~ 10 microns.
Wherein said P+ buried regions 3 can be diffused into the bottom of described P type epitaxial loayer 2 up spreading a segment distance in epitaxially grown pyroprocess.
Step 3, as shown in Figure 2 C, carry out P type ion implantation and form P type isolation well 6 in described P type epitaxial loayer 2, described P type isolation well 6 is a circulating type structure, and the circle zone of described P type isolation well 6 is upper diode area; In the vertical, the bottom extending to described P type epitaxial loayer 2 from the top of described P type epitaxial loayer 2 of described P type isolation well 6, the bottom of described P type isolation well 6 and described P+ buried regions 3 intersect and for being drawn by described P+ buried regions 3.
The process conditions of the P type ion implantation of described P type isolation well 6 are: implanted dopant is boron, and the dosage of injection is 2e14cm
-2~ 2e16cm
-2, Implantation Energy 35KeV ~ 150KeV.
Step 4, as shown in Figure 2 D, carry out N-type ion implantation and form N-type isolation well 7 in described P type epitaxial loayer 2, described N-type isolation well 7 is a circulating type structure, the circle zone of described N-type isolation well 7 is lower diode area, and described lower diode area and described upper diode area are separated by a lateral separation.
The process conditions of the N-type ion implantation of described N-type isolation well 7 are: implanted dopant is phosphorus, and the dosage of injection is 2e14cm
-2~ 1e15cm
-2, Implantation Energy 200KeV ~ 1000KeV.
Step 5, as shown in Figure 2 E, carry out N-type ion implantation and form a N+ district 4 in described P type epitaxial loayer 2 surface of diode area on described, this N+ district 4 and the upper diode of described P type epitaxial loayer 2 composition bottom it, the doping content of described P type epitaxial loayer 2 is less than the doping content in described N+ district 4 and makes described upper diode be a kind of structure of single side abrupt junction.
The process conditions of the N-type ion implantation in described N+ district 4 are: implanted dopant is arsenic, and the dosage of injection is 1e15cm
-2~ 1e16cm
-2, Implantation Energy 10KeV ~ 100KeV.
Step 6, as shown in Figure 2 E, carry out P type ion implantation and form a P+ district 5 on described P type epitaxial loayer 2 surface of described lower diode area, described N type semiconductor substrate 1 bottom this P+ district 5 and the described P type epitaxial loayer 2 bottom it and described P+ district 5 forms lower diode, described P+ district 5 is for drawing described P type epitaxial loayer 2, and the doping content of described P type epitaxial loayer 2 is less than the doping content of described N type semiconductor substrate 1 and makes described lower diode be a kind of structure of single side abrupt junction.
The process conditions of the P type ion implantation in described P+ district 5 are: implanted dopant is boron, and the dosage of injection is 2e15cm
-2~ 2e16cm
-2, Implantation Energy 5KeV ~ 20KeV.
Step 7, as described in Figure 1, forms metal connecting line and is linked together and form an electrode tip of device in the P+ district 5 of the N+ district 4 of described upper diode and described lower diode; Form metal connecting line described N type semiconductor substrate 1 is drawn and forms another electrode tip of device.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. a Transient Voltage Suppressor, is characterized in that, comprising:
N type semiconductor substrate;
Be formed at the P type epitaxial loayer on described N type semiconductor substrate;
P+ buried regions, be positioned at the surface of described N type semiconductor substrate and be diffused into the bottom of described P type epitaxial loayer, described P+ buried regions has certain transverse width, the described N type semiconductor substrate composition Zener diode of described P+ buried regions and its bottom section;
Described P type epi-layer surface directly over described P+ buried regions is formed with a N+ district, this N+ district and the upper diode of described P type epitaxial loayer composition bottom it, the doping content of described P type epitaxial loayer is less than the doping content in described N+ district and makes described upper diode be a kind of structure of single side abrupt junction;
With described on the be separated by described P type epi-layer surface of a lateral separation of diode be formed with a P+ district, this P+ district and the described P type epitaxial loayer bottom it and the lower diode of the composition of the described N type semiconductor substrate bottom described P+ district, described P+ district is used for described P type epitaxial loayer to draw, and the doping content of described P type epitaxial loayer is less than the doping content of described N type semiconductor substrate and makes described lower diode be a kind of structure of single side abrupt junction;
On described all sides of diode described P type epitaxial loayer in be formed by diode ring on described around P type isolation well; In the vertical, the bottom extending to described P type epitaxial loayer from the top of described P type epitaxial loayer of described P type isolation well, the bottom of described P type isolation well and described P+ buried regions intersect and for being drawn by described P+ buried regions;
Be formed in the described P type epitaxial loayer of all sides of described lower diode by described lower diode ring around N-type isolation well; In the vertical, the bottom extending to described P type epitaxial loayer from the top of described P type epitaxial loayer of described N-type isolation well.
2. Transient Voltage Suppressor as claimed in claim 1, is characterized in that: resistivity 0.0064 ohmcm ~ 0.014 ohmcm of described N type semiconductor substrate.
3. Transient Voltage Suppressor as claimed in claim 1, is characterized in that: the impurity of described P type epitaxial loayer is boron, and doping content is 1e13cm
-3~ 1e14cm
-3.
4. a manufacture method for Transient Voltage Suppressor, is characterized in that, comprises the steps:
Step one, carry out P type ion implantation and form a P+ buried regions on the surface of N type semiconductor substrate, described P+ buried regions has certain transverse width, the described N type semiconductor substrate composition Zener diode of described P+ buried regions and its bottom section;
Step 2, described N type semiconductor substrate carries out epitaxial growth form P type epitaxial loayer;
Step 3, carry out P type ion implantation form P type isolation well in described P type epitaxial loayer, described P type isolation well is a circulating type structure, and the circle zone of described P type isolation well is upper diode area; In the vertical, the bottom extending to described P type epitaxial loayer from the top of described P type epitaxial loayer of described P type isolation well, the bottom of described P type isolation well and described P+ buried regions intersect and for being drawn by described P+ buried regions;
Step 4, carry out N-type ion implantation form N-type isolation well in described P type epitaxial loayer, described N-type isolation well is a circulating type structure, the circle zone of described N-type isolation well is lower diode area, and described lower diode area and described upper diode area are separated by a lateral separation; In the vertical, the bottom extending to described P type epitaxial loayer from the top of described P type epitaxial loayer of described N-type isolation well;
Step 5, carry out N-type ion implantation described P type epi-layer surface of diode area on described and form a N+ district, this N+ district and the upper diode of described P type epitaxial loayer composition bottom it, the doping content of described P type epitaxial loayer is less than the doping content in described N+ district and makes described upper diode be a kind of structure of single side abrupt junction;
Step 6, carry out P type ion implantation and form a P+ district in the described P type epi-layer surface of described lower diode area, this P+ district and the described P type epitaxial loayer bottom it and the lower diode of the composition of the described N type semiconductor substrate bottom described P+ district, described P+ district is used for described P type epitaxial loayer to draw, and the doping content of described P type epitaxial loayer is less than the doping content of described N type semiconductor substrate and makes described lower diode be a kind of structure of single side abrupt junction.
5. the manufacture method of Transient Voltage Suppressor as claimed in claim 4, it is characterized in that: the process conditions of the P type ion implantation of the buried regions of P+ described in step one are: implanted dopant is boron or boron fluoride, the dosage of injection is 1e14cm
-2~ 1e16cm
-2, Implantation Energy 10KeV ~ 50KeV.
6. the manufacture method of Transient Voltage Suppressor as claimed in claim 4, it is characterized in that: the process conditions of the P type ion implantation of the type of P described in step 3 isolation well are: implanted dopant is boron, the dosage of injection is 2e14cm
-2~ 2e16cm
-2, Implantation Energy 35KeV ~ 150KeV.
7. the manufacture method of Transient Voltage Suppressor as claimed in claim 4, it is characterized in that: the process conditions of the N-type ion implantation of the isolation well of N-type described in step 4 are: implanted dopant is phosphorus, the dosage of injection is 2e14cm
-2~ 1e15cm
-2, Implantation Energy 200KeV ~ 1000KeV.
8. the manufacture method of Transient Voltage Suppressor as claimed in claim 4, it is characterized in that: the process conditions of the N-type ion implantation in the district of N+ described in step 5 are: implanted dopant is arsenic, the dosage of injection is 1e15cm
-2~ 1e16cm
-2, Implantation Energy 10KeV ~ 100KeV.
9. the manufacture method of Transient Voltage Suppressor as claimed in claim 4, it is characterized in that: the process conditions of the P type ion implantation in the district of P+ described in step 6 are: implanted dopant is boron, the dosage of injection is 2e15cm
-2~ 2e16cm
-2, Implantation Energy 5KeV ~ 20KeV.
10. the manufacture method of Transient Voltage Suppressor as claimed in claim 4, is characterized in that: resistivity 0.0064 ohmcm ~ 0.014 ohmcm of the substrate of N type semiconductor described in step one; The impurity of the type of P described in step 2 epitaxial loayer is boron, and doping content is 1e13cm
-3~ 1e14cm
-3.
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| TWI601287B (en) * | 2016-12-21 | 2017-10-01 | 新唐科技股份有限公司 | Transient-voltage-suppression (tvs) diode device and method of fabricating the same |
| CN107301996B (en) * | 2017-07-21 | 2023-11-28 | 北京燕东微电子有限公司 | Transient voltage suppressor and method of manufacturing the same |
| CN107527907B (en) * | 2017-08-31 | 2024-04-09 | 北京燕东微电子有限公司 | Transient voltage suppressor and method of manufacturing the same |
| CN116469940A (en) * | 2023-06-20 | 2023-07-21 | 西安矽源半导体有限公司 | Buried layer zener diode and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6867436B1 (en) * | 2003-08-05 | 2005-03-15 | Protek Devices, Lp | Transient voltage suppression device |
| CN101527324A (en) * | 2008-12-08 | 2009-09-09 | 上海长园维安微电子有限公司 | Two-way low-voltage punch-through transient voltage suppression diode and manufacturing method thereof |
| CN101853853A (en) * | 2009-03-31 | 2010-10-06 | 万国半导体有限公司 | The semiconductor controlled rectifier that has low electric capacity and forward drop and exhaust is as the Transient Voltage Suppressor of steering diode |
| CN102437156A (en) * | 2011-12-13 | 2012-05-02 | 杭州士兰集成电路有限公司 | Ultralow capacitance transient voltage suppression device and manufacturing method thereof |
-
2012
- 2012-05-18 CN CN201210161049.6A patent/CN103426879B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6867436B1 (en) * | 2003-08-05 | 2005-03-15 | Protek Devices, Lp | Transient voltage suppression device |
| CN101527324A (en) * | 2008-12-08 | 2009-09-09 | 上海长园维安微电子有限公司 | Two-way low-voltage punch-through transient voltage suppression diode and manufacturing method thereof |
| CN101853853A (en) * | 2009-03-31 | 2010-10-06 | 万国半导体有限公司 | The semiconductor controlled rectifier that has low electric capacity and forward drop and exhaust is as the Transient Voltage Suppressor of steering diode |
| CN102437156A (en) * | 2011-12-13 | 2012-05-02 | 杭州士兰集成电路有限公司 | Ultralow capacitance transient voltage suppression device and manufacturing method thereof |
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