CN103426815A - Semiconductor reflow processing for feature fill - Google Patents
Semiconductor reflow processing for feature fill Download PDFInfo
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- CN103426815A CN103426815A CN2013101504839A CN201310150483A CN103426815A CN 103426815 A CN103426815 A CN 103426815A CN 2013101504839 A CN2013101504839 A CN 2013101504839A CN 201310150483 A CN201310150483 A CN 201310150483A CN 103426815 A CN103426815 A CN 103426815A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Abstract
A method for at least partially filling a feature on a workpiece generally includes obtaining a workpiece including a feature; depositing a first conformal conductive layer in the feature; and thermally treating the workpiece to reflow the first conformal conductive layer in the feature.
Description
Technical field
Present disclosure for the parts at microelectronic workpiece (for example relates to, groove and via hole (via), particularly inlay groove and via hole in (Damascene) application) in electrochemical deposition electric conducting material (metal for example, for example, the method alloy of copper (Cu), cobalt (Co), nickel (Ni), gold (Au), silver (Ag), manganese (Mn), tin (Sn), aluminium (Al) and above each thing).
Background technology
Integrated circuit is formed in semi-conducting material and covers the interconnection integral body of the device within the dielectric material of semiconductor material surface.The device that can be formed in semiconductor comprises MOS transistor, bipolar transistor, diode and diffused resistor.The device that can be formed within dielectric comprises thin film resistor and capacitor.Device is by being formed on the conductor path interconnection within dielectric.Usually, there is the two-stage of continuous grade or the conductor path more than two-stage separated by dielectric layer and be used as interconnection.In current practice, cupric oxide and silica are respectively used to conductor and dielectric usually.
Deposit in copper interconnect (deposit) generally includes dielectric layer, barrier layer, kind crystal layer, copper is filled and copper covers (cap).Because copper is easy to be diffused in dielectric material, so barrier layer is for separating copper deposit and dielectric material.However, it should be understood that except can not needing barrier layer for copper removal, for other metal interconnected bodies, also can not need barrier layer.Barrier layer consists of refractory metal or fire resistant compound usually, for example, and titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN) etc.Other suitable barrier materials can comprise manganese (Mn) and nitrogenized manganese (MnN).Usually use the deposition technique that is called physical vapor deposition (PVD) to form barrier layer, but also can for example, by using other deposition techniques (, chemical vapor deposition (CVD) or ald (ALD)), form barrier layer.
Planting crystal layer can be deposited on barrier layer.Yet, will also be understood that, directly on barrier layer, (direct on barrier) (DOB) deposits also in the scope of present disclosure, described directly on barrier layer (DOB) deposition for example the barrier layer formed by alloy or codeposition (co-deposited) metal and the those skilled in the art known and/or other barrier layers of using on deposition, interconnecting metal can be deposited on the described barrier layer consisted of alloy or codeposition metal and not need independent kind crystal layer, described interconnecting metal is titanium ruthenium (TiRu) for example, tantalum ruthenium (TaRu), tungsten ruthenium (WRu).
In a unrestricted example, plant crystal layer and can be copper kind crystal layer.As another unrestricted example, plant crystal layer and can be copper alloy kind crystal layer, for example, cupromanganese, copper-cobalt alloy or corronil.In the situation that, during copper is deposited on to parts, for kind of a crystal layer, several exemplary selections are arranged.The first, plant crystal layer and can be PVD copper kind crystal layer.Referring to for example for explanation, comprising Fig. 3 of the technique of the brilliant deposition of PVD copper kind.Planting crystal layer also can for example, form by using other deposition techniques (CVD or ALD).
The second, plant crystal layer and can be stacked film, for example, laying and PVD kind crystal layer.Laying is to be used between barrier layer and PVD kind crystalline substance the material of alleviating the brilliant problem of discontinuous kind and improving the brilliant adhesion of PVD kind.Liner is noble metal normally, for example ruthenium (Ru), platinum (Pt), palladium (Pd) and osmium (Os), but this series also can comprise cobalt (Co) and nickel (Ni).Current, CVD Ru and CVD Co are common liners; Yet laying also can for example, form by using other deposition techniques (, ALD or PVD).
The 3rd, plant crystal layer and can be secondary kind crystal layer.Secondary kind crystal layer is similar to laying, be because secondary kind crystal layer for example, is formed by noble metal (Ru, Pt, Pd and Os) usually, but this series also can comprise Co and Ni and modal CVD Ru and CVD Co.(as kind of crystal layer and laying, secondary kind crystal layer also can for example, form by using other deposition techniques (ALD or PVD)).Difference is: secondary kind crystal layer is as kind of a crystal layer, and laying is the intermediate layer between barrier layer and PVD kind crystalline substance.Referring to for example for explanation, comprising Fig. 5 and Fig. 6 of the technique of the brilliant deposition of secondary kind, after the brilliant deposition of described secondary kind, be respectively the brilliant deposition of ECD kind in Fig. 5, as described below, and the deposition of the quick flashing thing in Fig. 6 (flash deposition).(" quick flashing thing " deposition is mainly the upper place, bottom that reaches, the zone (field) at parts, significantly is not deposited on component side walls).
After according to an example deposition kind crystal layer in above-mentioned example, parts can comprise that kind of crystal layer strengthens (SLE) layer, and it is the thin layer of plated metal (for example, the copper of the about 2nm of thickness) that described kind of crystal layer strengthens (SLE) layer.The SLE layer is also referred to as electrochemical deposition kind brilliant (or ECD kind crystalline substance).Referring to for example for explanation, comprising Fig. 4 of the technique of the brilliant deposition of PVD kind and the brilliant deposition of ECD kind.Referring to for example for explanation, comprising Fig. 5 of the technique of the brilliant deposition of secondary kind and the brilliant deposition of ECD kind.As Fig. 4 and seen in fig. 5, ECD kind crystalline substance can be conformal deposited (conformally deposited) layer.
Usually use alkaline chemical (basic chemistry) the deposition ECD copper kind crystalline substance that comprises the cupri ethylene diamine that concentration is very low (EDA) complex compound.Also can use other copper complexs (for example, copper citrate, cupric tartrate and urea copper etc.) depositions ECD copper kind crystalline substance, and can be approximately 2 to approximately 11, approximately 3 in about 10 pH scope or approximately 4 to deposition ECD copper kind crystalline substance in about 10 pH scope.
After according to an example deposition kind crystal layer in above-mentioned example (described kind of crystal layer also can comprise optional ECD kind crystalline substance), for example, can use the acid deposition chemicals to carry out traditional ECD in parts and fill and cover.Traditional ECD copper acidic chemical can comprise for example copper sulphate, sulfuric acid, methanesulfonic acid, hydrochloric acid and organic additive (for example, promoter (accelerator), inhibitor (suppressor) and leveling agent (leveler)).The electrochemical deposition of having found copper is the most economical mode of deposited copper metal layer.Except feasible economically, the ECD deposition technique provides in fact from bottom to top (for example, non-conformal) metal filled, described metal filled mechanically with electric on be applicable to interconnection structure.
Traditional ECD fills, and especially the ECD in widget fills, and can cause interconnecting than low quality.For instance, traditional E CD copper is filled and can be produced space, especially in size is less than the parts of 30nm, produces space.As an example of the lash types of using traditional ECD deposition to form, but the opening pinch off of parts (pinch off).The space of other types also can produce because use traditional ECD copper fill process in widget.Described space and sedimental other intrinsic properties that use traditional ECD copper to fill formation can increase the resistance of interconnection body, thereby reduce the electric property of device and the reliability of copper interconnect is degenerated.
Therefore, exist to the improvement for parts, the needs of the metal filled technique of tight in fact.Described tight in fact is metal filled be can be used in widget, for example, has the parts of the opening size that is less than 30nm.
Summary of the invention
Thereby the selection that provides this summary of the invention to introduce in simplified form design, further describe described design hereinafter in embodiment.Content of the present invention is not intended to identify the key feature of object required for protection, also is not intended to the auxiliary content as the scope of determining object required for protection.
According to an execution mode of present disclosure, provide a kind of for filling at least partly the method for the parts on workpiece.Method generally includes following steps: obtain the workpiece that comprises parts; The first conformal electrically conductive layers is deposited in parts; With heat treated part so that the first conformal electrically conductive layers in parts anti-stream (reflow).
According to another execution mode of present disclosure, provide a kind of for filling at least partly the method for the parts on workpiece.Method generally includes following steps: obtain the workpiece that comprises parts; By barrier deposition in parts; With after barrier layer by the first conductive layer deposition in parts, wherein the first conductive layer is kind of a crystal layer.Method is further comprising the steps: after the first conductive layer by the second conductive layer deposition in parts, wherein the second conductive layer is conformal electrically conductive layers; With make workpiece annealing so that the second conductive layer anti-stream in parts.
Another execution mode according to present disclosure, provide a kind of workpiece.Workpiece generally includes at least one parts with the size that is less than 30nm and the void-free in fact conductive layer in parts.
The accompanying drawing explanation
When considering by reference to the accompanying drawings, will be easier to understand aforementioned aspect and many advantages of following of present disclosure by reference to following detailed description, wherein:
Fig. 1 describes the treatment step of present disclosure illustrative embodiments and the indicative flowchart of example feature evolution;
Fig. 2 is the exemplary process that can use in conjunction with prior art technique and the comparison diagram of technique according to the present disclosure execution mode;
Fig. 3 describes to use the treatment step of the main mosaic technology of prior art and the indicative flowchart of example feature evolution, comprises barrier deposition, plants brilliant deposition and traditional E CD filling and cover deposition;
Fig. 4 is for describing to use prior art SLE(also referred to as ECD kind crystalline substance) treatment step of technique and the indicative flowchart of example feature evolution, comprise barrier deposition, kind crystalline substance deposition, the brilliant deposition of ECD kind and traditional ECD filling and covering deposition;
Fig. 5 describes to use the treatment step of the brilliant technique of prior art ECD kind and the indicative flowchart of example feature evolution, comprises that barrier deposition, the brilliant deposition of secondary kind, the brilliant deposition of ECD kind and traditional E CD fill and cover deposition;
Fig. 6 describes to have the treatment step of prior art deposition of the brilliant process aspect of secondary kind of flash layer and the indicative flowchart of example feature evolution, comprises that barrier deposition, the brilliant deposition of secondary kind, quick flashing thing deposition and traditional ECD fill and cover deposition;
Fig. 7 describes the treatment step of some illustrative embodiments of present disclosure and the indicative flowchart of example feature evolution;
The chart drawing that Fig. 8 is the exemplary process that deposits in mosaic component for various exemplary wafer according to present disclosure embodiment, described mosaic component has the parts diameter of about 30nm;
The chart drawing that Fig. 9 is 120 microns long line resistor (line resistor) resistance result of obtaining in the exemplary wafer described from Fig. 8;
The chart drawing that Figure 10 is the line resistor resistance result of 1 meter long that obtains in the exemplary wafer described from Fig. 8;
The chart drawing that Figure 11 postpones result for the resistor capacitance-resistance of 1 meter long obtained in the exemplary wafer of describing from Fig. 8; With
Figure 12 comprises transmission electron microscope (TEM) image for the gap-fill of tight in fact of the mosaic component according to the present disclosure execution mode, and described mosaic component has the parts diameter of about 30nm.
Embodiment
The execution mode of present disclosure relates to workpiece (for example semiconductor wafer), for the treatment of device or the processing components of workpiece and the method for processing described workpiece.Term workpiece, wafer or semiconductor wafer mean any smooth medium or object, comprise that semiconductor wafer and other substrates or wafer, glass, mask and optics or storage medium, MEMS substrate or any other have the workpiece of microelectronics, micromechanics or micro electro mechanical device.
Technique as herein described will be for metal deposition or the metal alloy deposition of workpiece component, and described parts comprise groove and via hole.In an execution mode of present disclosure, technique can be used in widget, for example has the parts of the parts diameter that is less than 30nm.However, it should be understood that technique as herein described is applicable to any part dimension.The size of discussing in the application is characteristic size after the etching of the top open part of parts.Technique as herein described can be applicable to copper, cobalt, nickel, gold, silver, manganese, tin, aluminium and the alloy deposition of the various forms in damascene applications for example.In the execution mode of present disclosure, mosaic component is optional freely has the group that the parts of following size form: be less than 30nm, about 5nm to be less than 30nm, about 10nm to be less than 30nm, about 15nm to about 20nm, about 20nm to being less than 30nm, be less than 20nm, be less than 10nm and about 5nm arrives about 10nm.
Should be understood that descriptive term used herein " microfeature workpieces " reaches " workpiece " and comprises all structures and the layer that before in processing procedure, has deposited and be formed on set point, and be not limited in those structures depicted in figure 1 and layer.
Should be understood that and for example also can revise technique as herein described, for the metal or metal alloy deposition in high-aspect-ratio parts (, penetrating the via hole in via hole (TSV) parts of silicon).
Although usually be described as in this application the metal deposition, should be understood that term " metal " also takes into account metal alloy.Described metal and metal alloy can be used for forming kind of crystal layer or for filling component wholly or in part.The exemplary copper alloy can include but not limited to copper manganese and copper aluminium.As unrestricted example, with main alloying metal (such as Cu, Co, Ni, Ag, Au etc.), to compare, the alloying component proportioning can be approximately 0.5% in the scope of about 6% less important alloying metal.
As mentioned above, the tradition manufacture of metal interconnected body can comprise barrier layer suitably is deposited on dielectric material to prevent that metal is diffused in dielectric material.Suitable barrier layer can comprise for example Ta, Ti, TiN, TaN, Mn or MnN.Suitable barrier deposition method can comprise PVD, ALD and CVD; Yet PVD is the common technology for barrier deposition.Barrier layer is generally used for making copper or copper alloy and dielectric material to separate; However, it should be understood that in the situation that other metal interconnected bodies, diffusion may not be problem and can not need barrier layer.
After barrier deposition, can be optionally to plant the crystal layer deposition.In the situation that, during metal is deposited on to parts, for kind of a crystal layer, several selections are arranged.As mentioned above, plant crystal layer and can be (1) kind crystal layer (as unrestricted example, being PVD copper kind crystal layer).Plant crystal layer and can be metal level, for example, the alloy of copper, cobalt, nickel, gold, silver, manganese, tin, aluminium, ruthenium and above each thing.Plant crystal layer and also can be (2) laying and the stacked film of planting crystal layer (as unrestricted example, being CVD Ru laying and PVD copper kind crystal layer), or (3) secondary kind crystal layer (as unrestricted example, being CVD or ALD Ru secondary kind crystal layer).However, it should be understood that present disclosure also takes into account the additive method of the described exemplary kind of crystal layer of deposition.
As discussed above, laying is to be used in barrier layer and to plant between crystal layer to alleviate the brilliant problem of discontinuous kind and improve kind of the material of crystal layer adhesion.Liner is noble metal normally, for example Ru, Pt, Pd and Os, but described series also can comprise Co and Ni.Current, CVD Ru and CVD Co are common liners; Yet laying also can for example, form by using other deposition techniques (, PVD or ALD).For damascene applications, the thickness of laying can be approximately
Arrive
Scope in.
Equally as discussed above, secondary kind crystal layer is similar to laying, be because secondary kind crystal layer for example, is formed by noble metal (Ru, Pt, Pd and Os) usually, but this series also can comprise Co and Ni and modal CVD Ru and CVD Co.Difference is: secondary kind crystal layer is as kind of a crystal layer, and laying is between barrier layer and plants the intermediate layer between crystal layer.Secondary kind crystal layer also can for example, form by using other deposition techniques (PVD or ALD).
Can be at forming gas environment (forming gas) (for example, the hydrogen that 3%-5% is arranged in the hydrogen of 3%-5% or helium is arranged in nitrogen) in, between approximately 100 ℃ to heat treatment or annealed liners or the brilliant deposit of secondary kind at the about temperature between 500 ℃, removing any oxide on surface, make secondary kind crystal layer or laying fine and close and improve sedimental surface nature.Can pass through at gaseous nitrogen (N
2Gas) dipping comes other passivation liner or the brilliant deposit of secondary kind or in other passivation environment, to prevent surface oxidation.The passivation of liner or secondary kind crystalline substance is described in No. 8357599th, the United States Patent (USP) of on January 22nd, 2013 issue.
(for example depositing kind of crystal layer, a unrestricted example in the unrestricted example of PVD copper kind crystalline substance, the PVD copper kind crystalline substance that comprises CVD Ru liner or CVD Ru secondary kind crystalline substance or another plated metal or metal alloy, layer combination or deposition technique), after, parts can be included in the conformal metal level after kind of crystal layer.Yet, but should also be understood that conformal metal level Direct precipitation, on barrier layer, do not plant crystal layer.
In an execution mode of present disclosure, use the brilliant process deposits conforma layer of ECD kind, then can use the technique that is called as ECD kind brilliant " adding " deposition (or ECD kind brilliant " adding ") that comprises heat treatment step to revise described conforma layer.In other execution modes of present disclosure, can use CVD, ALD or other techniques of deposition conforma layers, then can make conforma layer stand heat treatment step.According to the execution mode of present disclosure, conforma layer is that " flowable " maybe can move through heat-treated or annealing the time.
In this execution mode, ECD kind brilliant " adding " typically refers to the brilliant deposition of ECD metal kind and adds heat treatment step (for example annealing steps).In an execution mode of present disclosure, heat treatment step can cause some or all to plant the anti-stream of brilliant deposition.In ECD kind crystal layer, the increase of temperature contributes to the mobility of layer Atom and strengthens the ability of atom interstitital texture.
With traditional E CD metal filled (use acidic chemical), compare, ECD kind brilliant " adding " deposition is similar to the brilliant deposition of ECD kind (use alkaline chemical), but has increased heat treatment step.In addition, replace only deposition kind of crystal layer, can carry out ECD kind brilliant " adding " in order to be partially filled or complete filling component.Can realize by brilliant " adding " technique of ECD kind the essence tight filling of widget, (image of filling referring to the essence tight in widget in Figure 12) as described in greater detail below.
The chemicals used at the ECD chamber for ECD kind brilliant " adding " deposition can comprise alkaline chemical, for example, at the about Cu (ethylenediamine) 2 under 8 to the pH in about 11 scope, in an execution mode of present disclosure, pH is approximately 8 to approximately 10, and pH is approximately 9.3 in an execution mode of present disclosure.However, it should be understood that the acidic chemical that uses suitable organic additive also can be used for realizing the brilliant deposition of conformal ECD kind.
After the brilliant deposition of ECD kind, then can make workpiece stand rotation (spin), rinse and dry (SRD) technique or other cleaning procedures.Then enough warm so that plant heating ECD kind crystalline substance at the temperature of brilliant anti-stream, but this temperature is not overheated so that workpiece or workpiece on component wear or degeneration.For instance, temperature can approximately 100 ℃ in the about scope of 500 ℃ with the brilliant anti-stream of the kind for parts.Suitable heat treatment temperature or annealing temperature approximately 100 ℃ in the about scope of 500 ℃, and availablely can maintain approximately 200 ℃ in the about scope of 400 ℃ and at least maintain approximately 250 ℃ and realize described suitable heat treatment temperature or annealing temperature to the about interior equipment of temperature range of 350 ℃ continuing temperature.
Can use forming gas or inert gas, pure hydrogen or reducibility gas (for example, ammonia (NH
3)) execution Technology for Heating Processing or annealing process.During anti-stream, deposition shape changes, and makes metal deposit can collect (pool) bottom at parts, as shown in Figure 7.Except the anti-stream during Technology for Heating Processing, metal deposit also can produce larger crystal grain and reduce the film resistor coefficient.Inert gas can be used for the workpiece after cooling heating.
Complete ECD kind brilliant " add " deposition and Technology for Heating Processing to be partially filled or fully after filling component, traditional acidic chemical can be used for gap-fill and covered the depositing operation deposited.The acidic chemical metal deposition step is generally used for filling macrostructure and for maintaining the required suitable film thickness of follow-up polishing step, because described acidic chemical metal deposition step, normally than the brilliant technique of ECD kind technique faster, is saved time and reduces processing cost.
As Fig. 1 and seen in fig. 7, can repeat the brilliant deposition of ECD kind and anti-flow step to have guaranteed with the brilliant filling component of ECD kind.With regard to that, technique as herein described can comprise the brilliant deposition of one or more ECD kind, clean (for example SDR) and heat treatment cycle.
With reference to Fig. 1, the example components of having described anti-stream technique 100 and having been produced by described anti-stream technique.Workpiece 112 can be the dielectric material on the crystalline silicon workpiece that contains at least one parts 122 in the exemplary embodiment.In illustrative steps 102, be lined with barrier layer 114 in parts 122 and plant crystal layer 115.In illustrative steps 104, the parts 122 of workpiece 112 have received the brilliant material 116 of one deck ECD kind on kind of crystal layer 115.In exemplary annealing steps 106, under proper temperature, make workpiece anneal to induce exemplary anti-flow step 108 to promote to be partially filled or to fill fully.During annealing steps, the brilliant material 116 of ECD kind flows in parts 122 to form filler 118, simultaneously workpiece 112 or be included in the situation of adverse effect of the parts in workpiece 112 and make this adverse effect minimum.In the exemplary embodiment, can repeat the brilliant deposition step 104 of ECD kind, annealing steps 106 and anti-flow step 108 to obtain the desired characteristic of filling 118.The number of times of repeating step can be depending on structure.Once the desired size that filler 118 reaches, usage example covering step 110 completes additional materials 120 is deposited on to the technique on parts, thinks that extra workpiece 112 is processed to prepare.
Referring now to Fig. 2, the handling process example is provided, wherein the execution mode of present disclosure can be used and be dissolved in other surface of the work depositing operations in conjunction with other surface of the work depositing operations.To at first the technique of previous exploitation be described.The first, TSV technique comprises barrier layer, plants the deposition of crystal layer and traditional E CD filling.Brilliant (also referred to as the SLE) technique of the second, ECD kind comprises barrier layer, plants the deposition that crystal layer, ECD kind crystal layer and traditional E CD fill.The 3rd, follow brilliant (SLE) technique of ECD kind of liner to comprise the deposition that barrier layer, laying, kind crystal layer, ECD kind crystal layer and traditional E CD fill.The 4th, follow brilliant (SLE) technique of ECD kind of secondary kind crystalline substance to comprise the deposition that barrier layer, secondary kind crystal layer, ECD kind crystal layer and traditional E CD fill.The 5th, follow brilliant (SLE) technique of secondary kind ECD kind brilliant and the quick flashing thing to comprise the deposition that barrier layer, secondary kind crystal layer, flash layer, ECD kind crystal layer and traditional E CD fill.The 6th, brilliant (DOB) technique of ECD kind comprises the deposition that barrier layer, ECD kind crystal layer and traditional E CD fill.Brilliant (DOB) technique of described ECD kind is that DOB technique is because do not deposit secondary kind crystalline substance, liner or plant crystal layer; On the contrary, ECD kind crystal layer Direct precipitation is on (platable) barrier layer of electrodepositable.
Still, with reference to figure 2, now the technique according to the present disclosure execution mode will be described.The 7th, brilliant additional (DOB) technique of ECD kind comprises the deposition that barrier layer, brilliant " adding " deposit of ECD kind and traditional E CD fill and/or cover.Identical with above-mentioned the 6th example, brilliant additional (DOB) technique of described ECD kind is also DOB technique, is because do not deposit secondary kind crystalline substance, liner or plant crystal layer; On the contrary, ECD kind crystal layer Direct precipitation is on the barrier layer of electrodepositable.The 8th, the brilliant additional process of ECD kind comprises the deposition that barrier layer, secondary kind crystal layer, brilliant " adding " deposit of ECD kind and traditional E CD fill and/or cover.The 9th, do not have the brilliant additional process of ECD kind of ECD to comprise brilliant " adding " the sedimental deposition of barrier layer, secondary kind crystal layer and ECD kind.The tenth, do not have the brilliant additional process of ECD kind of secondary kind crystalline substance to comprise the deposition that barrier layer, kind crystal layer, brilliant " adding " deposit of ECD kind and traditional E CD fill and/or cover.The 11, follow liner and plant the deposition that the brilliant additional process of brilliant ECD kind comprises that barrier layer, the beds of precipitation, kind crystal layer, brilliant " adding " deposit of ECD kind and traditional E CD fill and/or cover.
With reference to figure 7, provide another illustrative processes according to the present disclosure execution mode.In first step, before the brilliant step of ECD kind, heat treatment or annealing have the workpiece of barrier layer and secondary kind crystal layer to remove any oxide on surface, make the deposit densification and improve sedimental surface nature.Kind crystal layer shown in Fig. 7 is secondary kind crystal layer, but should be understood that described secondary kind crystal layer also can be the stacked film of kind of crystal layer or laying and kind crystal layer.Suitable heat-treat condition or annealing conditions can include may be in forming gas or pure hydrogen between approximately 200 ℃ last approximately one (1) minute to approximately ten (10) minutes to the about temperature between 400 ℃.As described above, can for example, at inert gas (, N
2, argon gas (Ar) or helium (He)) in heat treated part alternatively.Also can use reducibility gas, for example, ammonia (NH
3).
In second step, workpiece transfer is used for to the conformal deposited of ECD kind crystal layer to deposition chambers.The thickness of institute's deposit film changes according to desirable properties and the characteristic size of metal deposit.
In third step, rotational workpieces, use deionization (DI) water rinse workpiece dry (SRD) workpiece, to clean workpiece.
In the 4th step, heat treatment or annealing workpiece at the temperature in the scope of 200 ℃ to 400 ℃ flow to parts so that metal is counter.
In the 5th step, workpiece can experience the order that has of step 2, step 3 and step 4 to be processed again, until obtain the expectation of workpiece upper-part, fills profile.
In the 6th step, make workpiece stand the thickness that traditional ECD acidic chemical deposits to reach expectation.Then, for subsequent treatment is ready to workpiece, described subsequent treatment can comprise additional heat treatment, chemico-mechanical polishing and other technique.
The alternate embodiments of technique can comprise that this paper has described the modification of step, and described step, combination and permutation can incorporate in addition for following additional step.Imagine in this disclosure, can have or do not have organic additive (for example, inhibitor, promoter and/or leveling agent) for example approximately 4 to approximately 10, approximately 3 to approximately 10 or approximately 2 in the alkaline solution in about 11 pH scope or acid solution, carrying out conformal " planting brilliant " deposition.Can use a plurality of deposition steps, clean (for example SRD) step and heat treatment step or annealing steps to carry out anti-stream, or can be in single step then by the heat treatment under proper temperature or annealing is counter flows.
ECD kind brilliant " adding " deposition is very important to the exploitation of widget, and this is because heat treatment step or annealing steps and anti-flow step provide the void-free kind of essence brilliant deposition.As hereinafter be described in more detail, the space in parts forms the reliability degeneration that increases resistance (reducing the electric property of device) and make to interconnect body.
By using technique as herein described to realize other advantages.At this on the one hand, (for example,, by Applied Materials, Inc. manufactures individual tool
Electrochemical deposition, clean (for example SRD) and heat treatment or temper remover) can be used for the brilliant deposition step of ECD kind (or the brilliant deposition steps of a plurality of ECD kinds when repeating), cleaning (or a plurality of cleanings when repeating), heat treatment step (or a plurality of heat treatment steps when repeating) and for final ECD step.In addition, result shows uses technique as herein described to the void-free gap-fill of the essence of widget, causes lower resistance and capacitance-resistance (RC) length of delay.In addition, technique as herein described provides fills the approximate ability that is less than other widget of level of about 30nm, yet uses traditional handicraft possibly can't realize filling.It is also favourable in the parts that are greater than 30nm that ECD kind brilliant " adding " is deposited on.
As described above, can apply one or more layer of ECD kind crystalline substance, then one or more layer of described ECD kind crystalline substance is exposed to the rising temperature to fill darker parts or the parts of high-aspect-ratio.With reference to Fig. 8, two brilliant additional process (comprising annealing steps) (wafer 4 and wafer 5) of exemplary ECD kind are provided, with the brilliant techniques (there is no annealing steps) of two traditional E CD kinds [wafer 1 and wafer 7] of the deposition of the mosaic component of parts diameter for thering is about 30nm, compare.Arrive Figure 11 with reference to Fig. 9, result shows, with the single step of ECD kind crystalline substance (, there is no annealing steps) compare, the increment deposition (incremental deposition) of ECD kind crystalline substance in mosaic component causes resistance and capacitance-resistance (RC) length of delay to reduce, and after some of them or whole deposition step, is annealing steps.
All wafers 1, wafer 4, wafer 5 and wafer 7 comprise following initial treatment condition: deposition
ALDTaN barrier layer, then deposition
The kind crystal layer of CVD Ru (secondary kind crystalline substance), and then make workpiece stand annealing under 300 ℃ and the nitrogen passivation of 10 minutes.
Then pass through single step wafer electroplating 1 and the wafer 7 of the ECD copper kind crystalline substance under 2.1amp-min and 0.5amp-min respectively, then use traditional acid ECD copper deposition process that wafer 1 and wafer 7 are completed and fill and cover.Synthetic workpiece produces thick ECD copper kind brilliant (wafer 1) and thin ECD copper kind brilliant (wafer 7).
Make wafer 4 and wafer 5 stand brilliant " adding " condition of ECD kind.Wafer 4 comprises the brilliant step of three ECD copper kinds, each step is under 0.7amp-min, 300 ℃ of annealing are wherein arranged and not annealing after third step after each step in the first two step, then use traditional acid ECD copper deposition process to complete and fill and cover.The micro-image be associated with the wafer 4 with the part dimension that approaches 30nm is provided in Figure 12.Although not annealing, should be understood that the final annealing step is also in the scope of present disclosure after third step.
To Figure 11, provide comparison resistance and the RC delayed data of wafer 1, wafer 4, wafer 5 and wafer 7 referring now to Fig. 9.As at Fig. 9 to visible in Figure 11, with the workpiece (wafer 1 and wafer 7) that the technology of using previous exploitation forms, compare, the workpiece (wafer 4 and wafer 5) that uses ECD kind brilliant " adding " to form according to methods described herein has significantly reduced resistance and resistance-type/condenser type (RC) postpones.
With reference to Fig. 9 and Figure 10, with using the brilliant workpiece that forms but do not have ECD kind crystalline substance to add anneal cycles of ECD kind, compare, the workpiece formed according to the present disclosure execution mode realizes that the resistance value in following scope reduces: 0 to approximately 40%, be greater than 0 to approximately 30%, be greater than 0 to approximately 20%, approximately 10% arriving approximately 20% and approximately 10% and arrive approximately 15%.
With reference to Figure 11, form but do not have the workpiece of the brilliant additional anneal circulation of ECD kind to compare with use ECD kind is brilliant, realize that according to the workpiece of present disclosure execution mode formation the RC length of delay reduces.Dielectric low damage or not damage between low RC postpones to cause the low karat gold in parts is belonged to.
Although illustrated and described illustrated embodiment, will understand, can make in this article various variations in the situation that do not deviate from spirit and the scope of present disclosure.
Claims (20)
1. one kind for filling at least partly the method for the parts on workpiece, said method comprising the steps of:
(a) obtain the workpiece that comprises parts;
(b) the first conformal electrically conductive layers is deposited in described parts; With
(c) the described workpiece of heat treatment so that described the first conformal electrically conductive layers in described parts anti-stream.
2. method according to claim 1, wherein the step of the described workpiece of heat treatment reduces the space of described parts in filling.
3. method according to claim 1, described method is further comprising the steps: before described the first conformal electrically conductive layers of deposition, by barrier deposition in described parts.
4. method according to claim 1, described method is further comprising the steps: before described the first conformal electrically conductive layers of deposition, current conducting seed crystal layer is deposited in described parts.
5. method according to claim 4, wherein for the metal choosing group that freely following each thing forms of described kind of crystal layer: the alloy of copper, cobalt, nickel, gold, silver, manganese, tin, aluminium, ruthenium and above each thing.
6. method according to claim 1, wherein for the metal choosing group that freely following each thing forms of described the first conformal electrically conductive layers: the alloy of copper, cobalt, nickel, gold, silver, manganese, tin, aluminium and above each thing.
7. method according to claim 1, wherein carry out described the first conformal electrically conductive layers of electrochemical deposition by chemical vapour deposition (CVD) or by ald.
8. method according to claim 1, described method is further comprising the steps: deposit the second conformal electrically conductive layers after described the first conformal electrically conductive layers, and the described workpiece of heat treatment is so that anti-stream of described the second conformal electrically conductive layers.
9. method according to claim 8, described method is further comprising the steps: deposit the 3rd conformal electrically conductive layers after described the second conformal electrically conductive layers, and the described workpiece of heat treatment is so that the described the 3rd conformal electrically conductive layers is counter flows.
10. method according to claim 4, the wherein said kind of crystal layer choosing group that freely following each thing forms: plant brilliant, the secondary kind is brilliant and plant stacked film brilliant and liner.
11. method according to claim 1, wherein the first conformal electrically conductive layers of anti-stream partially or fully fill described parts.
12. method according to claim 1, wherein use and comprise that at least one copper complex formazan chemicals deposits described the first conformal electrically conductive layers, the group that described at least one copper complex selects free cupri ethylene diamine, copper citrate, cupric tartrate and urea copper to form.
13. method according to claim 1, described method is further comprising the steps: by cap layer deposition on the first conformal electrically conductive layers of anti-stream.
14. method according to claim 13, the wherein described cover layer of deposition in acidic chemical.
15. method according to claim 1, wherein the heat treatment temperature choosing group that freely temperature in following scope forms: approximately 100 ℃ in the about scope of 500 ℃, approximately 200 ℃ in the about scope of 400 ℃ and approximately 250 ℃ in the about scope of 350 ℃.
16. method according to claim 1, wherein the parts diameter is selected from the group that following each person forms: be less than 30nm, about 5nm to be less than 30nm, about 10nm to be less than 30nm, about 15nm to about 20nm, reach about 20nm to being less than 30nm, be less than 20nm, be less than 10nm and about 5nm arrives about 10nm.
17. method according to claim 1, wherein with the workpiece that step by the described workpiece of heat treatment does not form, compare, the resistance value that described heat treated part has the group that the freely following scope of choosing forms reduces: be greater than 0 to approximately 40%, be greater than 0 to approximately 30%, be greater than 0 to approximately 20%, approximately 10% arriving approximately 20% and approximately 10% and arrive approximately 15%.
18. method according to claim 3, wherein said the first conformal electrically conductive layers Direct precipitation is on described barrier layer.
19. the method for the parts at least part of filling workpiece said method comprising the steps of:
(a) obtain the workpiece that comprises parts;
(b) by barrier deposition in described parts;
(c) after described barrier layer by the first conductive layer deposition in described parts, wherein said the first conductive layer is kind of a crystal layer;
(d) after described the first conductive layer by the second conductive layer deposition in described parts, wherein said the second conductive layer is conformal electrically conductive layers; With
(e) make described workpiece annealing so that described the second conductive layer instead flows in described parts.
20. a workpiece, described workpiece comprises:
(a) at least one parts, described at least one parts have the size that is less than 30nm; With
(b) the void-free conductive layer of essence, the void-free conductive layer setting of described essence is put in described parts.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
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| US201261638851P | 2012-04-26 | 2012-04-26 | |
| US61/638,851 | 2012-04-26 | ||
| US13/801,786 US10665503B2 (en) | 2012-04-26 | 2013-03-13 | Semiconductor reflow processing for feature fill |
| US13/801,786 | 2013-03-13 |
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| CN103426815A true CN103426815A (en) | 2013-12-04 |
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| CN201310150483.9A Active CN103426815B (en) | 2012-04-26 | 2013-04-26 | Semiconductor reflow processing for component filling |
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| CN (1) | CN103426815B (en) |
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| CN105789180A (en) * | 2014-08-07 | 2016-07-20 | 财团法人工业技术研究院 | Semiconductor element, manufacturing method and stack structure thereof |
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| CN112352065A (en) * | 2018-06-30 | 2021-02-09 | 朗姆研究公司 | Zinc and doping for liner passivation and adhesion improved metal liners |
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| US10438846B2 (en) * | 2017-11-28 | 2019-10-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Physical vapor deposition process for semiconductor interconnection structures |
| KR102605619B1 (en) * | 2019-07-17 | 2023-11-23 | 삼성전자주식회사 | Semiconductor device comprising through substrate vias and method for manufacturing the same |
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Also Published As
| Publication number | Publication date |
|---|---|
| KR20130121042A (en) | 2013-11-05 |
| CN103426815B (en) | 2018-10-26 |
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